52 results about "Buffered oxide etch" patented technology

A conditioning disk and a conditioner for a chemical mechanical polishing (CMP) pad, and a method of fabricating, reworking, and cleaning the conditioning disk, are utilized to improve conditioning efficiency, and to reduce production expenses. The conditioning disk for a CMP pad is divided into regions defined by a size difference of abrasive grains formed on the body surface in each region of the conditioning disk. The method of fabricating the conditioning disk is performed by forming adhesive films for attaching the abrasive grains onto the body surface multiple times. In addition, a used conditioning disk may be reworked by detaching the abrasive grains from the body, and attaching new abrasive grains. A used conditioning disk can also be cleaned of by-products of the conditioning process by a cleaning method using a HF solution or BOE (buffered oxide etch) solution.

The invention provides a method for exposing a semiconductor substrate and an invalidation analysis method. The method comprises the following steps: providing a semiconductor sample; removing an oxidation layer between the semiconductor substrate and a semiconductor polycrystal layer with chemical solution; and removing the semiconductor polycrystal layer through ultrasonic oscillation and exposing the semiconductor substrate, wherein the semiconductor sample comprises the semiconductor substrate, the oxidation layer and the semiconductor polycrystal layer from bottom to top in sequence; and the chemical solution is buffer oxide etching solution or hydrofluoric acid. The method for exposing the semiconductor substrate and the invalidation analysis method solve the problem that the semiconductor substrate can be damaged by de-layering the semiconductor polycrystal layer and the oxidation layer above the semiconductor substrate by layers in the prior art.

A method of fabricating an array substrate includes forming a gate line and a gate electrode; forming a gate insulating layer, an intrinsic amorphous silicon layer, an inorganic material insulating layer and a heat transfer layer on the gate line and the gate electrode; irradiating a laser beam onto the heat transfer layer to crystallize the intrinsic amorphous silicon layer into a polycrystalline silicon layer; removing the heat transfer layer; patterning the inorganic insulating material layer using a buffered oxide etchant to form an etch-stopper corresponding to the gate electrode forming an impurity-doped amorphous silicon layer and a metal layer on the etch-stopper and the polycrystalline silicon layer; patterning the metal layer to form a data line, a source electrode and a drain electrode and forming a pixel electrode on the passivation layer.

A method of forming silicon carbide Schottky diode is disclosed. The processes required two photo-masks only. The processes are as follows: firstly, an n+-silicon carbide substrate having an n− silicon carbide drift layer is provided. Then a silicon layer is formed on the drift layer. An ion implant is carried out to dope the silicon layer. Afterward the doped silicon layer is patterned to define an active region. A thermal oxidation is then followed to form a thick oxide layer by oxidizing the silicon layer and form guard rings by using the doped silicon layer as a diffused source. The thin oxide layer on the drift layer is then removed by dilute HF dip or by BOE (buffer oxide etching) solution dip. Thereafter, a top metal layer is deposited and patterned to define as anode. After a backside layer removal, a metal layer served as cathode is formed.

A method and means for detection of oxidizing contamination in acid etching baths employed to etch silicon oxide layers from silicon substrates employed in silicon integrated circuit microelectronics fabrications. There is provided a silicon substrate having within a doped region formed employing ion implantation. The silicon substrate is immersed within a buffered oxide etch (BOE) acid bath, wherein the presence of an oxidizing contaminant correlates with an increase in the resistance of the doped region upon the removal of any silicon oxide layer on the silicon surface.

The invention provides a gate-oxide etching method and a multi-grid-electrode manufacturing method. The gate-oxide etching method includes controlling over-etching time of buffered oxide etch (BOE), enabling over-etching time of the BOE to be smaller than 30% of main etching time, and matching with concentration ratio of APM. According to the method, damage on surface of a lining can be reduced on the condition that the gate-oxide is completely etched. Meanwhile, the gate-oxide etching method is applied to the multi-grid-electrode manufacturing method, and defects of particulate matters can be reduced, so that quality of multi-grid-electrode components is greatly improved.

A method for manufacturing a high-transmittance optical filter for image display devices, which may include the steps of coating a photocatalytic compound on a transparent substrate to form a photocatalytic film, selectively exposing the photocatalytic film to light and growing a metal crystal thereon by plating to form a metal pattern, and selectively etching and removing the photocatalytic compound remaining on the transparent substrate using a buffered oxide etchant (BOE). According to the method, a high-transmittance, high-resolution and low-resistivity optical filter can be manufactured in a simple manner at low costs.

The invention provides a method for treating synthetic wastewater collected by several strands of semiconductor technology wastewater, wherein the synthetic wastewater does not contain the NH4F/HF buffered oxide etch solution wastewater (NH4F/F wastewater for short), but basically contains an oxidizing agent, organic and inorganic substances, and ammonia nitrogen impurities. Firstly, the synthetic wastewater is treated by an antioxidant; subsequently treated in the anaerobic microbial decomposition way, the impurities are partly decomposed; and then the wastewater is treated in the aerobic microbial decomposition way, the residual organic substances and the ammonia nitrogen impurities are furthermore decomposed, thus the recyclable or dischargeable wastewater is obtained. The method also comprises the steps of individually treating an NH4OH rinsing wastewater, a TMAH yellow light technology wastewater or the NH4F/F wastewater, and also comprises the treatment method of collecting the individually treated wastewaters into the synthetic wastewater.

Embodiments of the present invention describe a method and device of preventing delamination of semiconductor layers in a semiconductor device. The semiconductor device comprises a substrate with an interlayer dielectric (ILD). A protection layer is deposited on the ILD. Next, a getter layer is formed on the protection layer to remove any native oxides on the protection layer. A capping layer is then deposited on the getter layer to prevent oxidation of the getter layer. Next, a semiconductor layer is formed on the capping layer. An oxide layer is then deposited on the semiconductor layer. Subsequently, a buffered oxide etch solution is used to remove the oxide layer. By removing the native oxides on the protection layer, the getter layer prevents the reaction between the buffered oxide etch solution and the native oxides which may cause delamination of the semiconductor layer and protection layer.

Solutions of carbon nanotubes and methods for purifying the solutions are provided. The methods include mixing, for example, at least one complexing agents, at least one ionic species, and/or at least one buffer oxide etch (BOE) with a liquid medium containing carbon nanotubes and different types of contaminants, such as metal impurities, amorphous carbon, and/or silica particles, and performing a filtration process to the liquid medium so as to remove or reduce the contaminants in the liquid medium. As a result, carbon nanotube solutions of low contaminants are produced. In some embodiments, the solutions of this disclosure include a high concentration of carbon nanotubes and are substantially free from metal, amorphous carbon, and/or silica impurities.

The invention is directed towards methods and compositions for identifying the amount of hydrofluoric acid in a buffered oxide etching composition. In buffered oxide etching compositions it is very difficult to measure the amount of hydrofluoric acid because it has varying equilibriums and it is toxic so it hard to handle and sample. When used to manufacture microchips however, incorrect amounts of hydrofluoric acid will ruin those chips. The invention utilizes a unique method of spectrographically measuring the hydrofluoric acid when in contact with added chromogenic agents to obtain exact measurements that are accurate, immediate, and safe.

The invention relates to a preparation method of a BOE (Buffered Oxide Etch)-resistant metal mask, in particular to a preparation method of plating a BOE resistant metal mask layer on a quartz crystal. The method specifically comprises a washing step and a coating step. The method has the following obvious effects: (1) a BOE resisting process is performed with a single Cr/ Au mask layer; (2) problems such as surface undercutting, swelling and even falling off after the etching of an existing Cr/ Au mask layer are solved; (3) a transfer etching pattern of the single Cr/ Au mask layer is high in accuracy, and the accuracy can be controlled to be within 1 microns; and (4) the preparation processes are simple and easily controlled, the preparation cost is low, and mass production can be carried out.

The invention discloses a mixed-dimension Van der Waals heterojunction room temperature two-color infrared detector and a preparation method thereof. The preparation method of the device comprises the following steps of: etching double-sided polished Si/SiO2 by utilizing buffer oxide etching liquid prepared from hydrofluoric acid and ammonium fluoride in a certain proportion to form a Si window; and forming a PNP (NPN) heterostructure by non-destructively transferring a two-dimensional Van der Waals material heterojunction to the Si window by using a polypropylene carbonate film. Dual-band infrared signal detection is realized by using a photoelectric triode energy band structure, and meanwhile, crosstalk is reduced by using a Si material with high absorbance as a near-infrared photosensitive material and a long-wave-pass filter, so that the dual-band infrared response of the device is improved. The mixed-dimension Van der Waals heterojunction room temperature two-color infrared detector has the advantages that a three-dimensional thin film material and the two-dimensional Van der Waals material are combined, near-infrared/mid-infrared room temperature detection is achieved, the manufacturing cost is low, the process is simple, preparation is easy, the detection rate is high, and the working temperature is high.

The invention provides an MEMS microphone and a production method thereof. The microphone comprises a substrate with a first surface and a second surface opposite to the first surface; a capacitor structure positioned on the first surface of the substrate, wherein the capacitor structure comprises a cavity, fixed electrodes positioned in the cavity, a vibrating diaphragm opposite to the fixed electrodes, sound holes distributed at intervals in the fixed electrodes, and amplitude limiting structures positioned in the sound holes, wherein polycrystalline silicon spacing layers are arranged around the fixed electrode; and a back cavity positioned in the substrate, wherein the top of the back cavity is exposed from the second surface of the substrate, and the capacitor structure is exposed from the bottom of the back cavity. According to the MEMS microphone and the production method thereof provided by the invention, the problem that in the prior art, when oxide spacing layers are used forimproving APT performance, after a final buffer oxide etching technology, a side excavating phenomenon occurs in an area adjacent to the connection end of the fixed electrode due to siphonic effect brought by the oxide spacing layers is solved.

The present invention discloses a method for fabricating bipolar integrated circuits, wherein LOCOS technology is used to define the active regions needed by all elements so that the self-alignment of the associated layers can be realized, and implant resistor regions are also directly defined in the active regions by local oxide layers; after base regions have been driven in the wafer, the resistors are implanted into the wafer so that the cost of resistor photomasks can be saved; silicon nitride is adopted to be the material of the dielectric layers of the capacitors, and with the characteristic of a buffering oxide etchant that etches oxide faster than it etches silicon nitride, the conventional deposition sequence of the dielectric layer is changed so that the formation of the dielectric layer needs only a single photomask.

The invention provides an etching method for a laminated inorganic membrane, which combines dry etching and wet etching for etching of the laminated inorganic membrane. The method comprises the following steps: a patterned photoresist layer is firstly formed on the laminated inorganic membrane, the dry etching of the laminated inorganic membrane is carried out in a manner that the photoresist layer serves as a shielding layer, and the dry etching is stopped when a silicon oxide bottom layer at the bottommost layer of the laminated inorganic membrane is to be etched; and the wet etching is then carried out on the remaining silicon oxide bottom layer through a buffered oxide etch (BOE), so that via holes are formed in the laminated inorganic membrane corresponding to patterns of the photoresist layer. The method provided by the invention has the advantages that the uniformity of etching effects for various areas of a same substrate can be improved, so that the phenomenon in the prior art that a lower membrane is etched due to non-uniform etching of the various areas when the via holes, especially deep via holes, are formed in the laminated inorganic membrane is prevented.