329 results about "Etching selectivity" patented technology

The invention discloses an integrated circuit equipment data optimization monitoring system and method based on big data, and relates to the technical field of integrated circuit manufacturing. The method is used for solving the problems of insufficient multi-physical field monitoring, difficulty in abnormal traceability and lack of closed-loop control in plasma etching. A plasma sheath thickness inversion model and an etching selection ratio model are constructed by collecting radio frequency reflection phase, mass spectrum ion strength and wafer temperature data, and process parameter-plasma state dynamic coupling is established. Interference image distortion features and electron microscope size data are fused, micro-groove geometric parameters are analyzed, morphology instability risk indexes are generated, and nanoscale early warning is achieved. And designing a dual-channel fusion network, embedding a physical constraint attention mechanism, and generating an etching rate optimization instruction. On the basis of incremental learning, model parameters are updated online, a'monitoring-decision-feedback 'closed-loop system is formed, anomaly detection sensitivity and decision reliability are improved, and technical support is provided for intelligence of integrated circuit equipment.

A method of manufacturing a structure having multi metal layers includes: depositing a top metal layer on a bottom metal layer; forming a patterned photoresist on the top metal layer; etching the top and bottom metal layers through first hollow portions of the patterned photoresist to respectively form a top metal pattern and a bottom metal pattern; forming a second hollow portion in the patterned photoresist to expose a portion of the top metal pattern; etching the top metal pattern through the second hollow portion until a top surface portion of the bottom metal pattern is exposed by the etched top metal pattern, in which an etch selectivity of the top and bottom metal layers in the etching the top metal pattern is greater than 1.0; and anodizing the top surface portion to form an anodized segment of the bottom metal layer.

A bottom electrode is deposited on a substrate. A dielectric layer is deposited on the bottom electrode. One or more structures are patterned within the dielectric layer. A liner layer is deposited on top of the dielectric layer and the bottom electrode. A selectivity promotion layer is deposited on top of the liner layer. The selectivity promotion layer is etched to expose a top surface of the dielectric layer and a portion of the bottom electrode. A phase change memory material layer is deposited within a void of the one or more structures between the selectivity promotion layer.

Apparatuses and methods are provided. Some methods may include providing a substrate to a processing chamber, the substrate having a first material adjacent to and covering a surface of a second material, modifying a layer of the first material by flowing a first process gas onto the substrate and thereby creating a modified layer of the first material, removing the modified layer of the first material by flowing a second process gas onto the substrate, and converting, when the surface of the second material is uncovered via removal of the modified layer, the surface to a converted layer of the second material by flowing a third process gas onto the substrate, in which the first and second process gases are less reactive with the converted layer than with the first material and the second material.

A method of manufacturing a structure having anodized parts includes: forming a bottom metal pattern with a dielectric layer thereon on a substrate, in which the dielectric layer has an opening exposing the bottom metal pattern; forming a semiconductor layer to cover the dielectric layer; forming a first metal layer on the semiconductor layer; forming a second metal layer on the first metal layer; forming a mask layer on the second metal layer to expose a portion of a top surface of the second metal layer; etching the second metal layer through the mask layer until a top surface of the first metal layer is exposed, in which an etch selectivity of the second metal layer and the first metal layer is greater than 2.0; anodizing the first metal layer through the mask layer to form an anodized segment; and removing the mask layer.

An in situ protective coating is deposited on surfaces of chamber components of a reaction chamber at high temperatures. The in situ protective coating may be deposited at a temperature greater than about 200° C. to provide a high quality coating that is resistant to certain types of halogen chemistries, such as fluorine-based species, chlorine-based species, bromine-based species, or iodine-based species. Subsequent coatings or layers may be deposited on the in situ protective coating having different etch selectivities than the underlying in situ protective coating. The in situ protective coating may be deposited throughout the reaction chamber to deposit on surfaces of the chamber components, including on chamber walls.

A trench in a semiconductor substrate is lined with a first insulation layer. A hard mask layer deposited on the first insulation layer is used to control performance of an etch that selectively removes a first portion of the first insulating layer from an upper trench portion while leaving a second portion of first insulating layer in a lower trench portion. After removing the hard mask layer, an upper portion of the trench is lined with a second insulation layer. An opening in the trench that includes a lower open portion delimited by the second portion of first insulating layer in the lower trench portion and an upper open portion delimited by the second insulation layer at the upper trench portion, is then filled by a single deposition of polysilicon material forming a unitary gate / field plate conductor of a field effect rectifier diode.

The present: invention addresses the problem of providing a silicon nitride etching liquid composition which is capable of selectively etching Si3N4 with a practical etching selectivity with respect to SiO2, while suppressing regrowth of SiO2, and which is also capable of suppressing pattern collapse of an SiO2 film in the production of a 3D nonvolatile memory cell. A silicon nitride etching liquid composition for producing a 3D nonvolatile memory cell, which contains phosphoric acid, one or more silane coupling agents and water, but which does not contain ammonium ions.

Apparatuses and methods are provided. Some methods may include providing a substrate to a processing chamber, the substrate having a first material adjacent to and covering a surface of a second material, modifying a layer of the first material by flowing a first process gas onto the substrate and thereby creating a modified layer of the first material, removing the modified layer of the first material by flowing a second process gas onto the substrate, and converting, when the surface of the second material is uncovered via removal of the modified layer, the surface to a converted layer of the second material by flowing a third process gas onto the substrate, in which the first and second process gases are less reactive with the converted layer than with the first material and the second material.

The present invention relates to a processing method for a gradient film layer and a processing method for a gradient-depth micro-nano structure. The processing method for the gradient film layer includes the following steps: fixing a planar film layer on the surface of a substrate; forming a sacrificial film layer with a gradually changing thickness on the surface of the planar film layer through gradient coating and / or exposure and development; based on the etching selectivity ratio, removing the sacrificial film layer and the planar film layer above the gradient surface in sequence through dry etching to obtain a substrate with a gradient film layer; the processing method for the gradient-depth micro-nano structure includes the following steps: forming a photoresist film on the surface of the gradient film layer and patterning the photoresist film in the gradient structure region; through etching and resist removal, removing the photoresist film and the gradient film layer in the gradient structure region in sequence, and after the etching is completed, through post-treatment, a gradient-depth micro-nano structure is obtained. The present invention has the effects of improving the processing flexibility, increasing the thickness control range of the gradient film layer, and obtaining a gradient-depth micro-nano structure with a continuous depth change.

A substrate-treatment method includes (a) providing a substrate at a stage, the substrate including a silicon nitride-containing film, in which a recess defined by a top, a side wall, and a bottom is formed, and a silicon film exposed from the bottom of the recess; (b) forming a silicon oxide film along the recess; (c) exposing the silicon oxide film to a plasma of a process gas containing a hydrogen gas, thereby modifying the silicon oxide film at the top and bottom of the recess selectively relative to the side wall by an anisotropic plasma treatment; and (d) selectively removing the modified silicon oxide film at the top and bottom of the recess through chemical etching without using a plasma, thereby retaining the silicon oxide film at the side wall of the recess.

Provided is an etching solution composition capable of preventing reduction in the etching rate of a silicon nitride film, achieving high etching selectivity with respect to silicon nitride, and suppressing deposition of silica on the surface of silicon oxide.　This etching solution composition is based on an inorganic acid and is for selectively etching silicon nitride from a semiconductor containing the silicon nitride and silicon oxide, and comprises: (a) a fluorine compound that increases the etching rate of silicon nitride; and (b) a volatilization inhibitor that inhibits volatilization of the fluorine compound.

The invention provides a composition, application thereof and a preparation method of a semiconductor device. The composition comprises the following components in percentage by mass: 5-50% of a first aprotic organic solvent; 5%-30% of a second aprotic organic solvent; 0.01%-5% of an acid; 0.15%-5% of a corrosion inhibitor; 10%-85% of water; the corrosion inhibitor comprises amino acid with the molecular weight larger than or equal to 100. The composition provided by the invention can be mixed with an oxidizing agent for use, etching residues on the surface of a patterned substrate can be effectively cleaned after mixing, a part of a hard mask on the patterned substrate can be selectively removed while a metal material in the patterned substrate is effectively protected, and the etching selection ratio of the hard mask to the metal material is improved.

The invention provides a dry etching method for a molybdenum silicide layer, and relates to the field of semiconductor mask plates. The method is used for performing dry etching pattern transfer on the molybdenum silicide phase shift layer in the phase shift mask. The method comprises the following steps of: 1, putting a patterned molybdenum silicide layer into an ICP (Inductively Coupled Plasma) dry etching machine; 2, mixed SF6 gas and Ar gas are introduced into the etching cavity; and 3, the plasma concentration is regulated and controlled by controlling the ICP source, the plasma bombardment kinetic energy is regulated and controlled through the RF source, and etching of the molybdenum silicide layer is completed. According to the dry etching method, SF6 and Ar are adopted as etching gas, a good etching selection ratio and good morphology can be obtained by controlling the gas proportion, the ICP power and the RF power, and the dry etching method has the advantages of being good in safety, low in production cost and the like.

A technique enabling wet etching of a first silicon oxide film with high selectivity with respect to a metal film and a second silicon oxide film is provided. A substrate processing method of wet-etching a substrate having a stacked structure including a metal film, a first silicon oxide film, and a second silicon oxide film having a moisture content lower than that of the first silicon oxide film is provided. The substrate processing method includes performing an etching while increasing etching selectivity of the first silicon oxide film with respect to the second silicon oxide film and the metal film by supplying an etching liquid, which is prepared by diluting sulfuric acid, hydrogen peroxide and hydrofluoric acid in an anhydrous organic solvent, to the substrate such that the metal film, the first silicon oxide film, and the second silicon oxide film are simultaneously exposed to the etching liquid.

A method for forming a semiconductor structure, the method comprising: providing a substrate, the substrate having a stack structure formed thereon, the stack structure comprising one or more channel stacks stacked in sequence from bottom to top, each channel stack comprising a placeholder layer and a channel layer on the placeholder layer, the substrate further having a dummy gate structure formed thereon, the dummy gate structure spanning across the stack structure and covering part of the top and part of the sidewall of the stack structure; forming a recess through the stack structure on both sides of the dummy gate structure; removing a part of the length of the placeholder layer exposed by the sidewall of the recess along the extension direction of the channel layer to form an inner trench; forming an inner spacer material layer on the sidewall of the dummy gate structure and on the sidewall of the recess, the inner spacer material layer also filling in the inner trench; and performing a modification treatment on the inner spacer material layer outside the inner trench for converting the inner spacer material layer into a sacrificial layer, the sacrificial layer having an etching selectivity ratio with the inner spacer material layer and the channel layer. The embodiments of the present application are beneficial to the performance of the semiconductor device.

The invention discloses a monocrystalline silicon wafer alkali polishing additive and a preparation method and application thereof, and the alkali polishing additive comprises the following components by mass content: 0.5-4% of a reaction accelerator, 2-5% of a corrosion and scale inhibitor, 1.5-3% of a chelating agent, 1-3% of a pH regulator, 1-5% of a surfactant, 3-10% of a cosolvent and the balance of water according to the total mass of 100%. The alkali polishing additive is obvious in performance gain, good in etching selectivity and small in silicon wafer weight loss; the back polishing effect can be improved, the reflectivity of the silicon wafer is high, and the photoelectric conversion efficiency of a photovoltaic cell is improved; the anti-crystallization performance is excellent, and the environment is protected.

The invention provides a preparation method of a bump region window, and belongs to the technical field of semiconductors. The method comprises the following steps: preparing a matrix structure, wherein the matrix structure comprises a base layer and at least one bulge structure positioned on the top surface of the base layer; sequentially depositing a dielectric film layer and a protective film layer on the substrate structure; the protective film layer is etched under a first etching condition so that the protective film layer can be thinned to be lower than the top end of the dielectric film layer of the protruding structure, and under the first etching condition, the etching selection ratio of the protective film layer to the dielectric film layer is larger than 1: 1; the dielectric film layer is etched under a second etching condition, so that the distance between the top end of the dielectric film layer and the top end of the protruding structure is a target height difference, and the etching selection ratio of the dielectric film layer to the protective film layer is larger than 5: 1 under the second etching condition; and removing the protective film layer to form a window in the top area of the convex structure. According to the preparation method, the position precision of the window can be ensured.

A substrate processing method according to the present invention incudes: a preparation step of preparing a substrate in which at least a first surface containing silicon oxide and a second surface containing silicon or a silicon compound other than silicon oxide are exposed; a surface modification step of forming an etching selectivity imparting film on at least a part of the first surface and at least a part of the second surface by a silylation treatment of bringing a silylating agent into contact with the first surface and the second surface; and an etching step of selectively carrying out an etching treatment on the second surface with respect to the first surface using an etching agent after the surface modification step.

The invention belongs to the technical field of wet electronic chemicals, and particularly relates to a buffer oxide etching solution (BOE) with high selection ratio of silicon dioxide (SiO2) to silicon oxynitride (SiOxNy) in semiconductor manufacturing, and the etching solution comprises the following components in percentage by mass: 0-20% of HF, 20-40% of NH4F, 0.01-0.05% of an impregnating compound, 0.005-0.01% of an additive and the balance of ultrapure water. The wetting agent is introduced, so that the wettability of the silicon dioxide film layer can be improved, and the etching roughness is improved; meanwhile, after 2-(2-(2-hydroxyethoxy)-ethoxy)-ethyl phosphonic acid is added, a phosphonic acid group can form coordination with a Si-N bond in silicon oxynitride, and the silicon oxynitride film etching selection ratio of silicon dioxide can be remarkably increased under the condition that the silicon dioxide etching rate is not reduced. The etching liquid is stable, the solution is clear and transparent, and the addition of the additive can reduce the surface tension and improve the infiltration and undercutting capabilities of the etching liquid.

There are provided a method of manufacturing a treated substrate that can, in a substrate having on its surface at least two regions of a first region containing silicon and a second region made from a material different from that of the first region, suppress etching of the first region and achieve high etch selectivity between the two regions, and a method of manufacturing a semiconductor comprising the method of manufacturing a treated substrate. The method of manufacturing a treated substrate comprises a step 1 being a chemical solution treatment step, a step 2 being a cleaning step, and a step 3 being an etching step.

One embodiment of the present invention is an input device using upper and lower electrode layers with no etching selectivity and comprising: a mesh-shaped lower electrode layer provided on a base material; an insulating layer provided to cover the lower electrode layer; a mesh-shaped upper electrode layer provided on the insulating layer in a direction intersecting the lower electrode layer; a first lower lead-out wiring layer provided between the base material and the insulating layer and connected at one end thereof to the lower electrode layer; a second lower lead-out wiring layer provided between the base material and the insulating layer and formed at the same tier as, but separately from, the first lower lead-out wiring layer; a first external connection terminal layer connected to the other end of the first lower lead-out wiring layer; and a second external connection terminal layer connected to the other end of the second lower lead-out wiring layer. The upper electrode layer is connected at one end of the second lower lead-out wiring layer so as to cover a first exposed part exposed through a through-hole from the insulating layer, thus making it possible to effectively utilize wiring of a material common to the electrodes.

Provided is a plasma processing method and device capable of controlling the etching mask shape during a single-step process that etches a target material disposed below the etching mask. The plasma processing method includes performing selective deposition on the etching mask in separate phases, which are controlled via a periodic bias voltage signal. By tuning the bias voltage power, duration and timing, the mask height and width can be controlled and stabilized while etching on the substrate proceeds. Thus, the present method provides an etching process that allows fine control of the etching mask shape for small pattern sizes and provides high etching selectivity through deposition.

Embodiments of the present disclosure generally relate to methods for etching a carbon hard mask to have improved etching selectivity and profile control. In some embodiments, a method is provided for processing a carbon hard mask layer, which includes positioning a workpiece within a process area of ​​a processing chamber, wherein the workpiece has a carbon hard mask layer positioned on or throughout the underlying layer, and processing the carbon hard mask layer by exposing the workpiece to a sequential penetration synthesis (SIS) process to produce an alumina-carbon hybrid hard mask denser than the carbon hard mask layer. The SIS process includes exposing the carbon hard mask layer to an aluminum precursor to penetrate the carbon hard mask layer with the aluminum precursor, purging and removing gaseous residues, exposing the carbon hard mask layer to an oxidizing agent to penetrate the carbon hard mask layer with the oxidizing agent to produce an alumina coating positioned on the inner surface of the carbon hard mask layer, and purging the process area to remove gaseous residues.

A method of manufacturing a structure having anodized parts includes: forming a bottom metal layer on a substrate; forming a top metal layer on the bottom metal layer; forming a mask layer on the top metal layer to expose a portion of a top surface of the top metal layer; etching the top metal layer through the mask layer until a top surface of the bottom metal layer is exposed, wherein an etch selectivity of the top metal layer and the bottom metal layer is greater than 2.0; anodizing the bottom metal layer through the mask layer to form an anodized segment; and removing the mask layer after the anodizing.

The present disclosure discloses a semiconductor device, electronic device, and preparation method. Wordline trenches are first formed on a semiconductor substrate, followed by forming a wordline structure in the wordline trenches, and then forming an active area. This allows the wordline trenches to pass through the semiconductor substrate without requiring them to pass through other materials. Because the semiconductor substrate is made of uniform material, etching selectivity issues are eliminated, allowing the bottom surface of the formed wordline trenches to be flat. When forming the wordline structure in the wordline trenches, the wordline structure can be in direct contact with the semiconductor substrate without requiring it to contact other materials. This allows the bottom surface of the wordline structure to be flat, thereby improving the performance and reliability of the semiconductor device.

This application discloses the formation of vias using imprint lithography and the formation of repositioning vias by imprint lithography. A resist layer is formed on top of a dielectric layer. For example, a pattern of via openings is imprinted in the resist layer using nanoimprint lithography. After imprinting, the pattern of via openings imprinted in the resist layer is transferred to the dielectric layer by anisotropic etching to form via openings in the dielectric layer. Anisotropic etching has low etch selectivity between the resist layer and the dielectric layer. The via openings in the dielectric layer are filled with a conductive material to form vias in the dielectric layer. The centerline of at least one repositioning via is not parallel to the centerline of at least one other via.

The invention provides an etching method and etching equipment for a silicon-based nitride thin film layer. The etching method comprises the following steps: providing a substrate with the silicon-based nitride thin film layer on the surface; the silicon-based nitride thin film layer is placed in an etching groove containing phosphoric acid etching liquid to remove the silicon-based nitride thin film layer, and in the etching process, a bubble generating device in the etching groove introduces micro-nano bubbles into the phosphoric acid etching liquid to trigger micro-turbulence to promote etching uniformity; and the micro-nano bubbles crack on the surface of the silicon-based nitride thin film layer to generate local pressure so as to enhance the etching reaction. Based on the synergistic effect of the micro-nano bubbles and the phosphoric acid etching liquid, efficient removal of the silicon-based nitride thin film layer is achieved. Compared with a traditional etching process, the etching rate is improved by more than 30%, the etching uniformity is greatly optimized, and the etching selection ratio of the silicon-based nitride thin film layer and the oxide thin film layer is greatly improved. Meanwhile, the introduction of the micro-nano bubbles significantly reduces the dosage of chemicals, the production cost and the environmental burden.

A pixel according to one embodiment of the present application includes: first and second electrodes spaced apart from each other; a first insulating layer having a first etching selectivity; a first insulating pattern having a second etching selectivity; a light emitting element including first and second ends; a second insulating pattern disposed on one region of the light emitting element to expose the first and second ends of the light emitting element and having the second etching selectivity; and third and fourth electrodes electrically connecting the first and second ends of the light emitting element to the first and second electrodes, respectively.

The invention relates to a display device, an electronic device, and a method of manufacturing the display device. The display device includes: a substrate; a first pixel electrode and a second pixel electrode arranged to be separated from each other over the substrate; a first bank layer disposed on the first pixel electrode and the second pixel electrode and including a 1-1 opening over the first pixel electrode and a 2-1 opening over the second pixel electrode; a second bank layer disposed on the first bank layer and including a 1-2 opening over the first pixel electrode and a 2-2 opening over the second pixel electrode; and a wiring layer disposed on the second bank layer and including a portion disposed between the first pixel electrode and the second pixel electrode, in which the first bank layer includes a first inorganic insulating material, and the second bank layer includes a second inorganic insulating material having a different etching selectivity from the first inorganic insulating material.