923 results about "Etching selectivity" patented technology

High-deposition rate methods for forming transparent ashable hardmasks (AHMs) that have high plasma etch selectivity to underlying layers are provided. The methods involve placing a wafer on a powered electrode such as a powered pedestal for plasma-enhanced deposition. According to various embodiments, the deposition is run at low hydrocarbon precursor partial pressures and/or low process temperatures. Also provided are ceramic wafer pedestals with multiple electrode planes embedded with the pedestal are provided. According to various embodiments, the pedestals have multiple RF mesh electrode planes that are connected together such that all the electrode planes are at the same potential.

Etching of nitride and oxide layers with reactant gases is modulated by etching in different process regimes. High etch selectivity to silicon nitride is achieved in an adsorption regime where the partial pressure of the etchant is lower than its vapor pressure. Low etch selectivity to silicon nitride is achieved in a condensation regime where the partial pressure of the etchant is higher than its vapor pressure. By controlling partial pressure of the etchant, very high etch selectivity to silicon nitride may be achieved.

Methods for etching dielectric layers comprising silicon and nitrogen are provided herein. In some embodiments, such methods may include providing a substrate having a dielectric layer comprising silicon and nitrogen disposed thereon, forming reactive species from a process gas comprising hydrogen (H₂) and nitrogen trifluoride (NF₃) using a remote plasma; and etching the dielectric layer using the reactive species. In some embodiments, an oxide layer is disposed adjacent to the dielectric layer. In some embodiments, the flow rate ratio of the process gas can be adjusted such that an etch selectivity of the dielectric layer to at least one of the oxide layer or the substrate is between about 0.8 to about 4.

The present invention includes a process for selectively etching a low-k dielectric material formed on a substrate using a plasma of a gas mixture in a plasma etch chamber. The gas mixture comprises a fluorine-rich fluorocarbon or hydrofluorocarbon gas, a nitrogen-containing gas, and one or more additive gases, such as a hydrogen-rich hydrofluorocarbon gas, an inert gas and/or a carbon-oxygen gas. The process provides a low-k dielectric to a photoresist mask etching selectivity ratio greater than about 5:1, a low-k dielectric to a barrier/liner layer etching selectivity ratio greater about 10:1, and a low-k dielectric etch rate higher than about 4000 Å/min.

A method and apparatus for selectively etching doped semiconductor oxides faster than undoped oxides. The method comprises applying dissociative energy to a mixture of nitrogen trifluoride and hydrogen gas remotely, flowing the activated gas toward a processing chamber to allow time for charged species to be extinguished, and applying the activated gas to the substrate. Reducing the ratio of hydrogen to nitrogen trifluoride increases etch selectivity. A similar process may be used to smooth surface defects in a silicon surface.

A method of suppressing the etch rate for exposed silicon-and-nitrogen-containing material on patterned heterogeneous structures is described and includes a two stage remote plasma etch. The etch selectivity of silicon relative to silicon nitride and other silicon-and-nitrogen-containing material is increased using the method. The first stage of the remote plasma etch reacts plasma effluents with the patterned heterogeneous structures to form protective solid by-product on the silicon-and-nitrogen-containing material. The plasma effluents of the first stage are formed from a remote plasma of a combination of precursors, including nitrogen trifluoride and hydrogen (H₂). The second stage of the remote plasma etch also reacts plasma effluents with the patterned heterogeneous structures to selectively remove material which lacks the protective solid by-product. The plasma effluents of the second stage are formed from a remote plasma of a fluorine-containing precursor.

There are included steps of forming a silicon nitride layer on a silicon layer or a silicon oxide layer, loading the silicon layer or the silicon oxide layer and the silicon nitride layer in a dry etching atmosphere, and selectively etching the silicon nitride layer with respect to the silicon layer or the silicon oxide layer by flowing a fluorine gas consisting of any one of CH2F2, CH3F, or CHF3 and an inert gas to the dry etching atmosphere. Hence, in the etching process of the silicon nitride layer, the etching selectivity of the silicon nitride layer to Si or SiO2 can be enhanced and also etching anisotropy can be enhanced.

A method of etching exposed patterned heterogeneous structures is described and includes a remote plasma etch formed from a reactive precursor. The plasma power is pulsed rather than left on continuously. Plasma effluents from the remote plasma are flowed into a substrate processing region where the plasma effluents selectively remove one material faster than another. The etch selectivity results from the pulsing of the plasma power to the remote plasma region, which has been found to suppress the number of ionically-charged species that reach the substrate. The etch selectivity may also result from the presence of an ion suppression element positioned between a portion of the remote plasma and the substrate processing region.

The present invention relates to a method of forming an amorphous carbon film and a method of manufacturing a semiconductor device using the method. An amorphous carbon film is formed on a substrate by vaporizing a liquid hydrocarbon compound, which has chain structure and one double bond, and supplying the compound to a chamber, and ionizing the compound. The amorphous carbon film is used as a hard mask film.

It is possible to easily control characteristics of the amorphous carbon film, such as a deposition rate, an etching selectivity, a refractive index (n), a light absorption coefficient (k) and stress, so as to satisfy user's requirements. In particular, it is possible to lower the refractive index (n) and the light absorption coefficient (k). As a result, it is possible to perform a photolithography process without an antireflection film that prevents the diffuse reflection of a lower material layer.

Further, a small amount of reaction by-product is generated during a deposition process, and it is possible to easily remove reaction by-products that are attached on the inner wall of a chamber. For this reason, it is possible to increase a cycle of a process for cleaning a chamber, and to increase parts changing cycles of a chamber. As a result, it is possible to save time and cost.

Self-aligned contacts in integrated circuits can be formed on an integrated circuit substrate having an active region. A groove can be formed in the insulating layer and a conductive material can be formed in the groove to a level that is recessed in the groove. An insulating material can be formed in the groove on the conductive material that has an etch selectivity with respect to the insulating layer. A contact that is self-aligned to the active region can be then be formed.

An apparatus and a method for etching high dielectric constant (high-κ) materials using halogen containing gas and reducing gas chemistries are provided. One embodiment of the method is accomplished by etching a layer using two etch gas chemistries in separate steps. The first etch gas chemistry contain no oxygen containing gas in order to break through etching of the high dielectric constant materials, to dean any residues left from previous polysilicon etch process resulting in less high-κ foot, and also to control silicon recess problem associated with an underlying silicon oxide layer. The second over-etch gas chemistry provides a high etch selectivity for high dielectric constant materials over silicon oxide materials to be combined with low source power to further reduce silicon substrate oxidation problem.

A method of fabricating a semiconductor device includes forming a first film on a processed film, patterning the first film into a pattern with smaller width and a space with larger width, forming a second film along upper and side surfaces of first film and an upper surface of second film, etching the second film thereby to expose upper surfaces of first film and processed film while part of second film remains along the side surface of first film, etching the first film under the condition that the first film has higher etch selectivity than the second film, etching an upper part of second film under the condition that the second film has a higher etch selectivity than the processed film, after the first film has been etched, and etching the processed film with the second film serving as mask after the upper part of second film has been etched.

A method of fabricating a magnetic tunnel junction (MTJ) device is provided. A patterned hard mask is oxidized to form a surface oxide thereon. An MTJ stack is etched in alignment with the patterned hard mask after the oxidizing of the patterned hard mask. Preferably, the MTJ stack etch recipe includes chlorine and oxygen. Etch selectivity between the hard mask and the MTJ stack is improved.

Implementations described herein generally relate to the fabrication of integrated circuits. More particularly, the implementations described herein provide techniques for deposition of amorphous carbon films on a substrate. In one implementation, a method of forming an amorphous carbon film is provided. The method comprises depositing an amorphous carbon film on an underlayer positioned on a susceptor in a first processing region. The method further comprises implanting a dopant or inert species into the amorphous carbon film in a second processing region. The dopant or inert species is selected from carbon, boron, nitrogen, silicon, phosphorous, argon, helium, neon, krypton, xenon or combinations thereof. The method further comprises patterning the doped amorphous carbon film. The method further comprises etching the underlayer.

Methods and structures are disclosed for advanced interconnects in sub-micron and sub-half-micron integrated circuit devices fabricated using a single damascene process. a dielectric etch-stop layer (e.g., silicon nitride) is deposited subsequent to rather than prior to CMP processing of the previous metallization layer (e.g., the conductive plug). This scheme effectively eliminates the effect of CMP-induced erosion on the etch-stop layer and therefore allows an extremely thin etch stop to be used. Moreover, a high etch-selectivity can be obtained for the trench etch, and all etch-stop material is removed from beneath the interconnect metal, thereby reducing parasitic effects. A patterned dielectric layer is used as a metal cap in place of the standard blanket silicon nitride layer, thus preventing the formation of blisters and bubbles associated with trapped moisture and gasses, and reducing interconnect capacitance.

The present disclosure provides a method of fabricating a semiconductor device that includes forming first and second gate structures over first and second regions of a substrate, respectively, forming spacers on sidewalls of the first and second gate structures, the spacers being formed of a first material, forming a capping layer over the first and second gate structures, the capping layer being formed of a second material different from the first material, forming a protection layer over the second region to protect the second gate structure, removing the capping layer over the first gate structure; removing the protection layer over the second region, epitaxially (epi) growing a semiconductor material on exposed portions of the substrate in the first region, and removing the capping layer over the second gate structure by an etching process that exhibits an etching selectivity of the second material to the first material.

The present invention provides a material for an antireflective film characterized by high etching selectivity with respect to a resist, that is, which has a fast etching speed when compared to the resist, and in addition, can be removed without damage to a film which is to be processed. The present invention also provides a pattern formation method for forming an antireflective film layer on a substrate using this antireflective film-forming composition, and a pattern formation method that uses this antireflective film as a hard mask, and a pattern formation method that uses this antireflective film as a hard mask for processing the substrate. The present invention provides an antireflective film-forming composition comprising an organic solvent, a cross linking agent, and a polymer comprising a light absorbing group obtained by hydrolyzing and condensing more than one type of silicon compound, a crosslinking group and a non-crosslinking group.

A method of patterning a crystalline film. A crystalline film having a degenerate lattice comprising first atoms in a first region and a second region is provided. Dopants are substituted for said first atoms in said first region to form a non-degenerate crystalline film in said first region. The first region and the second region are exposed to a wet etchant wherein the wet etchant etches the degenerate lattice in said second region without etching the non-degenerate lattice in the first region.

A method and apparatus are described for fabricating a low-pin-count chip package (701) including a die pad (706) for receiving an integrated circuit device and a plurality of connection leads (702) having recessed lead ends (704) at the outer peripheral region of each contact lead. After forming the package body (202) over the integrated circuit device, unplated portions (104) of the exposed bottom surface of the selectively plated lead frame are partially etched to form recessed lead ends (302) at the outer peripheral region of each contact lead, and the recessed lead ends are subsequently re-plated (402) to provide wettable recessed lead ends at the outer peripheral region of each contact lead.