148 results about "Etching selectivity" patented technology

The invention discloses an integrated circuit equipment data optimization monitoring system and method based on big data, and relates to the technical field of integrated circuit manufacturing. The method is used for solving the problems of insufficient multi-physical field monitoring, difficulty in abnormal traceability and lack of closed-loop control in plasma etching. A plasma sheath thickness inversion model and an etching selection ratio model are constructed by collecting radio frequency reflection phase, mass spectrum ion strength and wafer temperature data, and process parameter-plasma state dynamic coupling is established. Interference image distortion features and electron microscope size data are fused, micro-groove geometric parameters are analyzed, morphology instability risk indexes are generated, and nanoscale early warning is achieved. And designing a dual-channel fusion network, embedding a physical constraint attention mechanism, and generating an etching rate optimization instruction. On the basis of incremental learning, model parameters are updated online, a'monitoring-decision-feedback 'closed-loop system is formed, anomaly detection sensitivity and decision reliability are improved, and technical support is provided for intelligence of integrated circuit equipment.

A bottom electrode is deposited on a substrate. A dielectric layer is deposited on the bottom electrode. One or more structures are patterned within the dielectric layer. A liner layer is deposited on top of the dielectric layer and the bottom electrode. A selectivity promotion layer is deposited on top of the liner layer. The selectivity promotion layer is etched to expose a top surface of the dielectric layer and a portion of the bottom electrode. A phase change memory material layer is deposited within a void of the one or more structures between the selectivity promotion layer.

The present: invention addresses the problem of providing a silicon nitride etching liquid composition which is capable of selectively etching Si3N4 with a practical etching selectivity with respect to SiO2, while suppressing regrowth of SiO2, and which is also capable of suppressing pattern collapse of an SiO2 film in the production of a 3D nonvolatile memory cell. A silicon nitride etching liquid composition for producing a 3D nonvolatile memory cell, which contains phosphoric acid, one or more silane coupling agents and water, but which does not contain ammonium ions.

Provided is an etching solution composition capable of preventing reduction in the etching rate of a silicon nitride film, achieving high etching selectivity with respect to silicon nitride, and suppressing deposition of silica on the surface of silicon oxide.　This etching solution composition is based on an inorganic acid and is for selectively etching silicon nitride from a semiconductor containing the silicon nitride and silicon oxide, and comprises: (a) a fluorine compound that increases the etching rate of silicon nitride; and (b) a volatilization inhibitor that inhibits volatilization of the fluorine compound.

A technique enabling wet etching of a first silicon oxide film with high selectivity with respect to a metal film and a second silicon oxide film is provided. A substrate processing method of wet-etching a substrate having a stacked structure including a metal film, a first silicon oxide film, and a second silicon oxide film having a moisture content lower than that of the first silicon oxide film is provided. The substrate processing method includes performing an etching while increasing etching selectivity of the first silicon oxide film with respect to the second silicon oxide film and the metal film by supplying an etching liquid, which is prepared by diluting sulfuric acid, hydrogen peroxide and hydrofluoric acid in an anhydrous organic solvent, to the substrate such that the metal film, the first silicon oxide film, and the second silicon oxide film are simultaneously exposed to the etching liquid.

A method for forming a semiconductor structure, the method comprising: providing a substrate, the substrate having a stack structure formed thereon, the stack structure comprising one or more channel stacks stacked in sequence from bottom to top, each channel stack comprising a placeholder layer and a channel layer on the placeholder layer, the substrate further having a dummy gate structure formed thereon, the dummy gate structure spanning across the stack structure and covering part of the top and part of the sidewall of the stack structure; forming a recess through the stack structure on both sides of the dummy gate structure; removing a part of the length of the placeholder layer exposed by the sidewall of the recess along the extension direction of the channel layer to form an inner trench; forming an inner spacer material layer on the sidewall of the dummy gate structure and on the sidewall of the recess, the inner spacer material layer also filling in the inner trench; and performing a modification treatment on the inner spacer material layer outside the inner trench for converting the inner spacer material layer into a sacrificial layer, the sacrificial layer having an etching selectivity ratio with the inner spacer material layer and the channel layer. The embodiments of the present application are beneficial to the performance of the semiconductor device.

The invention discloses a monocrystalline silicon wafer alkali polishing additive and a preparation method and application thereof, and the alkali polishing additive comprises the following components by mass content: 0.5-4% of a reaction accelerator, 2-5% of a corrosion and scale inhibitor, 1.5-3% of a chelating agent, 1-3% of a pH regulator, 1-5% of a surfactant, 3-10% of a cosolvent and the balance of water according to the total mass of 100%. The alkali polishing additive is obvious in performance gain, good in etching selectivity and small in silicon wafer weight loss; the back polishing effect can be improved, the reflectivity of the silicon wafer is high, and the photoelectric conversion efficiency of a photovoltaic cell is improved; the anti-crystallization performance is excellent, and the environment is protected.

A substrate processing method according to the present invention incudes: a preparation step of preparing a substrate in which at least a first surface containing silicon oxide and a second surface containing silicon or a silicon compound other than silicon oxide are exposed; a surface modification step of forming an etching selectivity imparting film on at least a part of the first surface and at least a part of the second surface by a silylation treatment of bringing a silylating agent into contact with the first surface and the second surface; and an etching step of selectively carrying out an etching treatment on the second surface with respect to the first surface using an etching agent after the surface modification step.

Provided is a plasma processing method and device capable of controlling the etching mask shape during a single-step process that etches a target material disposed below the etching mask. The plasma processing method includes performing selective deposition on the etching mask in separate phases, which are controlled via a periodic bias voltage signal. By tuning the bias voltage power, duration and timing, the mask height and width can be controlled and stabilized while etching on the substrate proceeds. Thus, the present method provides an etching process that allows fine control of the etching mask shape for small pattern sizes and provides high etching selectivity through deposition.

Embodiments of the present disclosure generally relate to methods for etching a carbon hard mask to have improved etching selectivity and profile control. In some embodiments, a method is provided for processing a carbon hard mask layer, which includes positioning a workpiece within a process area of ​​a processing chamber, wherein the workpiece has a carbon hard mask layer positioned on or throughout the underlying layer, and processing the carbon hard mask layer by exposing the workpiece to a sequential penetration synthesis (SIS) process to produce an alumina-carbon hybrid hard mask denser than the carbon hard mask layer. The SIS process includes exposing the carbon hard mask layer to an aluminum precursor to penetrate the carbon hard mask layer with the aluminum precursor, purging and removing gaseous residues, exposing the carbon hard mask layer to an oxidizing agent to penetrate the carbon hard mask layer with the oxidizing agent to produce an alumina coating positioned on the inner surface of the carbon hard mask layer, and purging the process area to remove gaseous residues.

This application discloses the formation of vias using imprint lithography and the formation of repositioning vias by imprint lithography. A resist layer is formed on top of a dielectric layer. For example, a pattern of via openings is imprinted in the resist layer using nanoimprint lithography. After imprinting, the pattern of via openings imprinted in the resist layer is transferred to the dielectric layer by anisotropic etching to form via openings in the dielectric layer. Anisotropic etching has low etch selectivity between the resist layer and the dielectric layer. The via openings in the dielectric layer are filled with a conductive material to form vias in the dielectric layer. The centerline of at least one repositioning via is not parallel to the centerline of at least one other via.

A pixel according to one embodiment of the present application includes: first and second electrodes spaced apart from each other; a first insulating layer having a first etching selectivity; a first insulating pattern having a second etching selectivity; a light emitting element including first and second ends; a second insulating pattern disposed on one region of the light emitting element to expose the first and second ends of the light emitting element and having the second etching selectivity; and third and fourth electrodes electrically connecting the first and second ends of the light emitting element to the first and second electrodes, respectively.

The invention relates to a display device, an electronic device, and a method of manufacturing the display device. The display device includes: a substrate; a first pixel electrode and a second pixel electrode arranged to be separated from each other over the substrate; a first bank layer disposed on the first pixel electrode and the second pixel electrode and including a 1-1 opening over the first pixel electrode and a 2-1 opening over the second pixel electrode; a second bank layer disposed on the first bank layer and including a 1-2 opening over the first pixel electrode and a 2-2 opening over the second pixel electrode; and a wiring layer disposed on the second bank layer and including a portion disposed between the first pixel electrode and the second pixel electrode, in which the first bank layer includes a first inorganic insulating material, and the second bank layer includes a second inorganic insulating material having a different etching selectivity from the first inorganic insulating material.

The present application provides an organic compound, a photoresist containing the same and applications thereof, the organic compound has a structure as shown in formula I, through the design of molecular structure, it has the function of antioxidant, can effectively improve the etching performance of photoresist in dry etching as a photoetching aid. The photoresist containing the same has excellent etching performance and developing property, especially has excellent etching selectivity, can prevent the appearance of photoresist edge line from excessive etching, the slope is large, the line width is small and other abnormal morphology, can effectively reduce and avoid the problem of etching residue and subsequent stripping difficulty, significantly optimizes the etching morphology, can fully meet the processing demand of high precision, fine pattern / line.

The application provides a preparation method of a semiconductor device, and belongs to the technical field of semiconductors. The preparation method comprises the following steps: taking a third mask layer as a mask, etching a first dielectric layer by using a first etching process and stopping on a first mask layer and a second mask layer, etching the first mask layer and the second mask layer by using a second etching process with high selectivity and stopping on an anti-reflection dielectric layer, and etching the anti-reflection dielectric layer by using a third etching process with high selectivity and stopping on a second metal layer. Through step-by-step etching and etching selectivity control, a through hole is formed on metal layers with different heights at the same time, the etching amount on the first metal layer is sufficient, the second metal layer cannot be etched through, process damage is reduced, and process precision and yield are improved.

An electromechanical systems structure including: providing a stack, including a structural layer extending in a plane, a sidewall layer including a first portion lying in a plane parallel to the structural layer plane and a second portion lying in a plane transverse to the structural layer plane, an etch-stop layer, positioned between the sidewall layer and the structural layer, including an etch-selectivity different from an etch-selectivity of the structural layer and an etch-selectivity of the sidewall layer, and a mold comprising a wall parallel to the sidewall layer's second portion; etching the sidewall layer's first portion to expose the etch-stop layer; removing the mold; etching the etch-stop layer such that the sidewall layer's second portion masks a portion of the etch-stop layer; removing the sidewall layer's second portion; and etching the structural layer such that the portion of the etch-stop layer masks a portion of the structural layer.

The invention relates to a silicon-containing resist film forming composition and a pattern forming method. The present invention is a silicon-containing composition for forming a resist film, which forms an ultra-fine resist pattern having excellent LWR and CDU, which forms a resist film having high etching selectivity with an organic material, and which does not cause defects due to residues remaining after the completion of patterning, and a pattern forming method. A silicon-containing composition for forming a resist film, which contains a polysiloxane that contains at least one of a repeating unit represented by formula (A-1), a repeating unit represented by formula (A-2), and a partial structure represented by formula (A-3). (In the formula, R1 is a C1-30 monovalent organic group which may have a substituent and acts as a leaving group by heat, an acid or a base, a halogen atom, a hydroxyl group, a sulfo group, a nitro group or a carboxyl group, and R2 and R3 each independently represent a C1-30 monovalent organic group which may have a substituent.

An embodiment of the present invention increases the etching resistance of a photoresist in an EUV PR / SiON pattern using an ion beam etching apparatus to which grid pulsing is applied, so that the photoresist is etched less and SiON is etched more, thereby improving the etching selectivity. According to an embodiment of the present invention, it is possible to improve the LER through repetition of constant etching and deposition, thereby reducing process defects and enabling damage control.

To provide an ashable carbon hard mask (AHM) having high etching selectivity and low stress, in order to enable high aspect ratio (HAR) etching.SOLUTION: A method for accumulating a carbon ashable hard mask layer on a substrate includes: a step 610 of arranging a substrate in a treatment chamber; a step 614 of setting a chamber pressure to be within a predetermined pressure range, and setting a substrate temperature to be within a predetermined temperature range between -20°C and 200°C; a step 618 of supplying a gas mixture containing a hydrocarbon precursor and one or more other gases; and steps 622 to 632 of generating plasma by supplying RF plasma power in a first predetermined period, and accumulating a carbon ashable hard mask layer on a substrate.SELECTED DRAWING: Figure 6

The invention relates to the technical field of semiconductor manufacturing, and discloses a titanium etching solution preparation process based on a hydrogen peroxide-monoethanolamine system.The titanium etching solution comprises, by mass, 5%-15% of hydrogen peroxide, 5%-15% of monoethanolamine, 5%-15% of sodium hydroxide and the balance water. 5%-10% of monoethanolamine; 2%-5% of tris (hydroxymethyl) aminomethane; 0.5% to 1.5% of 2, 2 '-dipyridyl; and 0.1%-0.5% of a double-effect stabilizing and indicating agent. Trihydroxymethyl aminomethane and 2, 2 '-dipyridyl cooperate to stabilize hydrogen peroxide, and a stable pH buffer system is constructed. The key double-effect stabilizing agent and the indicator (such as salicylic acid) can be subjected to complexing chromogenic reaction when the etching product titanium ions are accumulated to reach a threshold value, so that the self-indication function of solution failure is realized. The invention discloses a preparation process for dropwise adding hydrogen peroxide under cooling and temperature control conditions. The titanium etching solution disclosed by the invention has the beneficial effects of high chemical stability, good Ti / Cu etching selectivity and in-situ failure early warning function.

The invention discloses a semiconductor device, a trench structure manufacturing method thereof, a power module and a vehicle. The manufacturing method comprises the following steps: providing a semiconductor body; forming a first film layer, a second film layer and a third film layer on the first surface; forming a first etching window on the third film layer; forming a second etching window on the second film layer by taking the third film layer as a mask; a first etching selection ratio exists between the third film layer and the second film layer; forming a third etching window on the first film layer by taking the second film layer as a mask; a second etching selection ratio exists between the second film layer and the first film layer; forming a groove in the semiconductor body by taking the first film layer as a mask; the groove extends into the semiconductor body along the direction from the first surface to the second surface; the first etching selection ratio is larger than a preset etching selection ratio threshold value, and the second etching selection ratio is smaller than the preset etching selection ratio threshold value. The electrical performance and the reliability of the semiconductor device can be improved.

The application discloses a buffer oxidation etching liquid for improving the etching selectivity of THOX oxide film and TEOS oxide film, and the main components are hydrofluoric acid, ammonium fluoride, additive one, additive two and ultrapure water. The etching liquid is used for etching THOX oxide film and TEOS oxide film simultaneously, and can inhibit the etching of the TEOS oxide film. The additive one is adsorbed by reacting with a large number of Si-OH functional groups on the TEOS oxide film, and a protective film hindering the etching of hydrofluoric acid is formed, so that the corrosion of the TEOS oxide film can be effectively inhibited. The additive two can reduce the surface tension of the etching liquid, so that the etching liquid has higher wettability, and the etching uniformity of the etching liquid is increased. The etching liquid has higher selectivity for the THOX oxide film and the TEOS oxide film, and the selectivity of the two can reach 8.32.

The present invention is applicable to the technical field of semiconductor processes, and particularly relates to a manufacturing method for a laterally excited bulk acoustic wave filter, and a radio-frequency module. The manufacturing method uses the respective excellent characteristics of silicon-based glass and photosensitive glass so as to obtain crystallized glass as a sacrificial layer by means of exposing and annealing the photosensitive glass during manufacturing, thereby implementing pattern transfer. This process does not involve cavity lithography, etching or coating, thus reduces process steps, thereby reducing difficulty and costs, and improving the yield and structural stability of a filter; in addition, crystallized glass and uncrystallized photosensitive glass have high etching selectivity and extremely low parasitic resistance and capacitance, so that cavity etching can be simply and accurately controlled so as to obtain an ideal cavity structure, and device insertion loss can be reduced to improve the overall performance of the filter.

The application discloses a kind of buffer oxide etching solution with high etching uniformity.The main components of the etching solution are hydrofluoric acid, ammonium fluoride, corrosion inhibitor and ultrapure water.The etching solution of the application is used for etching of silicon oxide film, and has little corrosion effect on tungsten nitride layer, and the surface uniformity of tungsten nitride layer is good after etching.The corrosion inhibitor has strong coordination ability and adsorption performance, and the corrosion inhibitor and tungsten nitride surface occur chemical adsorption, forming a protective film, which can prevent the further reaction of etching solution and tungsten nitride.The etching solution of the application has high selectivity to silicon oxide layer and tungsten nitride, and the etching selectivity ratio can be >4000.The etching solution of the application can effectively inhibit the corrosion of tungsten nitride, while ensuring the surface uniformity of tungsten nitride after etching of silicon oxide.

The invention belongs to the technical field of micro electro mechanical systems and ultrasonic sensing, and discloses a CMUT preparation method and a CMUT. According to the method, a double-self-stop high-precision control system is established, the depth of the cavity is defined by using the thickness of the first silicon oxide layer, the doping layer is used as a stop surface during etching, and the problem of uneven etching depth is eliminated; and the atomic-scale uniformity of the thickness of the vibrating diaphragm is ensured by matching the doping layer with the wet etching selectivity. Besides, according to the method, through combination of a doping self-stop technology and a dual-common monocrystalline silicon wafer bonding technology, a high-performance CMUT with thickness uniformity and depth consistency is manufactured, and the preparation cost is remarkably reduced. Besides, the method structurally solves the problem of insulation failure, the thought that the structure and the function are defined through double wafers is adopted, the second silicon dioxide layer forming the insulation layer is arranged on the flat second wafer, and the risk that the insulation layer at the corner of the cavity is broken down due to insufficient step covering capacity in the traditional process is thoroughly eliminated.

Various embodiments of stacked structures, process steps and methods are provided herein for etching high aspect ratio features (e.g., features having an aspect ratio ≥30:1) within stacked structures to reduce or eliminate problems that occur during conventional HAR etch processes. More specifically, novel hard mask layers and methods are provided to improve the etch profile, post-etch surface roughness and CD uniformity of high aspect ratio features etched within hard mask layers, as well as the etch selectivity to layer(s) underlying the hard mask layers or other semiconductor materials exposed on the substrate surface.

The invention discloses a semiconductor device forming method and a semiconductor device, a first conductive layer is formed on a substrate, then a mask layer is formed on the first conductive layer, the material of the mask layer comprises carbon, the mask layer is used as a mask, and the first conductive layer is etched to form a plurality of first conductive wires. In the process of etching the first conductive layer, the etching selection ratio of the first conductive layer relative to the mask layer is greater than the etching selection ratio of the first conductive layer relative to the silicon nitride. The mask layer comprising the carbon material is used as the mask to etch the first conductive layer, and compared with the etching of the first conductive layer by using silicon nitride as the mask, the etching selection ratio of the first conductive layer relative to the mask layer is increased, so that the consumption of the mask layer in the etching process of the first conductive layer can be reduced, and the morphology of the first conductive wire is improved. The etching selection ratio of the first conductive layer relative to the mask layer is improved, so that the thickness of the mask layer can be effectively reduced, the etching depth-to-width ratio is reduced, and a process window is increased.

A dielectric layer of a semiconductor device may be treated using an oxidation treatment process to tune the dielectric constant of the dielectric layer. For example, an etch stop layer (ESL) in an interconnect layer of the semiconductor device may be formed of a high dielectric constant (high-k) dielectric material, which provides etch selectivity for the ESL relative to other dielectric layers in the interconnect layer. A recess may be formed through the ESL and through the dielectric layers, and a conductive structure may be formed in the recess. Prior to formation of the conductive structure, an oxidation treatment operation may be performed to oxidize the exposed ends of the ESL in the recess. The oxidation treatment may lower the dielectric constant of the ends of the ESL, which may result in the ends of the ESL being less susceptible to current leakage through tunneling, hot-carrier injection, and / or thermionic emission.

The application provides a deep silicon etching structure and a preparation method thereof. By introducing a sacrifice passivation layer into a first groove on the surface of a structure to be etched, a firm physical barrier is constructed by using the high etching selectivity of the sacrifice passivation layer relative to a deep silicon etching gas and the excellent etching resistance of the sacrifice passivation layer. When a deep silicon etching process is performed on an SOI substrate, the sacrifice passivation layer can effectively block the bombardment of high-energy plasma, greatly reducing the risk of damage to the metal layer, so as to ensure that the device will not fail due to the thinning, open circuit or short circuit of the metal layer, guaranteeing the electrical integrity of the device. Furthermore, compared with the traditional process, the application only needs to add one step of depositing the sacrifice passivation layer and one step of etching to open the window area of the deep silicon etching, so that the preparation process is simple and the production cost is significantly reduced.

Provided is a method for manufacturing a semiconductor device, in which a mask layer, a buffer layer, and a first mandrel layer are sequentially stacked on a substrate including a first region and a second region. First mandrel patterns are formed on the buffer layer in the first region, and a second mandrel pattern covering the buffer layer in the second region is formed. A first spacer contacting side walls of the first mandrel pattern and the second mandrel pattern is formed on the buffer layer. The first mandrel patterns are removed. A buffer layer pattern and a preliminary mask pattern are formed on the substrate. The second mandrel pattern is removed. In addition, a mask pattern is formed. The buffer layer includes a material having lower electrical conductivity than the mask layer and having etching selectivity with respect to the mask layer.