238 results about "Etching selectivity" patented technology

The invention discloses an integrated circuit equipment data optimization monitoring system and method based on big data, and relates to the technical field of integrated circuit manufacturing. The method is used for solving the problems of insufficient multi-physical field monitoring, difficulty in abnormal traceability and lack of closed-loop control in plasma etching. A plasma sheath thickness inversion model and an etching selection ratio model are constructed by collecting radio frequency reflection phase, mass spectrum ion strength and wafer temperature data, and process parameter-plasma state dynamic coupling is established. Interference image distortion features and electron microscope size data are fused, micro-groove geometric parameters are analyzed, morphology instability risk indexes are generated, and nanoscale early warning is achieved. And designing a dual-channel fusion network, embedding a physical constraint attention mechanism, and generating an etching rate optimization instruction. On the basis of incremental learning, model parameters are updated online, a'monitoring-decision-feedback 'closed-loop system is formed, anomaly detection sensitivity and decision reliability are improved, and technical support is provided for intelligence of integrated circuit equipment.

A bottom electrode is deposited on a substrate. A dielectric layer is deposited on the bottom electrode. One or more structures are patterned within the dielectric layer. A liner layer is deposited on top of the dielectric layer and the bottom electrode. A selectivity promotion layer is deposited on top of the liner layer. The selectivity promotion layer is etched to expose a top surface of the dielectric layer and a portion of the bottom electrode. A phase change memory material layer is deposited within a void of the one or more structures between the selectivity promotion layer.

A trench in a semiconductor substrate is lined with a first insulation layer. A hard mask layer deposited on the first insulation layer is used to control performance of an etch that selectively removes a first portion of the first insulating layer from an upper trench portion while leaving a second portion of first insulating layer in a lower trench portion. After removing the hard mask layer, an upper portion of the trench is lined with a second insulation layer. An opening in the trench that includes a lower open portion delimited by the second portion of first insulating layer in the lower trench portion and an upper open portion delimited by the second insulation layer at the upper trench portion, is then filled by a single deposition of polysilicon material forming a unitary gate / field plate conductor of a field effect rectifier diode.

The present: invention addresses the problem of providing a silicon nitride etching liquid composition which is capable of selectively etching Si3N4 with a practical etching selectivity with respect to SiO2, while suppressing regrowth of SiO2, and which is also capable of suppressing pattern collapse of an SiO2 film in the production of a 3D nonvolatile memory cell. A silicon nitride etching liquid composition for producing a 3D nonvolatile memory cell, which contains phosphoric acid, one or more silane coupling agents and water, but which does not contain ammonium ions.

Provided is an etching solution composition capable of preventing reduction in the etching rate of a silicon nitride film, achieving high etching selectivity with respect to silicon nitride, and suppressing deposition of silica on the surface of silicon oxide.　This etching solution composition is based on an inorganic acid and is for selectively etching silicon nitride from a semiconductor containing the silicon nitride and silicon oxide, and comprises: (a) a fluorine compound that increases the etching rate of silicon nitride; and (b) a volatilization inhibitor that inhibits volatilization of the fluorine compound.

The invention provides a composition, application thereof and a preparation method of a semiconductor device. The composition comprises the following components in percentage by mass: 5-50% of a first aprotic organic solvent; 5%-30% of a second aprotic organic solvent; 0.01%-5% of an acid; 0.15%-5% of a corrosion inhibitor; 10%-85% of water; the corrosion inhibitor comprises amino acid with the molecular weight larger than or equal to 100. The composition provided by the invention can be mixed with an oxidizing agent for use, etching residues on the surface of a patterned substrate can be effectively cleaned after mixing, a part of a hard mask on the patterned substrate can be selectively removed while a metal material in the patterned substrate is effectively protected, and the etching selection ratio of the hard mask to the metal material is improved.

The invention provides a dry etching method for a molybdenum silicide layer, and relates to the field of semiconductor mask plates. The method is used for performing dry etching pattern transfer on the molybdenum silicide phase shift layer in the phase shift mask. The method comprises the following steps of: 1, putting a patterned molybdenum silicide layer into an ICP (Inductively Coupled Plasma) dry etching machine; 2, mixed SF6 gas and Ar gas are introduced into the etching cavity; and 3, the plasma concentration is regulated and controlled by controlling the ICP source, the plasma bombardment kinetic energy is regulated and controlled through the RF source, and etching of the molybdenum silicide layer is completed. According to the dry etching method, SF6 and Ar are adopted as etching gas, a good etching selection ratio and good morphology can be obtained by controlling the gas proportion, the ICP power and the RF power, and the dry etching method has the advantages of being good in safety, low in production cost and the like.

A technique enabling wet etching of a first silicon oxide film with high selectivity with respect to a metal film and a second silicon oxide film is provided. A substrate processing method of wet-etching a substrate having a stacked structure including a metal film, a first silicon oxide film, and a second silicon oxide film having a moisture content lower than that of the first silicon oxide film is provided. The substrate processing method includes performing an etching while increasing etching selectivity of the first silicon oxide film with respect to the second silicon oxide film and the metal film by supplying an etching liquid, which is prepared by diluting sulfuric acid, hydrogen peroxide and hydrofluoric acid in an anhydrous organic solvent, to the substrate such that the metal film, the first silicon oxide film, and the second silicon oxide film are simultaneously exposed to the etching liquid.

A method for forming a semiconductor structure, the method comprising: providing a substrate, the substrate having a stack structure formed thereon, the stack structure comprising one or more channel stacks stacked in sequence from bottom to top, each channel stack comprising a placeholder layer and a channel layer on the placeholder layer, the substrate further having a dummy gate structure formed thereon, the dummy gate structure spanning across the stack structure and covering part of the top and part of the sidewall of the stack structure; forming a recess through the stack structure on both sides of the dummy gate structure; removing a part of the length of the placeholder layer exposed by the sidewall of the recess along the extension direction of the channel layer to form an inner trench; forming an inner spacer material layer on the sidewall of the dummy gate structure and on the sidewall of the recess, the inner spacer material layer also filling in the inner trench; and performing a modification treatment on the inner spacer material layer outside the inner trench for converting the inner spacer material layer into a sacrificial layer, the sacrificial layer having an etching selectivity ratio with the inner spacer material layer and the channel layer. The embodiments of the present application are beneficial to the performance of the semiconductor device.

The invention discloses a monocrystalline silicon wafer alkali polishing additive and a preparation method and application thereof, and the alkali polishing additive comprises the following components by mass content: 0.5-4% of a reaction accelerator, 2-5% of a corrosion and scale inhibitor, 1.5-3% of a chelating agent, 1-3% of a pH regulator, 1-5% of a surfactant, 3-10% of a cosolvent and the balance of water according to the total mass of 100%. The alkali polishing additive is obvious in performance gain, good in etching selectivity and small in silicon wafer weight loss; the back polishing effect can be improved, the reflectivity of the silicon wafer is high, and the photoelectric conversion efficiency of a photovoltaic cell is improved; the anti-crystallization performance is excellent, and the environment is protected.

The invention provides a preparation method of a bump region window, and belongs to the technical field of semiconductors. The method comprises the following steps: preparing a matrix structure, wherein the matrix structure comprises a base layer and at least one bulge structure positioned on the top surface of the base layer; sequentially depositing a dielectric film layer and a protective film layer on the substrate structure; the protective film layer is etched under a first etching condition so that the protective film layer can be thinned to be lower than the top end of the dielectric film layer of the protruding structure, and under the first etching condition, the etching selection ratio of the protective film layer to the dielectric film layer is larger than 1: 1; the dielectric film layer is etched under a second etching condition, so that the distance between the top end of the dielectric film layer and the top end of the protruding structure is a target height difference, and the etching selection ratio of the dielectric film layer to the protective film layer is larger than 5: 1 under the second etching condition; and removing the protective film layer to form a window in the top area of the convex structure. According to the preparation method, the position precision of the window can be ensured.

A substrate processing method according to the present invention incudes: a preparation step of preparing a substrate in which at least a first surface containing silicon oxide and a second surface containing silicon or a silicon compound other than silicon oxide are exposed; a surface modification step of forming an etching selectivity imparting film on at least a part of the first surface and at least a part of the second surface by a silylation treatment of bringing a silylating agent into contact with the first surface and the second surface; and an etching step of selectively carrying out an etching treatment on the second surface with respect to the first surface using an etching agent after the surface modification step.

The invention belongs to the technical field of wet electronic chemicals, and particularly relates to a buffer oxide etching solution (BOE) with high selection ratio of silicon dioxide (SiO2) to silicon oxynitride (SiOxNy) in semiconductor manufacturing, and the etching solution comprises the following components in percentage by mass: 0-20% of HF, 20-40% of NH4F, 0.01-0.05% of an impregnating compound, 0.005-0.01% of an additive and the balance of ultrapure water. The wetting agent is introduced, so that the wettability of the silicon dioxide film layer can be improved, and the etching roughness is improved; meanwhile, after 2-(2-(2-hydroxyethoxy)-ethoxy)-ethyl phosphonic acid is added, a phosphonic acid group can form coordination with a Si-N bond in silicon oxynitride, and the silicon oxynitride film etching selection ratio of silicon dioxide can be remarkably increased under the condition that the silicon dioxide etching rate is not reduced. The etching liquid is stable, the solution is clear and transparent, and the addition of the additive can reduce the surface tension and improve the infiltration and undercutting capabilities of the etching liquid.

Provided is a plasma processing method and device capable of controlling the etching mask shape during a single-step process that etches a target material disposed below the etching mask. The plasma processing method includes performing selective deposition on the etching mask in separate phases, which are controlled via a periodic bias voltage signal. By tuning the bias voltage power, duration and timing, the mask height and width can be controlled and stabilized while etching on the substrate proceeds. Thus, the present method provides an etching process that allows fine control of the etching mask shape for small pattern sizes and provides high etching selectivity through deposition.

Embodiments of the present disclosure generally relate to methods for etching a carbon hard mask to have improved etching selectivity and profile control. In some embodiments, a method is provided for processing a carbon hard mask layer, which includes positioning a workpiece within a process area of ​​a processing chamber, wherein the workpiece has a carbon hard mask layer positioned on or throughout the underlying layer, and processing the carbon hard mask layer by exposing the workpiece to a sequential penetration synthesis (SIS) process to produce an alumina-carbon hybrid hard mask denser than the carbon hard mask layer. The SIS process includes exposing the carbon hard mask layer to an aluminum precursor to penetrate the carbon hard mask layer with the aluminum precursor, purging and removing gaseous residues, exposing the carbon hard mask layer to an oxidizing agent to penetrate the carbon hard mask layer with the oxidizing agent to produce an alumina coating positioned on the inner surface of the carbon hard mask layer, and purging the process area to remove gaseous residues.

The present disclosure discloses a semiconductor device, electronic device, and preparation method. Wordline trenches are first formed on a semiconductor substrate, followed by forming a wordline structure in the wordline trenches, and then forming an active area. This allows the wordline trenches to pass through the semiconductor substrate without requiring them to pass through other materials. Because the semiconductor substrate is made of uniform material, etching selectivity issues are eliminated, allowing the bottom surface of the formed wordline trenches to be flat. When forming the wordline structure in the wordline trenches, the wordline structure can be in direct contact with the semiconductor substrate without requiring it to contact other materials. This allows the bottom surface of the wordline structure to be flat, thereby improving the performance and reliability of the semiconductor device.

This application discloses the formation of vias using imprint lithography and the formation of repositioning vias by imprint lithography. A resist layer is formed on top of a dielectric layer. For example, a pattern of via openings is imprinted in the resist layer using nanoimprint lithography. After imprinting, the pattern of via openings imprinted in the resist layer is transferred to the dielectric layer by anisotropic etching to form via openings in the dielectric layer. Anisotropic etching has low etch selectivity between the resist layer and the dielectric layer. The via openings in the dielectric layer are filled with a conductive material to form vias in the dielectric layer. The centerline of at least one repositioning via is not parallel to the centerline of at least one other via.

A pixel according to one embodiment of the present application includes: first and second electrodes spaced apart from each other; a first insulating layer having a first etching selectivity; a first insulating pattern having a second etching selectivity; a light emitting element including first and second ends; a second insulating pattern disposed on one region of the light emitting element to expose the first and second ends of the light emitting element and having the second etching selectivity; and third and fourth electrodes electrically connecting the first and second ends of the light emitting element to the first and second electrodes, respectively.

The invention relates to a display device, an electronic device, and a method of manufacturing the display device. The display device includes: a substrate; a first pixel electrode and a second pixel electrode arranged to be separated from each other over the substrate; a first bank layer disposed on the first pixel electrode and the second pixel electrode and including a 1-1 opening over the first pixel electrode and a 2-1 opening over the second pixel electrode; a second bank layer disposed on the first bank layer and including a 1-2 opening over the first pixel electrode and a 2-2 opening over the second pixel electrode; and a wiring layer disposed on the second bank layer and including a portion disposed between the first pixel electrode and the second pixel electrode, in which the first bank layer includes a first inorganic insulating material, and the second bank layer includes a second inorganic insulating material having a different etching selectivity from the first inorganic insulating material.

The present application provides an organic compound, a photoresist containing the same and applications thereof, the organic compound has a structure as shown in formula I, through the design of molecular structure, it has the function of antioxidant, can effectively improve the etching performance of photoresist in dry etching as a photoetching aid. The photoresist containing the same has excellent etching performance and developing property, especially has excellent etching selectivity, can prevent the appearance of photoresist edge line from excessive etching, the slope is large, the line width is small and other abnormal morphology, can effectively reduce and avoid the problem of etching residue and subsequent stripping difficulty, significantly optimizes the etching morphology, can fully meet the processing demand of high precision, fine pattern / line.

The application provides a preparation method of a semiconductor device, and belongs to the technical field of semiconductors. The preparation method comprises the following steps: taking a third mask layer as a mask, etching a first dielectric layer by using a first etching process and stopping on a first mask layer and a second mask layer, etching the first mask layer and the second mask layer by using a second etching process with high selectivity and stopping on an anti-reflection dielectric layer, and etching the anti-reflection dielectric layer by using a third etching process with high selectivity and stopping on a second metal layer. Through step-by-step etching and etching selectivity control, a through hole is formed on metal layers with different heights at the same time, the etching amount on the first metal layer is sufficient, the second metal layer cannot be etched through, process damage is reduced, and process precision and yield are improved.

To provide a semiconductor device.SOLUTION: A method of a semiconductor device fabrication includes a step of forming a vertical structure in a layer stack by processing a first surface of a first die, and the vertical structure has an edge part in the first layer. The first layer has a better etch selectivity to a layer stack than a second layer (S310). The method further includes a step of replacing the first layer with a second layer by processing a second surface of the first die opposite the first surface (S320).SELECTED DRAWING: Figure 3

An electromechanical systems structure including: providing a stack, including a structural layer extending in a plane, a sidewall layer including a first portion lying in a plane parallel to the structural layer plane and a second portion lying in a plane transverse to the structural layer plane, an etch-stop layer, positioned between the sidewall layer and the structural layer, including an etch-selectivity different from an etch-selectivity of the structural layer and an etch-selectivity of the sidewall layer, and a mold comprising a wall parallel to the sidewall layer's second portion; etching the sidewall layer's first portion to expose the etch-stop layer; removing the mold; etching the etch-stop layer such that the sidewall layer's second portion masks a portion of the etch-stop layer; removing the sidewall layer's second portion; and etching the structural layer such that the portion of the etch-stop layer masks a portion of the structural layer.

A semiconductor device manufacturing method includes: forming an inorganic layer on a support layer; forming an organic mask pattern on the inorganic layer; and forming inorganic patterns and spacing patterns configured to at least partially expose the support layer between the inorganic patterns by performing a plasma etching process on the inorganic layer using the organic mask pattern as an etching mask. The plasma etch process has an etch selectivity that facilitates the inorganic layer relative to the organic mask pattern. A plasma etching process is performed on the inorganic layer by using a mixed gas including a C2H2F4 gas as a primary etching gas and an O2 gas or an oxygen-containing gas as an auxiliary etching gas, the ratio of the primary etching gas to the auxiliary etching gas being configured to be about 1 to about 5.

Embodiments of the present disclosure are directed to selective etch processes. The process includes flowing a precursor into a semiconductor processing chamber containing a substrate, the precursor including one or more of an inter-halogen compound, a halogen-containing species, a pseudo-halogen species, a mixture of one or more of the inter-halogen compound, the halogen-containing species, or the pseudo-halogen species and an amine or phosphine, or a mixture of one or more of an inter-halogen compound, a halogen-containing species or a pseudo-halogen species and a sulfur-containing species, and an activating species that forms a precursor to etch the substrate. The substrate has a plurality of alternating layers of silicon oxide and silicon nitride thereon and trenches formed through the plurality of alternating layers. The silicon nitride layer is selectively etched with respect to the silicon oxide layer with an etch selectivity greater than or equal to 500: 1.

The invention relates to a silicon-containing resist film forming composition and a pattern forming method. The present invention is a silicon-containing composition for forming a resist film, which forms an ultra-fine resist pattern having excellent LWR and CDU, which forms a resist film having high etching selectivity with an organic material, and which does not cause defects due to residues remaining after the completion of patterning, and a pattern forming method. A silicon-containing composition for forming a resist film, which contains a polysiloxane that contains at least one of a repeating unit represented by formula (A-1), a repeating unit represented by formula (A-2), and a partial structure represented by formula (A-3). (In the formula, R1 is a C1-30 monovalent organic group which may have a substituent and acts as a leaving group by heat, an acid or a base, a halogen atom, a hydroxyl group, a sulfo group, a nitro group or a carboxyl group, and R2 and R3 each independently represent a C1-30 monovalent organic group which may have a substituent.

An embodiment of the present invention increases the etching resistance of a photoresist in an EUV PR / SiON pattern using an ion beam etching apparatus to which grid pulsing is applied, so that the photoresist is etched less and SiON is etched more, thereby improving the etching selectivity. According to an embodiment of the present invention, it is possible to improve the LER through repetition of constant etching and deposition, thereby reducing process defects and enabling damage control.

To provide an ashable carbon hard mask (AHM) having high etching selectivity and low stress, in order to enable high aspect ratio (HAR) etching.SOLUTION: A method for accumulating a carbon ashable hard mask layer on a substrate includes: a step 610 of arranging a substrate in a treatment chamber; a step 614 of setting a chamber pressure to be within a predetermined pressure range, and setting a substrate temperature to be within a predetermined temperature range between -20°C and 200°C; a step 618 of supplying a gas mixture containing a hydrocarbon precursor and one or more other gases; and steps 622 to 632 of generating plasma by supplying RF plasma power in a first predetermined period, and accumulating a carbon ashable hard mask layer on a substrate.SELECTED DRAWING: Figure 6

The invention relates to the technical field of semiconductor manufacturing, and discloses a titanium etching solution preparation process based on a hydrogen peroxide-monoethanolamine system.The titanium etching solution comprises, by mass, 5%-15% of hydrogen peroxide, 5%-15% of monoethanolamine, 5%-15% of sodium hydroxide and the balance water. 5%-10% of monoethanolamine; 2%-5% of tris (hydroxymethyl) aminomethane; 0.5% to 1.5% of 2, 2 '-dipyridyl; and 0.1%-0.5% of a double-effect stabilizing and indicating agent. Trihydroxymethyl aminomethane and 2, 2 '-dipyridyl cooperate to stabilize hydrogen peroxide, and a stable pH buffer system is constructed. The key double-effect stabilizing agent and the indicator (such as salicylic acid) can be subjected to complexing chromogenic reaction when the etching product titanium ions are accumulated to reach a threshold value, so that the self-indication function of solution failure is realized. The invention discloses a preparation process for dropwise adding hydrogen peroxide under cooling and temperature control conditions. The titanium etching solution disclosed by the invention has the beneficial effects of high chemical stability, good Ti / Cu etching selectivity and in-situ failure early warning function.

The present invention relates to an intelligent wafer etching process in the field of information technology, comprising: obtaining etching rates of different materials under various chemical solution formulations, constructing an etching rate database covering various material systems, screening out material combinations with high etching selectivity by comparing etching rate differences in the database, and determining a targeted optimization direction for the chemical solution formulation; installing a multi-parameter online monitoring unit in the etching equipment, using an optical fiber spectrometer to measure chemical solution concentration in real time, and using a thermocouple and a pH electrode to measure chemical solution temperature and pH in real time; when the monitored parameters exceed a set range, starting a chemical solution ratio adjustment program, and realizing dynamic regulation of chemical solution properties by controlling liquid inlet and outlet volumes, thereby ensuring the stability and consistency of the etching process.