398 results about "Etching selectivity" patented technology

A method of fabricating a field effect transistor (FET) over a substrate that includes: growing a doped p-type semiconductor from a silicon nanosheet of the substrate, the substrate including a layer stack of alternating layers of the silicon nanosheet and a sacrificial layer, and a dummy gate formed over the layer stack, the layer stack including a trench exposing sidewalls of the layer stack, the doped p-type semiconductor and the sacrificial layer being separated by a dielectric inner spacer; removing the dummy gate; and etching the sacrificial layer selectively to the doped p-type semiconductor, the etching including exposing the substrate to a process gas including a fluorocarbon and a fluorine-containing etch gas in the absence of plasma.

A method includes: forming a stack of semiconductor nanostructures on a semiconductor fin; forming a source / drain opening adjacent the stack; forming a bottom dielectric layer on the semiconductor fin; forming a source / drain region in the source / drain opening, a void being present between the source / drain region and the bottom dielectric layer; forming a dielectric layer on the source / drain region; forming a hardened portion of the dielectric layer by treating the dielectric layer, the hardened portion having higher etch selectivity than other portions of the dielectric layer; removing the other portions of the dielectric layer, exposing the void; forming a source / drain contact opening that extends to and connects with the void, the source / drain contact opening exposing sidewalls of the source / drain region; forming a liner layer on exposed surfaces of the source / drain region; and forming a conductive core layer on the liner layer, the conductive core layer being in contact with the liner layer on a top surface, sidewalls and a bottom surface of the source / drain region.

The invention relates to an intelligent wafer etching process in the technical field of information, and the process comprises the steps: obtaining the etching rates of different materials under various liquid medicine formulas, constructing an etching rate database covering various material systems, screening out a material combination with high etching selectivity by comparing the etching rate differences in the database, and carrying out the etching of the material combination. Determining a targeted liquid medicine formula optimization direction; a multi-parameter online monitoring unit is installed in etching equipment, the concentration of liquid medicine is measured in real time through an optical fiber spectrometer, the temperature and the pH value of the liquid medicine are measured in real time through a thermocouple and a pH electrode, when monitoring parameters exceed a set range, a liquid medicine proportion adjusting program is started, and dynamic regulation and control over the property of the liquid medicine are achieved by controlling the liquid inlet amount and the liquid outlet amount. And the stability and the consistency of the etching process are ensured.

The invention discloses an integrated circuit equipment data optimization monitoring system and method based on big data, and relates to the technical field of integrated circuit manufacturing. The method is used for solving the problems of insufficient multi-physical field monitoring, difficulty in abnormal traceability and lack of closed-loop control in plasma etching. A plasma sheath thickness inversion model and an etching selection ratio model are constructed by collecting radio frequency reflection phase, mass spectrum ion strength and wafer temperature data, and process parameter-plasma state dynamic coupling is established. Interference image distortion features and electron microscope size data are fused, micro-groove geometric parameters are analyzed, morphology instability risk indexes are generated, and nanoscale early warning is achieved. And designing a dual-channel fusion network, embedding a physical constraint attention mechanism, and generating an etching rate optimization instruction. On the basis of incremental learning, model parameters are updated online, a'monitoring-decision-feedback 'closed-loop system is formed, anomaly detection sensitivity and decision reliability are improved, and technical support is provided for intelligence of integrated circuit equipment.

A method of manufacturing a structure having multi metal layers includes: depositing a top metal layer on a bottom metal layer; forming a patterned photoresist on the top metal layer; etching the top and bottom metal layers through first hollow portions of the patterned photoresist to respectively form a top metal pattern and a bottom metal pattern; forming a second hollow portion in the patterned photoresist to expose a portion of the top metal pattern; etching the top metal pattern through the second hollow portion until a top surface portion of the bottom metal pattern is exposed by the etched top metal pattern, in which an etch selectivity of the top and bottom metal layers in the etching the top metal pattern is greater than 1.0; and anodizing the top surface portion to form an anodized segment of the bottom metal layer.

A bottom electrode is deposited on a substrate. A dielectric layer is deposited on the bottom electrode. One or more structures are patterned within the dielectric layer. A liner layer is deposited on top of the dielectric layer and the bottom electrode. A selectivity promotion layer is deposited on top of the liner layer. The selectivity promotion layer is etched to expose a top surface of the dielectric layer and a portion of the bottom electrode. A phase change memory material layer is deposited within a void of the one or more structures between the selectivity promotion layer.

Apparatuses and methods are provided. Some methods may include providing a substrate to a processing chamber, the substrate having a first material adjacent to and covering a surface of a second material, modifying a layer of the first material by flowing a first process gas onto the substrate and thereby creating a modified layer of the first material, removing the modified layer of the first material by flowing a second process gas onto the substrate, and converting, when the surface of the second material is uncovered via removal of the modified layer, the surface to a converted layer of the second material by flowing a third process gas onto the substrate, in which the first and second process gases are less reactive with the converted layer than with the first material and the second material.

The invention provides an IGBT (Insulated Gate Bipolar Translator) device structure and a preparation method thereof. The preparation method comprises the following steps: forming a plurality of gate trenches in an active region, and forming a gate oxide layer and a polycrystalline silicon layer; forming a grid line mask pattern; forming a polysilicon gate line, and reserving a gate line mask pattern on the polysilicon gate line; a hard mask medium is deposited, a first window and a second window which expose the surface of the active area are formed, and the second window exposes the grid line mask pattern on the grid line; etching is carried out, based on the etching selection ratio, the semiconductor substrate in the first window is partially removed to form an emitter region contact hole, and the grid line mask pattern in the second window is not removed to protect the grid line; and removing the grid line mask pattern in the second window by a wet method to form a grid line contact hole. According to the invention, the preparation of the emitter region contact hole and the line contact hole only needs to use one mask plate for photoetching and etching, compared with the traditional process, one mask plate is effectively reduced, the process flow is simplified, the production period is shortened, and the production efficiency is improved while the tape-out cost is reduced.

A method of manufacturing a structure having anodized parts includes: forming a bottom metal pattern with a dielectric layer thereon on a substrate, in which the dielectric layer has an opening exposing the bottom metal pattern; forming a semiconductor layer to cover the dielectric layer; forming a first metal layer on the semiconductor layer; forming a second metal layer on the first metal layer; forming a mask layer on the second metal layer to expose a portion of a top surface of the second metal layer; etching the second metal layer through the mask layer until a top surface of the first metal layer is exposed, in which an etch selectivity of the second metal layer and the first metal layer is greater than 2.0; anodizing the first metal layer through the mask layer to form an anodized segment; and removing the mask layer.

The present disclosure provides a manufacturing method of a semiconductor structure, including: an insulating layer includes a first dielectric layer and a second dielectric layer, a protective layer covers an upper surface of the second dielectric layer and a bottom and sidewalls of the first trench; removing part of the protective layer to expose at least part of a surface of the second dielectric layer; removing the second dielectric layer by a first wet etching process, the first wet etching process has a first etch selectivity of a material of the second dielectric layer to that of the first dielectric layer; and removing the protective layer by a second wet etching process, the second wet etching process has a second etch selectivity of a material of the protective layer to that of the first dielectric layer, and the second etch selectivity is greater than the first etch selectivity.

An in situ protective coating is deposited on surfaces of chamber components of a reaction chamber at high temperatures. The in situ protective coating may be deposited at a temperature greater than about 200° C. to provide a high quality coating that is resistant to certain types of halogen chemistries, such as fluorine-based species, chlorine-based species, bromine-based species, or iodine-based species. Subsequent coatings or layers may be deposited on the in situ protective coating having different etch selectivities than the underlying in situ protective coating. The in situ protective coating may be deposited throughout the reaction chamber to deposit on surfaces of the chamber components, including on chamber walls.

Provided is a plasma processing method and device capable of controlling the etching mask shape during a single-step process that etches a target material disposed below the etching mask. The plasma processing method includes performing selective deposition on the etching mask in separate phases, which are controlled via a periodic bias voltage signal. By tuning the bias voltage power, duration and timing, the mask height and width can be controlled and stabilized while etching on the substrate proceeds. Thus, the present method provides an etching process that allows fine control of the etching mask shape for small pattern sizes and provides high etching selectivity through deposition.

A trench in a semiconductor substrate is lined with a first insulation layer. A hard mask layer deposited on the first insulation layer is used to control performance of an etch that selectively removes a first portion of the first insulating layer from an upper trench portion while leaving a second portion of first insulating layer in a lower trench portion. After removing the hard mask layer, an upper portion of the trench is lined with a second insulation layer. An opening in the trench that includes a lower open portion delimited by the second portion of first insulating layer in the lower trench portion and an upper open portion delimited by the second insulation layer at the upper trench portion, is then filled by a single deposition of polysilicon material forming a unitary gate / field plate conductor of a field effect rectifier diode.

The present: invention addresses the problem of providing a silicon nitride etching liquid composition which is capable of selectively etching Si3N4 with a practical etching selectivity with respect to SiO2, while suppressing regrowth of SiO2, and which is also capable of suppressing pattern collapse of an SiO2 film in the production of a 3D nonvolatile memory cell. A silicon nitride etching liquid composition for producing a 3D nonvolatile memory cell, which contains phosphoric acid, one or more silane coupling agents and water, but which does not contain ammonium ions.

Apparatuses and methods are provided. Some methods may include providing a substrate to a processing chamber, the substrate having a first material adjacent to and covering a surface of a second material, modifying a layer of the first material by flowing a first process gas onto the substrate and thereby creating a modified layer of the first material, removing the modified layer of the first material by flowing a second process gas onto the substrate, and converting, when the surface of the second material is uncovered via removal of the modified layer, the surface to a converted layer of the second material by flowing a third process gas onto the substrate, in which the first and second process gases are less reactive with the converted layer than with the first material and the second material.

The present invention relates to a processing method for a gradient film layer and a processing method for a gradient-depth micro-nano structure. The processing method for the gradient film layer includes the following steps: fixing a planar film layer on the surface of a substrate; forming a sacrificial film layer with a gradually changing thickness on the surface of the planar film layer through gradient coating and / or exposure and development; based on the etching selectivity ratio, removing the sacrificial film layer and the planar film layer above the gradient surface in sequence through dry etching to obtain a substrate with a gradient film layer; the processing method for the gradient-depth micro-nano structure includes the following steps: forming a photoresist film on the surface of the gradient film layer and patterning the photoresist film in the gradient structure region; through etching and resist removal, removing the photoresist film and the gradient film layer in the gradient structure region in sequence, and after the etching is completed, through post-treatment, a gradient-depth micro-nano structure is obtained. The present invention has the effects of improving the processing flexibility, increasing the thickness control range of the gradient film layer, and obtaining a gradient-depth micro-nano structure with a continuous depth change.

A substrate-treatment method includes (a) providing a substrate at a stage, the substrate including a silicon nitride-containing film, in which a recess defined by a top, a side wall, and a bottom is formed, and a silicon film exposed from the bottom of the recess; (b) forming a silicon oxide film along the recess; (c) exposing the silicon oxide film to a plasma of a process gas containing a hydrogen gas, thereby modifying the silicon oxide film at the top and bottom of the recess selectively relative to the side wall by an anisotropic plasma treatment; and (d) selectively removing the modified silicon oxide film at the top and bottom of the recess through chemical etching without using a plasma, thereby retaining the silicon oxide film at the side wall of the recess.

A method includes forming an epitaxial source / drain region in a substrate; forming a first inter-layer dielectric over the epitaxial source / drain region; forming a gate stack over the substrate and adjacent to the first inter-layer dielectric; forming a gate mask over the gate stack; forming a source / drain plug through the first inter-layer dielectric and electrically connected to the epitaxial source / drain region; depositing a dielectric layer over the gate mask and the first inter-layer dielectric, the dielectric layer having a different etch selectivity than the gate mask; forming a second inter-layer dielectric over the dielectric layer; etching an opening through the second inter-layer dielectric and the dielectric layer, the opening exposing the source / drain plug and the gate mask; and forming a conductive feature in the opening, the conductive feature being electrically connected to the source / drain plug.

Provided is an etching solution composition capable of preventing reduction in the etching rate of a silicon nitride film, achieving high etching selectivity with respect to silicon nitride, and suppressing deposition of silica on the surface of silicon oxide.　This etching solution composition is based on an inorganic acid and is for selectively etching silicon nitride from a semiconductor containing the silicon nitride and silicon oxide, and comprises: (a) a fluorine compound that increases the etching rate of silicon nitride; and (b) a volatilization inhibitor that inhibits volatilization of the fluorine compound.

To provide an etching solution with a high etching selectivity of silicon carbonitride to silicon and silicon oxide, a method for processing a substrate including the step of bringing the etchant in contact with the substrate, and a method for manufacturing a semiconductor device including the step of processing the substrate.SOLUTION: There is provided an etchant for etching silicon carbonitride containing phosphoric acid, water, cerium ions, and an Si source. Further, there is provided a method for processing a substrate, including the step of bringing the etchant into contact with a substrate which has a silicon carbonitride film and contains silicon. Furthermore, there is provided a method for manufacturing a semiconductor device including the method for processing.SELECTED DRAWING: None

The invention provides a composition, application thereof and a preparation method of a semiconductor device. The composition comprises the following components in percentage by mass: 5-50% of a first aprotic organic solvent; 5%-30% of a second aprotic organic solvent; 0.01%-5% of an acid; 0.15%-5% of a corrosion inhibitor; 10%-85% of water; the corrosion inhibitor comprises amino acid with the molecular weight larger than or equal to 100. The composition provided by the invention can be mixed with an oxidizing agent for use, etching residues on the surface of a patterned substrate can be effectively cleaned after mixing, a part of a hard mask on the patterned substrate can be selectively removed while a metal material in the patterned substrate is effectively protected, and the etching selection ratio of the hard mask to the metal material is improved.

The invention provides a dry etching method for a molybdenum silicide layer, and relates to the field of semiconductor mask plates. The method is used for performing dry etching pattern transfer on the molybdenum silicide phase shift layer in the phase shift mask. The method comprises the following steps of: 1, putting a patterned molybdenum silicide layer into an ICP (Inductively Coupled Plasma) dry etching machine; 2, mixed SF6 gas and Ar gas are introduced into the etching cavity; and 3, the plasma concentration is regulated and controlled by controlling the ICP source, the plasma bombardment kinetic energy is regulated and controlled through the RF source, and etching of the molybdenum silicide layer is completed. According to the dry etching method, SF6 and Ar are adopted as etching gas, a good etching selection ratio and good morphology can be obtained by controlling the gas proportion, the ICP power and the RF power, and the dry etching method has the advantages of being good in safety, low in production cost and the like.

A method of manufacturing a semiconductor device includes depositing a first dual layer structure over a substrate, wherein the first dual layer structure includes a silicon oxide layer and a silicon nitride layer over the silicon oxide layer; forming a first carbonaceous hard mask on the first double-layer structure; forming a second double-layer structure on the first carbonaceous hard mask; forming a mask stack of alternating anti-reflective coating (ARC) hard masks and second carbonaceous hard masks on the second bilayer structure; and coating a photoresist on the mask stack. Since the first double-layer structure containing silicon nitride and silicon oxide is used in the manufacturing method of the semiconductor device, the etching selectivity of oxide to nitride can help to control the shape of an array active region, and thus sidewall damage is reduced, and tip-to-tip depth and side-to-side depth are improved.

A technique enabling wet etching of a first silicon oxide film with high selectivity with respect to a metal film and a second silicon oxide film is provided. A substrate processing method of wet-etching a substrate having a stacked structure including a metal film, a first silicon oxide film, and a second silicon oxide film having a moisture content lower than that of the first silicon oxide film is provided. The substrate processing method includes performing an etching while increasing etching selectivity of the first silicon oxide film with respect to the second silicon oxide film and the metal film by supplying an etching liquid, which is prepared by diluting sulfuric acid, hydrogen peroxide and hydrofluoric acid in an anhydrous organic solvent, to the substrate such that the metal film, the first silicon oxide film, and the second silicon oxide film are simultaneously exposed to the etching liquid.

A method for forming a semiconductor structure, the method comprising: providing a substrate, the substrate having a stack structure formed thereon, the stack structure comprising one or more channel stacks stacked in sequence from bottom to top, each channel stack comprising a placeholder layer and a channel layer on the placeholder layer, the substrate further having a dummy gate structure formed thereon, the dummy gate structure spanning across the stack structure and covering part of the top and part of the sidewall of the stack structure; forming a recess through the stack structure on both sides of the dummy gate structure; removing a part of the length of the placeholder layer exposed by the sidewall of the recess along the extension direction of the channel layer to form an inner trench; forming an inner spacer material layer on the sidewall of the dummy gate structure and on the sidewall of the recess, the inner spacer material layer also filling in the inner trench; and performing a modification treatment on the inner spacer material layer outside the inner trench for converting the inner spacer material layer into a sacrificial layer, the sacrificial layer having an etching selectivity ratio with the inner spacer material layer and the channel layer. The embodiments of the present application are beneficial to the performance of the semiconductor device.

The invention discloses a monocrystalline silicon wafer alkali polishing additive and a preparation method and application thereof, and the alkali polishing additive comprises the following components by mass content: 0.5-4% of a reaction accelerator, 2-5% of a corrosion and scale inhibitor, 1.5-3% of a chelating agent, 1-3% of a pH regulator, 1-5% of a surfactant, 3-10% of a cosolvent and the balance of water according to the total mass of 100%. The alkali polishing additive is obvious in performance gain, good in etching selectivity and small in silicon wafer weight loss; the back polishing effect can be improved, the reflectivity of the silicon wafer is high, and the photoelectric conversion efficiency of a photovoltaic cell is improved; the anti-crystallization performance is excellent, and the environment is protected.

The invention provides a preparation method of a bump region window, and belongs to the technical field of semiconductors. The method comprises the following steps: preparing a matrix structure, wherein the matrix structure comprises a base layer and at least one bulge structure positioned on the top surface of the base layer; sequentially depositing a dielectric film layer and a protective film layer on the substrate structure; the protective film layer is etched under a first etching condition so that the protective film layer can be thinned to be lower than the top end of the dielectric film layer of the protruding structure, and under the first etching condition, the etching selection ratio of the protective film layer to the dielectric film layer is larger than 1: 1; the dielectric film layer is etched under a second etching condition, so that the distance between the top end of the dielectric film layer and the top end of the protruding structure is a target height difference, and the etching selection ratio of the dielectric film layer to the protective film layer is larger than 5: 1 under the second etching condition; and removing the protective film layer to form a window in the top area of the convex structure. According to the preparation method, the position precision of the window can be ensured.

A substrate processing method according to the present invention incudes: a preparation step of preparing a substrate in which at least a first surface containing silicon oxide and a second surface containing silicon or a silicon compound other than silicon oxide are exposed; a surface modification step of forming an etching selectivity imparting film on at least a part of the first surface and at least a part of the second surface by a silylation treatment of bringing a silylating agent into contact with the first surface and the second surface; and an etching step of selectively carrying out an etching treatment on the second surface with respect to the first surface using an etching agent after the surface modification step.

Embodiments of the present disclosure provide an interposer and a method of forming the same, and the method includes: providing a baseplate; forming a pattern transfer layer including a plurality of pattern regions spliced together on the baseplate, different pattern regions correspond to different lithographic templates, a splicing region of at least two pattern regions is an overlapping region, and any one of the lithographic templates includes a pattern composed of an exposed region for exposure and a masked region for masking; preprocessing the pattern transfer layer so that the plurality of pattern regions of the pattern transfer layer have different etching selectivity ratios in corresponding exposed regions and masked regions based on patterns of corresponding lithographic templates; etching the pattern transfer layer after preprocessed to form the patterns of corresponding lithographic templates on the pattern transfer layer; and patterning the baseplate using the pattern transfer layer as a mask. The embodiments of the present disclosure improve the device quality of the interposer.

An etching gas composition includes a first organofluorine compound having 3 to 6 carbon atoms, and an organosulfur compound having 1 to 4 sulfur atoms. The organosulfur compound may include a carbon-fluorine (C—F) bond, a carbon-sulfur (C—S) bond, at least one carbon-carbon double (—C═C—) bond. When the etching gas composition is used, excellent etch selectivity may be obtained, and the linearity and verticality of a pattern may be greatly increased by improving line edge roughness (LER) and line width roughness (LWR) due to an improvement in the roughness of an etched surface.