Patents
Literature
Patsnap Copilot is an intelligent assistant for R&D personnel, combined with Patent DNA, to facilitate innovative research.
Patsnap Copilot

213results about How to "Etching speed is fast" patented technology

Wire-width-variable laser galvanometer scanning quick etching method and device

The invention discloses a wire-width-variable laser galvanometer scanning quick etching method and device. The principle that after laser beam is defocused, the power density gradient becomes small, and a light spot becomes large is used, a high-speed galvanometer scanning error accurate correcting method is used, by setting different focusing and defocusing laser processing distances and corresponding power parameters and laser galvanometer scanning parameters, the size of the laser light spot is controlled, large light spot raster scanning filling after defocusing is carried out is on an image filling zone, and then an image contour is subjected to vector scanning drawing. For different working distances, galvanometer scanning error correcting is carried out first, a high-accuracy galvanometer scanning locating table is formed, and the fact that the same high-accuracy galvanometer scanning locating effect is obtained at different laser processing distances is guaranteed. Quick accurate etching on images with different wire widths can be achieved, etching accuracy and processing speed are considered at the same time, the method and device can be widely used a plane etching system and a three-dimensional laser etching system, and the processing efficiency of equipment is improved.
Owner:武汉飞能达激光技术有限公司

Silicon through hole etching method

The invention provides a silicon through hole etching method and belongs to the field of micro nano machining of micro electro mechanical systems, and the method can be used for solving the problems that the side wall of a substrate generates ripples, a photoresist can be easily damaged and metal pollution is caused when an existing Bosch process and a metal mask are utilized to carry out deep silicon etching. The method provided by the invention comprises a pattern preparation step, an etching step, a culture slice adding step, a penetrating step and a photoresist removing step. In the etching step, processing is stopped after circulative and alternative etching is finished, so that the photoresist is cooled and the protective action of the photoresist is prevented from being reduced; then circulative etching is carried out again; passivating gas is added into etching gas; and the etching gas is added into the passivating gas for improving the smoothness of the side wall. In the culture slice adding step, a silicon wafer is adhered to the upper surface of a culture slice,thus preventing silicon wafer fracture and equipment damage after etching penetration. The method provided by the invention has the advantages that the process is simple and the etching speed is quick; the photoresist utilized as the mask can be easily removed after being etched, and metal pollution is avoided; the verticality of the side wall of a through hole is easily controlled; the smoothness of the side wall is improved; and the ripples on the side wall are eliminated.
Owner:HUAZHONG UNIV OF SCI & TECH

Method for manufacturing oxide layer capable of reducing gradient of side wall

The invention provides a method for manufacturing an oxide layer capable of reducing the gradient of a side wall. In the prior art, silicon oxide is directly subjected to photoetching and wet etching without being washed with hydrofluoric acid buffer corrosive liquid so as to result in larger gradient of the side wall. The method comprises the following steps: firstly, growing the silicon oxide on a silicon substrate through thermal oxidation process; secondly, washing the silicon oxide by using the hydrofluoric acid buffer corrosive liquid, and drying the silicon oxide; thirdly, coating photoresist on the silicon oxide, and baking the photoresist; fourthly, forming a graph of the oxide layer on the photoresist by exposure process; fifthly, developing the graph; sixthly, etching the graph by using the hydrofluoric acid buffer corrosive liquid to form the oxide layer; and finally, removing the photoresist. The method effectively reduces the compactness of the surface of the oxide layer and the adherence force of the oxide layer with the photoresist by washing the silicon oxide with the hydrofluoric acid buffer corrosive liquid before the photoetching and the wet etching processes, thereby effectively reducing the gradient of the side wall, and effectively improving the performance of a device.
Owner:SHANGHAI HUAHONG GRACE SEMICON MFG CORP

Electrochemical processing method for micro-structure of P type silicon surface

The invention provides an electro-chemical processing method of a P-typed silicon surface micro-structure, relating to the processing of silicon surface. The invention provides a novel electro-chemical processing method which has low cost and simple processing steps, does not have complex processes such as mask lithography, etc., and with micro-structure etched and is processed on the surface of the P-typed silicon in one-step. The electro-chemical processing method comprises the steps that: the micro-structure on an original mother blank is transferred onto a gelose surface and then dipped in electrolyte, so as to gain the gelose gel template with the stored electrolyte; the gelose gel template is then arranged in an electrolytic cell, the micro-structure part of which is exposed on the liquid surface; a Pt layer is splashed on the back surface by the P-typed silicon through a front disposal to form an ohm contact; a polished surface is then arranged on the surface of the gelose gel template; the P-typed silicon sheet is taken as a working electrode and the electro-chemical polishing micro-processing is carried out to the P-typed silicon sheet; the micro-structure on the gelose gel template is transferred on the surface of the P-typed silicon by the electro-chemical polishing micro-processing to gain the P-typed silicon sheet with the micro-structure and the P-typed silicon sheet with the micro-structure is separated from the gelose.
Owner:XIAMEN UNIV
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products