145results about How to "Improve the selection ratio" patented technology

The invention relates to a silicon nitride film etching solution, comprising first silicone compound, whose silicone atom is dependently combined with over three hydrophilic functional groups, and second silicone compound, whose silicone atom is dependently combined with one or two hydrophilic functional groups.

There is provided a plasma etching device for generating plasma as a processing gas between an upper electrode (34) and a lower electrode (16) and subjecting a wafer (W) to plasma etching. The upper electrode (34) includes a variable DC power source (50) for applying DC voltage so that the absolute value of the self bias voltage Vdc on the surface of the upper electrode (34) becomes large enough to obtain an appropriate sputter effect to the surface and the thickness of the plasma sheath on the upper electrode (34) becomes thick enough to form a desired miniaturization plasma.

The present invention discloses a kind of chemical and mechanical water-free polishing liquid for polishing lithium-cesium borate crystal and its polishing method. The polishing liquid of the present invention consists of nanometer silica abrasive 4-8 wt%, organic solvent 72-95 wt%, organic alkali 0.5-10 wt% and surfactant 0.5-10 wt%. It is used in polishing lithium-cesium borate crystal at polishing pressure of 0.05 MPa to 0.1 MPa, polishing disc speed of 30 rpm to 60 rpm, and polishing time of 5-10 min. The water-free polishing liquid of the present invention has high flowability, no toxicity, no pollutant, no corrosion, moderate concentration and good floatability, and can obtain polished lithium-cesium borate crystal surface with high smoothness and no crack.

The invention discloses a method for etching class-III nitride by using a photo-assisted oxidation wet method, which is characterized by comprising the following steps: step 1, preparing an ultraviolet light masking layer with patterns on the surface of the class-III nitride by using a standard photo-etching process; step 2, placing the class-III nitride of which the surface is provided with the ultraviolet light masking layer with the patterns under high-energy ultraviolet light to be exposed so as to oxidize the exposed class-III nitride with the patterns under the assistance of the ultraviolet light to generate a metal oxide; step 3, removing the masking layer; and step 4, putting a sample of the exposed class-III nitride in acid or alkali solution so that the generated metal oxide is fully eroded to form an etching step with the patterns to finish the process for etching the class-III nitride by the wet method.

There is provided a plasma etching device for generating plasma as a processing gas between an upper electrode (34) and a lower electrode (16) and subjecting a wafer (W) to plasma etching. The upper electrode (34) includes a variable DC power source (50) for applying DC voltage so that the absolute value of the self bias voltage Vdc on the surface of the upper electrode (34) becomes large enough to obtain an appropriate sputter effect to the surface and the thickness of the plasma sheath on the upper electrode (34) becomes thick enough to form a desired miniaturization plasma.

This invention discloses a new forming method of embollishing metal layers containing providing a semiconductor basic material with a dielectric layer and holes then to form a barrier layer on the side wall of the dielectric layer and the holes and surface of the base to carry on at least one time of ALD to form a (continuous metal seed layer) CMSL on the barrier layer in which ALD steps including filling a mixed gas of hydrogen and silane then cleaning and vacuum, then to inlet metal reacting gas to form a CMSL of 20-40 A and to form a nucleation layer of 20-40 A on the CMSL finally.

The invention discloses a bulk silicon machining process based on silicon chip etching and puncturing, which comprises the following steps of preparing a patterned photoresist mask on the surface of a silicon chip; putting a metal film on the back surface of the silicon chip; adhering the metal film to a supporting chip by using vacuum oil, wherein the supporting chip is a silicon chip with an oxide layer on the surface; etching and puncturing the silicon chip to obtain a bulk silicon microstructure by using an inductively coupled plasma dry-etching system, wherein a staged etching method is adopted for inductive coupled plasma dry-etching, and comprises a plurality of etching stages each of which is alternately and cyclically implemented by three steps of passivation, bombardment and etching in an inductive coupled plasma machine, and along with the increasing of the etching depth, the bombardment intensity of the bombardment step in each etching stage is gradually enhanced; removing the photoresist mask and the metal film, and releasing the bulk silicon microstructure. According to the process, the selection ratio of photoresist, the etching depth and the perpendicularity of the sidewall of an etching groove can be effectively increased.

A polishing composition comprising: (a) an abrasive, (b) a compound to form a chelate with copper ions (c) a compound to provide a protective layer-forming function to a copper layer, (d) hydrogen peroxide, and (e) water, wherein the abrasive of component (a) has a primary particle size within a range of from 50 to 120 nm. This is used for polishing a semiconductor device having at least a layer of copper and a layer of a tantalum-containing compound formed on a substrate.

The invention provides a method for making a side wall between a base and an emitter of a high frequency triode. The method comprises a step of providing a substrate, forming an N epitaxial layer, a first polysilicon layer and a first TEOS layer on the surface of the substrate, a step of forming a base region trench which goes through the first polysilicon layer and the first TEOS layer, a step of forming a P type diffusion area at the N epitaxial layer under a first P polysilicon layer, and carrying out base region doping on the N epitaxial layer to form a base region, a step of orderly forming a second polysilicon layer and a second TEOS layer on the base region, in the base region trench and on the first polysilicon layer and the first TEOS layer, a step of etching the second polysilicon layer by using a dry method to form a polysilicon side wall, and a step of using a wet method to corrode the second TEOS layer to remove the second TEOS layer on the first TEOS layer and at the middle part of the base region, and retaining the second TEOS layer which is in contact with the polysilicon side wall, wherein the retained second TEOS layer is taken as the side wall between the base and the emitter.

The invention relates to a semiconductor product insulation layer structure. Both a device substrate (1) and a support substrate (2) are silicon wafers, a film layer (3) is arranged on the device substrate (1) and/or the support substrate (2), the film layer (3) is one of materials as follows, a silicon dioxide layer, a silicon oxynitride layer, a silicon nitride layer, a polysilicon layer and anamorphous silicon layer, and one of the device substrate (1) and/or the support substrate (2) and the other are bonded together through the film layer (3) disposed on at least one of the two to form an integrally multi-layer SOI structure. The invention further relates to a preparation method of the semiconductor product insulation layer structure. The special insulation layer structure is diverse, problems of serious self-heating, serious SOI warpage change caused by high-temperature annealing and poor radio frequency characteristics of an SOI device in the prior art are solved, and relatively expected large economic and social values can be achieved.

This invention relates to a chemical corrosive with high selectivity towards gallium arsenide among gallium arsenide/aluminium arsenide mixture. It uniquely contains citric acid solution and oxydol with a volume ratio of 4:1 and is compatible with gallium arsenide integration technique. Besides, it also has the advantages of nontoxic solution and simple technique.

The invention provides a plasma etching technology comprising a dielectric layer penetrating and etching step and a silicon main etching step, wherein, technical gas in the dielectric layer penetrating and etching step comprises fluorine-base etching gas, first light resistance protection gas and dilution gas; technical gas in the silicon main etching step comprises main etching gas, carbon-base by-product removing gas and second light resistance protection gas. In a preferable embodiment, the fluorine-base etching gas is CF4 or SF6, the first light resistance protection gas is CH2F2 or CHF3 or HBr, and the dilution gas is He, Ar or N2; the main etching gas is Cl2, the carbon-base by-product removing gas is O2, and the second light resistance protection gas is HBr. In semiconductor plasma etching, the invention can improve sidewall steepness in figure etching and prevent the upper edge and the lower edge of a line from producing fillets.

The invention discloses a dual-photoresist. The dual-photoresist comprises a first photoresist layer and a second photoresist layer which are sequentially formed on a target layer, wherein the first photoresist layer is a positive photoresist layer or a negative photoresist layer, and the polarity of the second photoresist layer is opposite to that of the first photoresist layer, and the first photoresist layer and the second photoresist layer are exposed in a same exposure process; the positive photoresist layer adopts a silicon-containing water-soluble positive photoresist. The invention further provides a processing method of the dual-photoresist. By adopting the technical scheme and adopting the fluorine-containing corrosion gas with high selection ratio to the silicon-containing water-soluble positive photoresist, the transferring between patterns of the dual photoresists is precise, and the controllability of the process is improved.

The invention discloses a chemical mechanic buffing liquid of titanium potassium oxide phosphate, which comprises the following parts: 10-90 percent nanometer SiO2 sol, 0.5-10 percent inorganic alkaline and organic alkaline, 0.5-10 percent non-ionic surfactant, 0.5-10 percent chelant and deionized water. The invention can prevent surface fish tail effectively, which improves the surface flatness.

The invention discloses a technological method for etching tungsten gate, pertaining to the field of semiconductor processing and manufacturing; the method comprises the following steps: a semiconductor silicon wafer is moved into a reaction chamber and heated to a high temperature; a first reaction gas is pumped into the reaction chamber; radio frequency power is imposed on the reaction chamber after the airflow of the first reaction gas becomes stable; and then, the first reaction gas etches the tungsten silicide layer or tungsten layer of the semiconductor silicon wafer; after the etching is finished, the pumping of the first reaction gas and the imposing of the radio frequency power are stopped; a second reaction gas is pumped into the reaction chamber; the radio frequency power is imposed on the reaction chamber after the airflow of the second reaction gas becomes stable; the second reaction gas etches the polysilicon layer of the semiconductor silicon wafer; after the etching is finished, the pumping of the second reaction gas and the imposing of the radio frequency power are stooped; and the semiconductor silicon wafer is moved out of the reaction chamber. The technological method improves the selection ratio between the tungsten silicide layer or tungsten layer and the polysilicon layer in the tungsten gate etching technology.

The invention provides a chemi-mechanical polishing fluid for polishing a semiconductor wafer, which is prepared from the following components in percentage by weight: 0.2-5% of acidic pH regulator, 0.01-5% of piperidine nitroxide free radical, 0.1-15% of surfactant, 0.5-20% of grinding particle and the balance of water. The polishing fluid provided by the invention can obviously change the removal rate of silicon nitride under acidic conditions, can regulate the selection ratio of silicon dioxide to silicon nitride, and has the advantages of simple preparation technique, high polishing precision and the like.