29 results about "Silicon etching" patented technology

The application provides a deep silicon etching method and a semiconductor process equipment, and relates to the technical field of semiconductors. The deep silicon etching method comprises a first cycle step and a second cycle step. The first cycle step and the second cycle step both comprise an etching step for etching a silicon substrate to form a groove, a removal step for removing by-products, and a deposition step for forming a protective layer on the sidewall of the groove. The protective gas used in the deposition step of the second cycle step comprises an oxygen-containing gas, and the lower electrode power of the deposition step of the second cycle step is greater than that of the deposition step of the first cycle step. The deep silicon etching method can balance the etching rate of different regions of the isolation groove, optimize the depth micro-loading effect, and improve the depth consistency of the isolation groove. Meanwhile, the deposition step does not consume the mask layer, thereby reducing the consumption of the mask layer, ensuring the effective height of the mask layer, improving the morphology precision of the formed isolation groove and AA, and improving the electrical properties and yield of the product.

The invention provides compositions useful in the etching of polysilicon in the presence of silicon oxide and silicon nitride. The compositions comprise choline hydroxide, an oxidizing agent such as periodic acid, and optionally a surfactant, and are useful in the etching of polysilicon in general, and in particular in both the operation of polysilicon trim as well as polysilicon exhume. The utilization of an added oxidizing agent was found to reduce selectivity of silicon etching based on the silicon crystal orientation, which was found to reduce roughness and the presence of residual silicon residues, such as silicon (111) residues after the etching step.

The application discloses a piezoelectric MEMS device preparation process and a device structure, and relates to the technical field of piezoelectric MEMS device preparation. The preparation process comprises the following steps: forming a groove near an edge region on a front surface of a substrate, depositing a sacrifice layer on the front surface of the substrate and patterning the sacrifice layer, so that the sacrifice layer is separated into a center region and an edge support region, forming a piezoelectric-buffer stack on the sacrifice layer and patterning the piezoelectric-buffer stack, and opening a release hole, the release hole being communicated with the center region of the sacrifice layer, introducing etching medium into the release hole to remove the center region of the sacrifice layer, and then etching a back cavity on the back surface of the substrate. The application limits the size of a diaphragm region through the groove, etches the back cavity of the substrate after the sacrifice layer is released, and compared with a traditional method of defining the diaphragm by etching the back cavity, the application completely avoids the size error of the diaphragm caused by the angle deviation of deep silicon etching, accurately locks the profile of the diaphragm, and greatly improves the size consistency and performance stability of devices in the same batch.

The application provides a silicon-based three-dimensional capacitor and a manufacturing method thereof. The manufacturing method comprises the following steps: preparing a dielectric mask layer on the surface of a silicon substrate, etching a plurality of spaced-apart etching micropores on the dielectric mask layer until the silicon substrate is exposed, etching the plurality of spaced-apart etching micropores by using a deep silicon etching process to form a plurality of spaced-apart first deep holes, removing the remaining dielectric mask layer, preparing a first polysilicon layer on the silicon substrate with the plurality of spaced-apart first deep holes, etching the first polysilicon layer in the first deep holes by using a deep silicon etching process to form second deep holes in the first polysilicon layer in the first deep holes, and the bottom surface and the side surface of the second deep holes are provided with the first polysilicon layer, and growing an insulating dielectric layer, a second polysilicon layer and an electrode layer on the first polysilicon layer on the surface of the first silicon substrate and in all the spaced-apart second deep holes in sequence. The silicon-based three-dimensional capacitor prepared by the application can improve the density of the capacitor.

This application provides a continuous titration method for the sulfuric acid and ammonium nitrate content of silicon etching solution. The continuous titration method includes the following steps: weigh m grams of silicon etching solution sample into a sample bottle, add phenolphthalein indicator, titrate with a first sodium hydroxide standard solution of concentration C1 until a pink color is achieved, and record the volume consumed V1. Calculate the sulfuric acid content. Add neutral formaldehyde solution to the same solution and let it stand for a first preset time to generate a free acid solution. Continue titrating the free acid solution with a second sodium hydroxide standard solution of concentration C2 until the solution turns pink. Gently heat the solution to a preset temperature and maintain this temperature for a second preset time. If the pink color persists, the titration endpoint is determined, and the volume consumed V2 is recorded. Calculate the ammonium nitrate content. This method achieves continuous titration of two components with a single sample, eliminates mutual interference between components, optimizes the endpoint determination method, and thus achieves a simple operation, high accuracy, low sample consumption, and high detection efficiency.

This invention discloses a pneumatic micro-transport device, including an air compressor connected to a pneumatic solenoid valve via an air pump pipe. The pneumatic solenoid valve is connected to a microcontroller via a relay, and the microcontroller is connected to a LabVIEW host computer via a USB interface. The pneumatic solenoid valve is also connected to a micro-transport array via the air pump pipe, and a transport plate is placed above the micro-transport array. This device is designed based on pneumatic principles. Compared to traditional contact-type transport devices, its transport method avoids failures caused by friction-induced wear. Furthermore, thanks to its non-contact transport characteristics, its application range is further expanded. It employs deep silicon etching micromachining technology, with the silicon plate structure serving as the air chamber channel and nozzle of the micro-transport device, significantly reducing the structural size of the micro-transport device, improving space utilization, and solving problems such as low integration in traditional micro-transport devices.

The present application relates to a kind of wafer cutting protection fluid for laser-assisted plasma etching process and its preparation method and application, according to weight parts, the wafer cutting protection fluid includes: water-soluble furan-based polyamide resin 70~85 parts;Solvent 15~25 parts;Plasticizer 1~5 parts;Ultraviolet light absorber 0.1~1 parts;Leveling agent 0.1~1 parts.The wafer cutting protection fluid provided by the present application can form a protective film with excellent mechanical properties, wear resistance and heat resistance, and easy to clean, widely used in thin wafer processing, deep silicon etching and TSV through hole and other processing processes.

This invention provides a double-sided deep silicon etching method and a MEMS device. The double-sided deep silicon etching method includes: providing an SOI substrate, on which a top silicon layer, a buried oxide layer, and a bottom silicon layer are sequentially formed; performing a first deep silicon etching on the top silicon layer to form multiple blind vias stopping at the buried oxide layer; after completing the first deep silicon etching, depositing a protective layer on the top silicon layer, the protective layer being deposited on the surface of the top silicon layer and at the corners of the top silicon layer at the openings of the blind vias; after completing the protective layer deposition, attaching an electrostatic film to the top silicon layer, flipping the SOI substrate, and performing a second deep silicon etching on the bottom silicon layer to form vias communicating with the blind vias; after completing the second deep silicon etching, removing the protective layer of the top silicon layer. The double-sided deep silicon etching method provided by this invention can effectively improve the problem of damage to the front morphology of the silicon substrate during double-sided deep silicon etching.

To provide an etching solution composition for silicon that yields an etching rate corresponding to the silicon dopant type. [Solution] The etching solution composition provides an etching rate for silicon that corresponds to the silicon dopant type. The etching solution composition comprises a water-soluble etching solution, one or more water-miscible organic solvents, and one or more surfactants.

The application discloses a high-etching-rate and high-smoothness silicon etching solution for wafer back thinning, which comprises HNO3, HF, H2SO4, H3PO4 and the rest water. The etching solution is compounded by HNO3, HF, H2SO4 and H3PO4 in a specific ratio, and can realize high etching rate and low roughness. The high etching rate can significantly improve the process efficiency of the thinning step, meet the process time of the etching machine, and meet the requirements of large-scale commercial production on efficiency and cost. The silicon etching solution can be used for wafer back thinning, and can realize the process requirements of fast etching (shortening process time) and smooth surface (low roughness).

The application relates to the technical field of semiconductor manufacturing, in particular to a silicon etching forming method for embedded packaging grooves; the silicon etching forming method for embedded packaging grooves takes a patterned silicon wafer as a base, takes tetramethylammonium hydroxide as an etching medium, takes a pH-responsive triblock copolymer as a morphology programming molecule, selectively anchors the silicon surface at the edge of a photoresist opening through covalent bonding, controls the molecular conformation by using the etching liquid, realizes in-situ continuous adjustment of the groove sidewall angle, realizes molecular recovery and residual removal through pH switching and RCA cleaning, and completes programmable etching forming of the embedded packaging grooves; the application realizes in-situ continuous adjustment of the groove sidewall angle of 60-90 degrees through covalent anchoring and pH control of the molecular conformation, combines a full-chain closed-loop process, solves the problems of fixed etching sidewall angle, high chemical consumption and difficult control of organic residues, and provides a high-precision and programmable solution for advanced packaging embedded groove etching.

An etching gas and an etching method capable of selectively etching an etching object containing silicon as compared with a non-etching object. The etching gas contains fluorobutene represented by a general formula C4HxFy, in which x is 1 or more and 7 or less, y is 1 or more and 7 or less, and x+y is 8. The etching gas contains or does not contain at least one of copper, zinc, manganese, cobalt, and silicon as metal impurities, and the sum of the concentrations of copper, zinc, manganese, cobalt, and silicon when contained is 5000 ppb by mass or less. The etching method includes an etching step of bringing the etching gas into contact with a member to be etched (12) having an etching object and a non-etching object, and selectively etching the etching object as compared with the non-etching object. The etching object contains silicon.

An etchant composition offers an etch rate on silicon which is sensitive to a dopant type of the silicon. The etchant composition comprises a water-soluble etchant, one or more water-miscible organic solvents, and one or more surfactants.

The application provides a piezoelectric MEMS hydrophone based on a bionic cochlea structure and a preparation method thereof. The preparation method comprises the following steps: forming a blocking layer, a lower electrode layer, a piezoelectric layer and an upper electrode layer on a substrate, and forming a hard mask on the back of the substrate; performing photoetching on the upper electrode layer and then performing reactive ion beam etching to obtain a bionic cochlea structure pattern; performing photoetching and patterning on the piezoelectric layer to obtain a bionic cochlea structure pattern, and then etching to expose the lower electrode layer; forming a positive electrode and a negative electrode on the upper electrode layer; forming an etched hard mask; performing deep silicon etching steps on the back after photoetching and patterning to obtain a back bionic cochlea spiral cavity structure and in-situ arrayed cilia; etching and releasing the device; bonding the piezoelectric vector hydrophone with a PCB board, and wire-bonding the positive electrode and the negative electrode with the PCB board. The hydrophone has the characteristics of miniaturization, realizes wide-frequency underwater sound detection by using a bionic cochlea spiral diaphragm structure, and improves detection sensitivity by using in-situ integrated bionic cochlea cilia.

The application discloses a deep silicon etching air inlet mechanism, which comprises a center air distribution disc and a secondary air inlet disc sleeved together, a center air inlet disc is arranged on the center air distribution disc, first air inlet holes and second air inlet holes are arranged on the center air inlet disc, a first communication hole is arranged on the center air distribution disc, the first air inlet holes are communicated with the first communication hole, and the first communication hole is used for vertically spraying air to a wafer, secondary air inlet holes are arranged on the secondary air inlet disc, the secondary air inlet holes are communicated with the second air inlet holes through second communication holes, the second communication holes are arranged on the center air distribution disc, and the secondary air inlet holes are used for spraying air to the side of the secondary air inlet disc. The deep silicon etching air inlet mechanism improves the etching rate of the wafer and is better in etching uniformity.

This invention discloses an acidic silicon etching solution for effectively controlling etching brightness in the field of semiconductor material processing technology. The etching solution is composed of ammonium bifluoride, nitric acid, sulfuric acid, silver nitrate, surfactant, boron compound additives, and ultrapure water. The boron compound additives exhibit good solubility in the acidic etching solution, effectively regulating the attack of fluoride ions on the silicon surface oxide layer, thereby achieving control over the etching process and the regulation of the surface brightness after etching. The etching solution described in this invention can be used for acidic etching of both monocrystalline and polycrystalline silicon. By adjusting the composition and content of the boron compound additives, silicon etching effects with different brightness levels at the same time and similar brightness levels at different times can be achieved, meeting the etching index requirements for silicon surface state in different application scenarios.

The utility model discloses an integrated circuit production is with corrosion device, including the reaction kettle for producing integrated circuit with high performance titanium silicon etching liquid, the reaction kettle top is provided with drive motor, drive motor drive connection has the screw rod, the screw rod is inserted to the inside of reaction kettle and is hinged to the bottom of reaction kettle, the screw rod screw thread connection has the promotion mixing material spare, the promotion mixing material spare sets up a plurality of liquid flow holes for liquid to pass, still sets up a plurality of material distributing blocks for dispersing liquid, drive motor drives the rotation of screw rod to drive the promotion mixing material spare elevating, thereby the promotion mixing material spare can along with the screw rod elevating to stir and tumble the primary solution and diluent of corrosion.

A method to reduce an etch rate of n-type silicon relative to an etch rate of a collateral material, prior to an oxidative, wet-etch process, comprises exposing a surface including n-type silicon and the collateral material to an aqueous rinse of a pre-determined temperature for a pre-determined period of time.

A method for fabricating a capped wafer includes the following steps: S1, providing a silicon substrate completed by photolithography, wherein the surface of the silicon substrate has multiple annular grooves formed by patterned photoresist, each annular groove opening on the side facing the chip wafer and exposing the silicon substrate at its bottom; S2, performing deep silicon etching in the chamber of a deep silicon etching machine, so that the exposed silicon substrate at the bottom of each annular groove is etched to remove a portion of the surface and expose a clean silicon substrate; S3, depositing solder in each annular groove; S4, removing the photoresist on the silicon substrate, so that the solder deposited in each annular groove forms annular solder rings. Through the deep silicon etching in step S2, the solder deposited in each annular groove is tightly bonded to the clean silicon substrate, enhancing the adhesion between the annular solder and the silicon substrate, thereby improving the sealing performance of the solder rings formed by bonding with the bonding material of the chip wafer, and thus reducing the leakage rate of the MEMS devices fabricated from the capped wafer and the chip wafer.

The application discloses a high-thermal-stability shape memory bionic adhesion structure and a preparation method, and belongs to the technical field of bionic adhesion structures. The structure uses m-xylylenediamine (MXDA) with a benzene ring as a curing agent of an epoxy resin monomer, selects bisphenol A diglycidyl ether (DGEBA) with a purity of greater than or equal to 85% as an epoxy monomer, and selects n-octylamine (OA) as an active agent to promote the reaction between MXDA and DGEBA. A microstructure template is prepared by a deep silicon etching method, and a cylindrical microstructure is prepared on the surface of the epoxy resin, so that the structure has the characteristics of high adhesion, relatively low pre-pressure, high adhesion-pressure ratio and high switching ratio. The adhesion performance of a traditional epoxy-based shape memory bionic adhesion structure is improved, and the transition temperature of the bionic adhesion structure is significantly improved, so that the application scenarios of the shape memory bionic adhesion structure are expanded.

This invention relates to the field of micro-nano optics, and particularly to a method for fabricating a vortex optical lens based on the ARDE effect of deep silicon etching, and the vortex optical lens itself. The fabrication method includes: designing a mask pattern with a gradient distribution of aperture size; forming a patterned mask on a substrate using maskless photolithography; performing deep silicon etching using the mask as a barrier layer, utilizing the ARDE effect to increase the etching rate with increasing aperture size, and directly forming a spiral phase structure on the silicon substrate through single-step etching. This invention also discloses the vortex optical lens and lens array fabricated by this method. This invention utilizes the ARDE effect to achieve single-step three-dimensional forming, resulting in small step height error, high contour accuracy, and excellent sidewall perpendicularity; it has a wide adjustable range of topological charge, high optical efficiency, and a high array fill factor; the process is compatible with CMOS processes, supports wafer-level mass production, and is low-cost and has a short cycle time, making it widely applicable in fields such as optical communication, quantum information, and super-resolution imaging.

Embodiments of the present disclosure disclose a novel wafer-level thermal micro-channel-based on-system bonding process method. A specific embodiment of the method comprises: performing a front-side process of a wafer-level silicon interposer to obtain an interposer front side, wherein the front-side process comprises: deep silicon etching, through-silicon via formation, and front-side multilayer wiring; performing a die bonding process on the interposer front side to obtain a die-bonded interposer, wherein the die bonding process comprises: die-to-wafer mounting, underfilling, plastic encapsulation, and thinning; integrating a wafer-level thermal micro-channel to the front side of the die-bonded interposer to obtain a wafer-level system substrate integrated with a thermal micro-channel; and assembling the wafer-level system substrate with a metal thermal cold plate to obtain a wafer-level substrate with a thermal structure. The embodiment not only reduces the process complexity and potential material consumption, but also shortens the production cycle, while ensuring or even improving product performance, and effectively controlling the manufacturing cost.

This invention relates to a silicon etchant composition and a method for forming patterns using the silicon etchant composition. The silicon etchant composition comprises an amino compound, a pyrazine compound, a basic compound including at least one of an organic hydroxide and an inorganic hydroxide, and a solvent. In the method of forming the pattern, a silicon-containing layer is formed on a substrate. A silicon protective layer is formed on a portion of the silicon-containing layer. The silicon-containing layer comprises silicon and germanium. The silicon-containing layer is etched using the silicon etchant composition.

This invention provides a method for reducing the etching rate of n-type silicon relative to the etching rate of coexisting materials before an oxidative wet etching process. [Solution] A method for reducing the etching rate of n-type silicon relative to the etching rate of a coexisting material which is a different material from n-type silicon, before an oxidative wet etching process, includes exposing a surface containing n-type silicon and the coexisting material to an aqueous rinse solution at a predetermined temperature for a predetermined time.

To provide a silicon etching solution composition that offers improved etching selectivity, and a pattern formation method using the silicon etching solution composition. [Solution] The silicon etching solution composition according to the embodiment of the present disclosure comprises an amine compound, a pyrazine compound, an alkaline compound, and a solvent. According to the pattern forming method according to the embodiment of the present disclosure, a silicon-containing film is formed on a substrate. A silicon protective film containing silicon and germanium is formed on a portion of the silicon-containing film. The silicon-containing film is etched with the silicon etching solution composition.

This application relates to silicon nitride etching compositions and methods. The invention provides compositions suitable for use in the selective removal of silicon nitride material from a microelectronic device having thereon silicon nitride material, polysilicon, silicon oxide material, and / or silicide material relative to the polysilicon, the silicon oxide material, and / or the silicide material. The compositions of the invention are particularly suitable for use in etching 3D NAND structures.

A silicon etchant composition includes an amine-based compound, a pyrazine compound, an alkaline compound including at least one of an organic hydroxide and an inorganic hydroxide, and a solvent. In a method of forming a pattern, a silicon-containing layer is formed on a substrate. A silicon protective layer is formed on a portion of the silicon-containing layer. The silicon-containing layer includes silicon and germanium. The silicon-containing is etched using the silicon etchant composition.