86 results about "Silicon etching" patented technology

The invention discloses a superconducting quantum chip, a substrate and a processing method thereof, and belongs to the technical field of deep silicon etching. The substrate processing method comprises the following steps: providing a substrate with a first photoresist layer on the surface; a first groove for exposing a part of the substrate is formed in the first photoresist layer; forming a protective layer on the inner wall of the first groove; the protective layer surrounds to form a second groove; and etching the substrate through the second groove in the thickness direction of the substrate. Through the mode, the first photoresist layer is not influenced when the substrate is etched, and the form of the first groove formed by the first photoresist layer is protected, so that the problems of expansion, breakage and the like of the first groove are avoided, and the condition that the etching of the substrate cannot meet the expected parameter requirement is avoided.

The application provides a deep silicon etching method and a semiconductor process equipment, and relates to the technical field of semiconductors. The deep silicon etching method comprises a first cycle step and a second cycle step. The first cycle step and the second cycle step both comprise an etching step for etching a silicon substrate to form a groove, a removal step for removing by-products, and a deposition step for forming a protective layer on the sidewall of the groove. The protective gas used in the deposition step of the second cycle step comprises an oxygen-containing gas, and the lower electrode power of the deposition step of the second cycle step is greater than that of the deposition step of the first cycle step. The deep silicon etching method can balance the etching rate of different regions of the isolation groove, optimize the depth micro-loading effect, and improve the depth consistency of the isolation groove. Meanwhile, the deposition step does not consume the mask layer, thereby reducing the consumption of the mask layer, ensuring the effective height of the mask layer, improving the morphology precision of the formed isolation groove and AA, and improving the electrical properties and yield of the product.

The invention discloses a non-polishing low-loss coupling optical fiber array adaptive to a deep silicon etching photon chip, a deep silicon etching photon chip coupling assembly and a method, and belongs to the technical field of silicon photon integration. The device comprises an optical fiber array main body, a V-shaped groove substrate and a special-shaped cover plate, the special-shaped cover plate is attached to the upper surface of the V-shaped groove substrate, an avoiding groove is formed in the position, corresponding to a deep silicon etching area of the end face of the chip, of the special-shaped cover plate, and the depth of the avoiding groove is not smaller than the total height of a residual step on the end face of the chip and a deep groove protruding structure so as to eliminate mechanical interference. The tail end of the optical fiber is positioned in the V-shaped groove, and the light-emitting end face is parallel and tightly butted with the end face of the chip. The customized avoiding groove is integrated in the cover plate, direct, lossless and low-loss coupling of the optical fiber array and the deep silicon etching silicon optical chip with the composite three-dimensional morphology end face can be achieved without extending the optical fiber, removing a bottom cover or polishing the end face of the chip, the integrity of the end face of the chip is effectively protected, and the coupling precision and the device yield are improved.

The invention provides compositions useful in the etching of polysilicon in the presence of silicon oxide and silicon nitride. The compositions comprise choline hydroxide, an oxidizing agent such as periodic acid, and optionally a surfactant, and are useful in the etching of polysilicon in general, and in particular in both the operation of polysilicon trim as well as polysilicon exhume. The utilization of an added oxidizing agent was found to reduce selectivity of silicon etching based on the silicon crystal orientation, which was found to reduce roughness and the presence of residual silicon residues, such as silicon (111) residues after the etching step.

The application discloses a piezoelectric MEMS device preparation process and a device structure, and relates to the technical field of piezoelectric MEMS device preparation. The preparation process comprises the following steps: forming a groove near an edge region on a front surface of a substrate, depositing a sacrifice layer on the front surface of the substrate and patterning the sacrifice layer, so that the sacrifice layer is separated into a center region and an edge support region, forming a piezoelectric-buffer stack on the sacrifice layer and patterning the piezoelectric-buffer stack, and opening a release hole, the release hole being communicated with the center region of the sacrifice layer, introducing etching medium into the release hole to remove the center region of the sacrifice layer, and then etching a back cavity on the back surface of the substrate. The application limits the size of a diaphragm region through the groove, etches the back cavity of the substrate after the sacrifice layer is released, and compared with a traditional method of defining the diaphragm by etching the back cavity, the application completely avoids the size error of the diaphragm caused by the angle deviation of deep silicon etching, accurately locks the profile of the diaphragm, and greatly improves the size consistency and performance stability of devices in the same batch.

The application provides a silicon-based three-dimensional capacitor and a manufacturing method thereof. The manufacturing method comprises the following steps: preparing a dielectric mask layer on the surface of a silicon substrate, etching a plurality of spaced-apart etching micropores on the dielectric mask layer until the silicon substrate is exposed, etching the plurality of spaced-apart etching micropores by using a deep silicon etching process to form a plurality of spaced-apart first deep holes, removing the remaining dielectric mask layer, preparing a first polysilicon layer on the silicon substrate with the plurality of spaced-apart first deep holes, etching the first polysilicon layer in the first deep holes by using a deep silicon etching process to form second deep holes in the first polysilicon layer in the first deep holes, and the bottom surface and the side surface of the second deep holes are provided with the first polysilicon layer, and growing an insulating dielectric layer, a second polysilicon layer and an electrode layer on the first polysilicon layer on the surface of the first silicon substrate and in all the spaced-apart second deep holes in sequence. The silicon-based three-dimensional capacitor prepared by the application can improve the density of the capacitor.

This application provides a continuous titration method for the sulfuric acid and ammonium nitrate content of silicon etching solution. The continuous titration method includes the following steps: weigh m grams of silicon etching solution sample into a sample bottle, add phenolphthalein indicator, titrate with a first sodium hydroxide standard solution of concentration C1 until a pink color is achieved, and record the volume consumed V1. Calculate the sulfuric acid content. Add neutral formaldehyde solution to the same solution and let it stand for a first preset time to generate a free acid solution. Continue titrating the free acid solution with a second sodium hydroxide standard solution of concentration C2 until the solution turns pink. Gently heat the solution to a preset temperature and maintain this temperature for a second preset time. If the pink color persists, the titration endpoint is determined, and the volume consumed V2 is recorded. Calculate the ammonium nitrate content. This method achieves continuous titration of two components with a single sample, eliminates mutual interference between components, optimizes the endpoint determination method, and thus achieves a simple operation, high accuracy, low sample consumption, and high detection efficiency.

The invention discloses a manufacturing method of a U-shaped groove, which is characterized in that a photoresist reserved on a field oxide in an X-direction photoetching process of the U-shaped groove can protect a hard mask on the field oxide of a Y-direction opening of a non-U-shaped groove region, the loss of the hard mask on the field oxide of the Y-direction opening of the non-U-shaped groove region cannot be caused, and a U-shaped groove process window is enlarged; in the process of performing X-direction silicon etching to form a U-shaped groove, silicon at an X-direction opening at a non-overlapping position of an X-direction opening pattern and a Y-direction opening pattern is protected by a mask first silicon oxide layer and a mask second silicon nitride layer, when the mask at the position is removed, the mask second silicon nitride layer is removed firstly, then the first silicon oxide layer is removed, and the first silicon oxide layer is removed after the mask second silicon nitride layer is removed. The SIN hard mask on the field oxide is not damaged, and the morphology standard of the U-shaped groove can be ensured.

The present invention provides an etching solution composition for silicon that yields an etching rate corresponding to the silicon dopant type, and a method for etching a surface having a first silicon region that is n-type and a second silicon region that differs from the first silicon region in terms of dopant type. [Solution] The etching solution composition provides an etching rate for silicon that corresponds to the silicon dopant type. The etching solution composition contains a base and an additive other than the base. The additive has 1 to 6 carbon atoms per molecule.

The invention discloses an MEMS (Micro Electro Mechanical System) thermal acceleration sensor for realizing wafer-level packaging by utilizing a silicon structure in glass and a preparation method. The sensor adopts a three-layer stacked structure, and comprises a silicon sealing cover in glass, an acceleration sensor body and a sealing laminated wafer. Wherein a silicon conductive through column which is electrically insulated from the glass medium is arranged in the glass-in-silicon sealing cover, so that electric signal transmission in the vertical direction is realized; the acceleration sensor body comprises a heating and temperature measuring module manufactured on a supporting layer; the sealing bonding wafer and the sealing cover jointly form a sealed cavity to package the working fluid. The preparation method comprises the following steps: preparing a silicon-in-glass sealing cover through two times of deep silicon etching, anodic bonding and a glass backflow process, manufacturing a sensor functional structure on a silicon substrate and forming a back cavity, and finally completing wafer-level integrated packaging through a surface mounting process. The wafer-level batch preparation and packaging complete solution of the thermal acceleration sensor is realized, and the problems of high packaging cost and low efficiency of a non-standard process are solved.

The invention relates to the field of ultrasonic transducer manufacturing, in particular to a micromechanical ultrasonic transducer and a manufacturing process thereof, and the manufacturing process comprises the following steps: S1, etching an etching boundary of a preset cavity at a monocrystalline silicon substrate; s2, performing oxidation treatment on the preset monocrystalline silicon substrate with the etched boundary to form an oxide layer; s3, growing monocrystalline silicon on the oxide layer to serve as a mechanical support layer; s4, carrying out planarization treatment on the surface of the mechanical supporting layer; s5, sequentially depositing a lower electrode metal layer, a piezoelectric layer, an upper electrode metal layer and a passivation layer on the planarized mechanical support layer to form a core stack structure; and S6, taking the etching boundary and the oxide layer as a two-dimensional etching stop layer, and performing deep silicon etching on the back surface to form a cavity. According to the micromechanical ultrasonic transducer and the manufacturing process thereof, the etching precision is improved, and the production cost is saved.

This invention discloses a pneumatic micro-transport device, including an air compressor connected to a pneumatic solenoid valve via an air pump pipe. The pneumatic solenoid valve is connected to a microcontroller via a relay, and the microcontroller is connected to a LabVIEW host computer via a USB interface. The pneumatic solenoid valve is also connected to a micro-transport array via the air pump pipe, and a transport plate is placed above the micro-transport array. This device is designed based on pneumatic principles. Compared to traditional contact-type transport devices, its transport method avoids failures caused by friction-induced wear. Furthermore, thanks to its non-contact transport characteristics, its application range is further expanded. It employs deep silicon etching micromachining technology, with the silicon plate structure serving as the air chamber channel and nozzle of the micro-transport device, significantly reducing the structural size of the micro-transport device, improving space utilization, and solving problems such as low integration in traditional micro-transport devices.

The present application relates to a kind of wafer cutting protection fluid for laser-assisted plasma etching process and its preparation method and application, according to weight parts, the wafer cutting protection fluid includes: water-soluble furan-based polyamide resin 70~85 parts;Solvent 15~25 parts;Plasticizer 1~5 parts;Ultraviolet light absorber 0.1~1 parts;Leveling agent 0.1~1 parts.The wafer cutting protection fluid provided by the present application can form a protective film with excellent mechanical properties, wear resistance and heat resistance, and easy to clean, widely used in thin wafer processing, deep silicon etching and TSV through hole and other processing processes.

This invention provides a double-sided deep silicon etching method and a MEMS device. The double-sided deep silicon etching method includes: providing an SOI substrate, on which a top silicon layer, a buried oxide layer, and a bottom silicon layer are sequentially formed; performing a first deep silicon etching on the top silicon layer to form multiple blind vias stopping at the buried oxide layer; after completing the first deep silicon etching, depositing a protective layer on the top silicon layer, the protective layer being deposited on the surface of the top silicon layer and at the corners of the top silicon layer at the openings of the blind vias; after completing the protective layer deposition, attaching an electrostatic film to the top silicon layer, flipping the SOI substrate, and performing a second deep silicon etching on the bottom silicon layer to form vias communicating with the blind vias; after completing the second deep silicon etching, removing the protective layer of the top silicon layer. The double-sided deep silicon etching method provided by this invention can effectively improve the problem of damage to the front morphology of the silicon substrate during double-sided deep silicon etching.

To provide an etching solution composition for silicon that yields an etching rate corresponding to the silicon dopant type. [Solution] The etching solution composition provides an etching rate for silicon that corresponds to the silicon dopant type. The etching solution composition comprises a water-soluble etching solution, one or more water-miscible organic solvents, and one or more surfactants.

A method for forming back etching of source and drain silicon in a transistor comprises the steps that a substrate is provided, the substrate comprises a device area, and a channel protruding part protrudes from the top of the substrate in the device area; in the device region, forming a gate structure crossing the channel lug boss, and covering a part of the top and a part of the side wall of the channel lug boss by the gate structure; forming a side wall material layer on the surface of the channel lug boss and the surface of the gate structure; removing the side wall material layer covering the surface of the channel lug boss and the top of the gate structure; and forming a source-drain doping layer in the channel lug bosses at the two sides of the gate structure. According to the method, the side wall material layer covering the surface of the channel lug boss and the top of the gate structure is removed completely, so that the cleanliness of the surface of the channel lug boss can be improved, the morphology of a source-drain groove formed in the channel lug boss subsequently is further improved, the stress action of the source-drain region from top to bottom in the channel structure is more uniform, and the reliability of the device is improved. Therefore, the performance of the semiconductor structure is improved.

The present invention provides a method for forming self-transformed support plates in shallow trench isolation for advanced semiconductor devices, in which after a photolithography process to define active areas on a silicon substrate, an additional photomask is implemented to add a support plate patterning layer in areas where silicon will be etched during a STI etching step to form STI trenches. Tiny silicon support plates inside the STI trenches are formed after the silicon etching. These silicon support plates may provide mechanical support to hold neighboring patterned strips where the active areas are defined or neighboring active areas islands, and preventing them from bending, deformed or shifting. An alignment of photomask pattern at following photolithography process is eased.

The application discloses a high-etching-rate and high-smoothness silicon etching solution for wafer back thinning, which comprises HNO3, HF, H2SO4, H3PO4 and the rest water. The etching solution is compounded by HNO3, HF, H2SO4 and H3PO4 in a specific ratio, and can realize high etching rate and low roughness. The high etching rate can significantly improve the process efficiency of the thinning step, meet the process time of the etching machine, and meet the requirements of large-scale commercial production on efficiency and cost. The silicon etching solution can be used for wafer back thinning, and can realize the process requirements of fast etching (shortening process time) and smooth surface (low roughness).

A silicon etched sharp bearing body may comprise a substrate. The sharp bearing body may further comprise a microneedle extending proud of a first side of the substrate. The microneedle may have a sloped face and sidewalls defining a tip region and a trailing region. The sidewalls at the tip region may be curved and devoid of straight spans. The sidewalls at the trailing region may be curved and devoid of straight spans. The sharp bearing body may further comprise a lumen extending through the sharp bearing body from a second side of the substrate opposite the first side and to the sloped face of the microneedle. The sharp bearing body may further comprise a trench recessed around the sidewalls of the microneedle. The wall of the trench most distal the sidewalls of the microneedle may be curved and devoid of straight spans.

A preparation and coupling optimization method of bar SOI waveguide using end face coupling belongs to the field of micro-nano fine structure processing and optical precision measurement. Through two-step photoetching and two-step etching, on one hand, the base section plane highly coinciding with the waveguide end face can be etched, and on the other hand, the etching widening of the Si base etching channel cannot cause the waveguide below to be hollowed out. By using the DC magnetron sputtering Cr mask, the waveguide material can be prevented from being etched and damaged in the deep silicon etching process. Through the ion beam etching process, the waveguide end face and the base etching sidewall are completely coincided, so that part of the light spot is avoided from being scattered by the Si base in the optical fiber coupling process, and the coupling efficiency of the waveguide is improved. By combining the FDTD simulation results, the ICP-PECVD is used to deposit the low internal stress SiO2+Si3N4 antireflection film with a suitable thickness on the waveguide end face, the light spot is avoided from being reflected on the waveguide end face, and the light spot coupling efficiency is maximized.

The invention discloses a novel micro sample injector for a gas chromatograph and a manufacturing method and a using method thereof.The novel micro sample injector comprises a first glass layer, an elastic film layer, a silicon etching layer and a second glass layer which are sequentially attached and connected from top to bottom, and the elastic film layer is connected to the surface, provided with an annular gas chamber, of the silicon etching layer; the elastic film layer is pushed by external air pressure to bend and deform towards the direction close to the silicon etching layer or reset towards the direction far away from the silicon etching layer so as to control the connection and disconnection of the two first air grooves in the same annular air chamber; a first micro valve is formed at the sample gas inlet; a second micro valve is formed at the sample gas outlet; a third micro valve is formed at the helium gas inlet; and a fourth micro valve is formed at the chromatographic column inlet. The micro sample injector adopts a four-layer structure of a glass layer, an elastic film, a silicon etching layer and a glass layer, so that the function of controlling the on-off of a gas path is realized; the four micro valves are designed to control gas inlet and outlet, the structure is simple, the problem of valve position switching asynchronism caused by gas path time sequence coordination is solved, and the sampling accuracy is improved.

The application relates to the technical field of semiconductor manufacturing, in particular to a silicon etching forming method for embedded packaging grooves; the silicon etching forming method for embedded packaging grooves takes a patterned silicon wafer as a base, takes tetramethylammonium hydroxide as an etching medium, takes a pH-responsive triblock copolymer as a morphology programming molecule, selectively anchors the silicon surface at the edge of a photoresist opening through covalent bonding, controls the molecular conformation by using the etching liquid, realizes in-situ continuous adjustment of the groove sidewall angle, realizes molecular recovery and residual removal through pH switching and RCA cleaning, and completes programmable etching forming of the embedded packaging grooves; the application realizes in-situ continuous adjustment of the groove sidewall angle of 60-90 degrees through covalent anchoring and pH control of the molecular conformation, combines a full-chain closed-loop process, solves the problems of fixed etching sidewall angle, high chemical consumption and difficult control of organic residues, and provides a high-precision and programmable solution for advanced packaging embedded groove etching.

An etching gas and an etching method capable of selectively etching an etching object containing silicon as compared with a non-etching object. The etching gas contains fluorobutene represented by a general formula C4HxFy, in which x is 1 or more and 7 or less, y is 1 or more and 7 or less, and x+y is 8. The etching gas contains or does not contain at least one of copper, zinc, manganese, cobalt, and silicon as metal impurities, and the sum of the concentrations of copper, zinc, manganese, cobalt, and silicon when contained is 5000 ppb by mass or less. The etching method includes an etching step of bringing the etching gas into contact with a member to be etched (12) having an etching object and a non-etching object, and selectively etching the etching object as compared with the non-etching object. The etching object contains silicon.

An etchant composition offers an etch rate on silicon which is sensitive to a dopant type of the silicon. The etchant composition comprises a water-soluble etchant, one or more water-miscible organic solvents, and one or more surfactants.

The invention relates to a low-resistance silicon etching solution. The etching solution is composed of sulfuric acid, nitric acid, fluoride, a pro-oxidant, a corrosion inhibitor, a viscosity modifier and ultrapure water. Sulfuric acid, nitric acid and fluoride are prepared according to a proper ratio, etching can be carried out at a stable rate, the oxidant aid can improve the oxidability of liquid medicine and reduce the influence of non-uniform doping on etching uniformity, and bubbles generated in the reaction process can be reduced through the combined action of the corrosion inhibitor and the viscosity modifier, so that the etching uniformity is improved. And incomplete or non-uniform etching caused by the fact that the etching liquid cannot be completely contacted with the surface of the low-resistance silicon is avoided. The low-resistance silicon etching liquid can quickly and stably etch a low-resistance silicon product, the surface roughness of the product is almost unchanged before and after etching, and the surface is fine and smooth and has no color difference or bubble spots.

The application provides a piezoelectric MEMS hydrophone based on a bionic cochlea structure and a preparation method thereof. The preparation method comprises the following steps: forming a blocking layer, a lower electrode layer, a piezoelectric layer and an upper electrode layer on a substrate, and forming a hard mask on the back of the substrate; performing photoetching on the upper electrode layer and then performing reactive ion beam etching to obtain a bionic cochlea structure pattern; performing photoetching and patterning on the piezoelectric layer to obtain a bionic cochlea structure pattern, and then etching to expose the lower electrode layer; forming a positive electrode and a negative electrode on the upper electrode layer; forming an etched hard mask; performing deep silicon etching steps on the back after photoetching and patterning to obtain a back bionic cochlea spiral cavity structure and in-situ arrayed cilia; etching and releasing the device; bonding the piezoelectric vector hydrophone with a PCB board, and wire-bonding the positive electrode and the negative electrode with the PCB board. The hydrophone has the characteristics of miniaturization, realizes wide-frequency underwater sound detection by using a bionic cochlea spiral diaphragm structure, and improves detection sensitivity by using in-situ integrated bionic cochlea cilia.

The invention discloses an application of a germanium-silicon etching solution. The invention specifically discloses an application of a germanium-silicon etching solution in etching a sacrificial layer in a GAA MOSFET (Good Acrylic Acid Metal-Oxide-Semiconductor Field Effect Transistor) structure. The germanium-silicon etching liquid is prepared from the following components in percentage by mass: 0.1%-5% of fluoride, 5%-70% of an oxidizing agent, 0.1%-2% of a wetting agent, 0.1%-2% of a complexing agent and a solvent, the sum of the mass fractions of all the components is 100%, and the mass fractions are the percentage of the mass of all the components in the total mass of the germanium-silicon etching liquid. When the germanium-silicon etching liquid is used for etching a sacrificial layer in a GAA MOSFET structure, high-selectivity etching of germanium-silicon / silicon can be achieved, and the etching effect is good and uniform.

A silicon etched sharp bearing body may comprise a substrate. The sharp bearing body may further comprise a microneedle extending proud of a first side of the substrate. The microneedle may have a sloped face and sidewalls defining a tip region and a trailing region. The sidewalls at the tip region may be curved and devoid of straight spans. The sidewalls at the trailing region may be curved and devoid of straight spans. The sharp bearing body may further comprise a lumen extending through the sharp bearing body from a second side of the substrate opposite the first side and to the sloped face of the microneedle. The sharp bearing body may further comprise a trench recessed around the sidewalls of the microneedle. The wall of the trench most distal the sidewalls of the microneedle may be curved and devoid of straight spans

Provided are an etching method and an etching device for forming an excellent etching shape.　An etching method comprises: a step for preparing a substrate having a silicon-containing layer to be etched, and a mask layer that is formed on the layer to be etched and has a pattern of openings; and a step for generating plasma of a processing gas to etch the layer to be etched through the openings of the mask layer, the processing gas being a mixed gas of HBr, SF6, and O2.

The application discloses a deep silicon etching air inlet mechanism, which comprises a center air distribution disc and a secondary air inlet disc sleeved together, a center air inlet disc is arranged on the center air distribution disc, first air inlet holes and second air inlet holes are arranged on the center air inlet disc, a first communication hole is arranged on the center air distribution disc, the first air inlet holes are communicated with the first communication hole, and the first communication hole is used for vertically spraying air to a wafer, secondary air inlet holes are arranged on the secondary air inlet disc, the secondary air inlet holes are communicated with the second air inlet holes through second communication holes, the second communication holes are arranged on the center air distribution disc, and the secondary air inlet holes are used for spraying air to the side of the secondary air inlet disc. The deep silicon etching air inlet mechanism improves the etching rate of the wafer and is better in etching uniformity.