277 results about "Silicon etching" patented technology

The invention discloses a semiconductor structure manufacturing method and a semiconductor structure, and the manufacturing method comprises the steps: carrying out the periodic cycle etching of a preset number of times on a substrate through employing an etching technology, forming a first intermediate structure on the substrate, and carrying out the first processing of the first intermediate structure, including employing a first gas and a second gas, removing a part of thickness of the passivation layer deposited on the side wall of the first intermediate structure, and reacting with the substrate material which exists on the side wall and is exposed on the surface of the convex part to generate a reaction product layer; and removing the reaction product layer by using a third gas and a fourth gas so as to remove at least part of the lug boss, and repeatedly executing the etching process and the first processing process until a high aspect ratio etching structure is formed on the substrate. According to the method, the etching process and the side wall processing technology are organically combined, the etching rate and the side wall quality are balanced through alternate circulation, and deep silicon etching with the higher aspect ratio and the smaller nanoscale size can be achieved.

The invention discloses a preparation method of a semiconductor structure and the semiconductor structure, and the preparation method comprises the steps: carrying out the etching of a substrate through employing an etching technology, so as to form a high-aspect-ratio etching structure on the substrate; after a periodic cycle step of a preset number of times of etching process is completed every time, a treatment process different from the etching process is used, and partial thickness of a passivation layer deposited on the side wall of an intermediate structure formed before the high aspect ratio etching structure is formed is removed. And removing at least part of the protruding part which exists on the side wall and is exposed from the surface of the residual passivation layer. According to the method, the etching process and the side wall processing technology are organically combined, the etching rate and the side wall quality are balanced through alternate circulation, and deep silicon etching with the higher aspect ratio and the smaller nanoscale size can be achieved.

The invention discloses an MEMS thermal flow sensor based on a glass film structure and a preparation method of the MEMS thermal flow sensor. The sensor comprises a glass inner silicon substrate, a back cavity, a silicon through column, a heating resistor, a temperature measurement resistor, an environment temperature measurement resistor, a chromium adhesion layer, a PAD port and a silicon nitride protection layer. Wherein the heating resistor is located in the center, and the temperature measuring resistors are symmetrically distributed on two sides of the heating resistor; the back cavity is located on the back of the glass inner silicon substrate, and the heating resistor, the temperature measuring resistor and the environment temperature measuring resistor lead a PAD port to the back of the glass inner silicon substrate through a silicon through column. A thermal temperature difference principle is adopted, and upstream and downstream temperature measuring resistors form a Wheatstone bridge. When the flow velocity is not zero, the Wheatstone bridge outputs, and the larger the flow velocity is, the larger the output is. Based on the glass and silicon composite substrate, the suspension film structure is formed through the silicon etching process, transmission of heat to the substrate is greatly reduced, and the heat utilization rate is increased.

The invention discloses a preparation and coupling optimization method of a strip-shaped SOI waveguide adopting end face coupling, and belongs to the field of micro-nano fine structure processing and optical precision measurement. According to the method, through two-step photoetching and two-step etching, on one hand, the substrate section highly coincident with the waveguide end face can be etched on the waveguide end face, and on the other hand, it can be guaranteed that the etching broadening of the Si substrate etching channel cannot cause the hollow-out of the lower portion of the waveguide above SiO2. By using the direct-current magnetron sputtering Cr mask, the waveguide material can be prevented from being etched and damaged in the deep silicon etching process. Through the ion beam etching process, the end face of the waveguide and the etched side wall of the substrate are completely overlapped, so that part of light spots are prevented from being scattered by the Si substrate in the optical fiber coupling process, and the coupling efficiency of the waveguide is further improved. By combining the FDTD simulation result, the low-internal stress SiO2-Si3N4 antireflection film with the proper thickness is deposited on the waveguide end face through ICP-PECVD, light spots are prevented from being reflected on the waveguide end face, and the light spot coupling efficiency reaches the maximum.

The invention relates to a 3 [mu] m SOI process integration method for an on-chip beam forming and wavelength division multiplexing system. The method comprises the steps of silicon waveguide etching, PN ion implantation, germanium-silicon epitaxy, germanium-silicon waveguide etching, metal layer growth and the like. In order to solve the problem that the silicon PN doping annealing temperature is higher than the germanium-silicon PN doping annealing temperature, the germanium-silicon epitaxial etching postposition technological process is developed, and the non-selective epitaxy and reverse etching modes are used, so that the problem that a wafer is uneven after silicon etching doping is solved. The method has extremely high application value in large-scale silicon photon integration application, and can be used for manufacturing complex active photon chips integrated with modulators, detectors and the like.

The invention discloses a manufacturing and temperature compensation method of a Pirani vacuum gauge compatible with a CMOS, and relates to the field of Pirani vacuum gauges, and the manufacturing method comprises the steps: sequentially depositing a first layer of silicon dioxide, a polycrystalline silicon sacrificial layer, a second layer of silicon dioxide, a polycrystalline silicon thermistor part, a third layer of silicon dioxide and an aluminum layer on a silicon substrate; the aluminum layer is used for forming a lead and a bonding pad; silicon dioxide is selectively removed through reactive ion etching, and the polycrystalline silicon sacrificial layer or the silicon substrate needing to be etched is exposed; etching the polycrystalline silicon sacrificial layer by adopting an isotropic etching technology to obtain a T-shaped device structure; or etching the silicon substrate by adopting a deep silicon etching technology and an isotropic etching technology to obtain an L-shaped device structure. According to the invention, two kinds of Pirani vacuum gauges compatible with CMOS can be manufactured; and meanwhile, through the temperature compensation method, the influence on the output performance can be specifically analyzed based on the environment temperature.

The invention discloses a heat dissipation enhanced semiconductor packaging method, which comprises the following steps of: performing deep silicon etching to form a vertical through hole; insulation and metallization are carried out; thinning the wafer; performing hybrid bonding and stacking of multiple layers of chips; a heat dissipation design is adopted to form a vertical heat dissipation path; a three-dimensional thermal through hole network: adding pure copper thermal through holes in a non-functional area; performing microfluid cooling integration; molding and packaging; and thermal performance verification: verifying that the junction temperature can be controlled within 85 DEG C through infrared thermal imaging and finite element simulation. The TSV with the depth-to-width ratio of 10: 1 can be realized by adopting the Bosch process; a three-dimensional integrated TSV array supporting HBM and other high-speed memories is embedded into diamond or graphene heat dissipation columns, a low-heat-resistance vertical heat dissipation path is formed by combining a three-dimensional pure copper heat through hole network, and local hot spots are effectively dispersed; the high-thermal-conductivity epoxy molding compound and the embedded copper block enhance the overall mechanical strength and thermal diffusivity, so that the product can dissipate heat efficiently, and the overall area is not easy to influence.

The invention provides a through hole microneedle and a preparation method thereof, and the method comprises the following steps: providing a silicon wafer, and sequentially forming a silicon nitride layer and a silicon oxide layer on the front surface and the back surface of the silicon wafer; forming a first etching mask on the front surface of the silicon wafer by utilizing photoetching and etching processes, and carrying out first deep silicon etching to form a semi-through deep hole; forming a second etching mask on the back surface of the silicon wafer by utilizing photoetching and etching processes, and carrying out secondary deep silicon etching to form a through deep hole to obtain a pinhole structure; removing the silicon oxide layers on the front surface and the back surface of the silicon wafer; forming a silicon oxide layer on the inner wall of the deep hole by adopting a thermal oxidation process; forming silicon nitride layers on the front surface and the back surface of the silicon wafer and the inner wall of the deep hole; removing all the silicon nitride layers on the front surface of the silicon wafer; etching the silicon wafer by using an anisotropic wet method to form a needle body structure; and removing the residual silicon nitride layer and the residual silicon oxide layer.

The invention relates to a wafer cutting protection liquid for a laser-assisted plasma etching process and a preparation method and application of the wafer cutting protection liquid, and the wafer cutting protection liquid comprises the following components in parts by weight: 70-85 parts of water-soluble furyl polyamide resin; 15-25 parts of a solvent; 1-5 parts of a plasticizer; 0.1-1 part of an ultraviolet light absorber; and 0.1-1 part of a leveling agent. The wafer cutting protection liquid provided by the invention can form a protection film which has excellent mechanical properties, wear resistance and heat resistance and is easy to clean, and is widely applicable to thin wafer processing, deep silicon etching, TSV through hole processing technologies and the like.

The invention discloses a high aspect ratio deep silicon etching structure and a patterning method thereof. The patterning method comprises the following steps: providing a substrate made of silicon; forming a plurality of photoresist patterns on the surface of the substrate, wherein an opening is formed between every two adjacent photoresist patterns; bombarding the interface of the substrate at the inner bottom corner of the opening by using plasma of a first gas at a first ultralow temperature to form a first protective film; depositing a polymer layer on the substrate, the photoresist pattern and the first protective film for protection by using plasma of second gas at a second ultralow temperature; etching the polymer layer and the substrate by using plasma of a third gas at a third ultralow temperature; repeating the steps of depositing the polymer layer and etching until a high aspect ratio deep silicon etching structure is formed on the substrate; and removing the photoresist pattern. According to the invention, the uniform protection of the side wall under the conditions of smaller size and higher aspect ratio can be realized, and the etching rate can be improved.

The invention discloses a semiconductor deep silicon etching method and application thereof. The semiconductor deep silicon etching method comprises the following steps: providing a structure to be etched, wherein the structure comprises a silicon structure and a silicon oxide layer; patterning etching is carried out; growing silicon oxide as a filling layer which comprises a side surface part and a bottom surface part, filling the first inner wall to form a second inner wall, and enabling the second inner wall and the bottom surface to be closer to 90 degrees; performing secondary etching to expose the silicon structure again; and forming a deep silicon etching structure by adopting a deep silicon etching process. According to the method, the opening width and the opening side wall morphology of the hard mask are adjusted by utilizing a transverse growth method, on one hand, the width of the mask opening can be accurately adjusted by controlling the transverse growth condition, and high-precision photoetching equipment is not needed; and on the other hand, the deep silicon etching quality can be remarkably improved by adjusting the shape of the side wall of the opening, and various abnormities of the deep silicon etching groove can be avoided without complex procedures and expensive equipment.

The invention discloses selective etching liquid of carbon-doped silicon nitride / silicon oxide. The selective etching liquid comprises the following raw materials in percentage by mass: 50-80% of a catalyst substance and 1-10% of an oxidizing substance, 2-10% of a fluorine-containing compound, 0.1-1% of a fluorine ion stabilizer and 0.1-1% of a selective additive; and the balance of deionized water. The etching solution can increase the etching rate of carbon-doped silicon nitride to a certain level and maintain the selection ratio of 5: 1 to silicon oxide.

Provided is an etching solution composition capable of preventing reduction in the etching rate of a silicon nitride film, achieving high etching selectivity with respect to silicon nitride, and suppressing deposition of silica on the surface of silicon oxide.　This etching solution composition is based on an inorganic acid and is for selectively etching silicon nitride from a semiconductor containing the silicon nitride and silicon oxide, and comprises: (a) a fluorine compound that increases the etching rate of silicon nitride; and (b) a volatilization inhibitor that inhibits volatilization of the fluorine compound.

The invention discloses a silicon deep etching method of a high aspect ratio structure. The silicon deep etching method comprises the following steps of: 1, exposing a required structure plane pattern on a silicon wafer; 2, depositing a metal catalyst with a set thickness above the silicon substrate partially covered with the photoresist; 3, preparing the porous morphology of the metal catalyst on the basis of the metal catalyst prepared in the step 2; and 4, the silicon wafer is immersed in an etching solution prepared by mixing an oxidizing agent and hydrofluoric acid in a set proportion for etching, a silicon hole with a high aspect ratio is obtained, the silicon hole comprises a channel and a hole, and deep silicon etching is achieved. According to the method, the micro-nano scale morphology of the metal catalyst is accurately regulated and controlled, and the corresponding etching solution is reasonably used, so that a smooth, flat and uniform high aspect ratio structure is prepared on a large scale.

The invention discloses a method for manufacturing a micro lens in a groove and a micro lens structure in the groove, the transfer of the micro lens is completed through three times of etching processes, the manufacturing of the micro lens in the groove is realized, the depth of the groove can be accurately controlled, the error range of the depth of the groove is controlled within 2 microns, and the method is suitable for manufacturing the micro lens in an ultra-deep groove with the groove depth larger than or equal to 50 microns. Wherein the three-time etching process comprises one-time steady-state etching and two-time deep silicon etching, the steady-state etching can realize the transfer of the micro lens, the first-time deep silicon etching adopts fast-rate etching to quickly form the outline of the groove structure, and the second-time deep silicon etching adopts slow-rate etching to realize the accurate control of the depth of the groove structure.

The invention discloses a large-area cross-scale super lens rapid preparation method based on a transfer printing process, and relates to the field of micro-nano manufacturing. Comprising the steps of substrate cleaning, primary gluing, primary pre-baking, primary exposure, secondary gluing, secondary pre-baking, transferring, secondary exposure, releasing, developing, deep silicon etching and dry-method photoresist removing. Through the transferable and releasable photoresist near-field contact type photoetching technology, the deep silicon etching technology, the dry photoresist removing technology and the like, rapid and low-cost preparation of the large-area cross-scale super lens is achieved. According to the method, perfect contact exposure can be realized by virtue of the transferable photoresist, and the structural precision of the near-infrared super lens can be easily achieved. The transferable photoresist with excellent mechanical properties is utilized to protect the photoresist with low mechanical properties, the key problem of perfect lossless stripping and release of the large-area double-layer photoresist is solved, and a scheme which is high in efficiency, low in cost, simple and capable of being copied quickly is provided for preparation of the large-area cross-scale super lens.

The invention discloses application of germanium-silicon etching liquid. The etching liquid is applied to selective etching of silicon in a GAA MOSFET structure. The etching liquid comprises the following components in percentage by mass: 1-10% of organic alkali, 0.001-0.1% of a nonionic surfactant, 5-30% of an organic solvent and water, and the sum of the mass fractions of the components is 100%. The etching liquid provided by the invention can selectively etch silicon, has a high etching rate for silicon, has a low etching rate for silicon-germanium alloy, silicon oxide and silicon nitride, and has a high selection ratio for silicon / silicon-germanium alloy.

The invention discloses a multifunctional protection device and a manufacturing process thereof, belonging to the technical field of protection devices. A silicon dioxide layer is grown on a P-type single-crystal silicon wafer, a boron ion implantation window is photoetched on the front side of the P-type single-crystal silicon wafer, a light boron layer is doped on the front side of the P-type single-crystal silicon wafer by ion implantation, and the light boron layer is redistributed by high-temperature diffusion, a light phosphorus implantation window is photoetched on the front and back sides of the P-type single-crystal silicon wafer, a phosphorus layer is ion implanted on the front and back sides of the P-type single-crystal silicon wafer, and the phosphorus layer is redistributed by high-temperature diffusion, a concentrated boron diffusion zone window is photoetched on the front side of the P-type single-crystal silicon wafer, concentrated boron diffusion is performed on the front side, concentrated phosphorus layer diffusion windows are photoetched on the front and back sides of the P-type single-crystal silicon wafer, concentrated phosphorus layer diffusion is performed on both sides, a groove etching window is photoetched on the front side of the P-type single-crystal silicon wafer, silicon etching is performed to form an inner groove mesa structure, and metallization treatment is performed on the front and back sides of the P-type single-crystal silicon wafer to construct a metal layer.

The present application discloses a method for fabricating a semiconductor structure and a semiconductor structure. The method comprises: etching a substrate using an etching process to form a high-aspect-ratio etched structure on the substrate; after each predetermined number of periodic cycles of the etching process are completed, using a treatment process different from the etching process to remove a portion of the thickness of a passivation layer deposited on the sidewalls of an intermediate structure formed before the high-aspect-ratio etched structure is formed, and removing at least a portion of a protrusion on the sidewall that is exposed from the remaining passivation layer surface. The present application organically combines the etching process with sidewall treatment technology, alternating cycles to balance the etching rate and sidewall quality, and can achieve deep silicon etching with higher aspect ratios and smaller nanometer-scale dimensions.

The invention discloses a superconducting quantum chip, a substrate and a processing method thereof, and belongs to the technical field of deep silicon etching. The substrate processing method comprises the following steps: providing a substrate with a first photoresist layer on the surface; a first groove for exposing a part of the substrate is formed in the first photoresist layer; forming a protective layer on the inner wall of the first groove; the protective layer surrounds to form a second groove; and etching the substrate through the second groove in the thickness direction of the substrate. Through the mode, the first photoresist layer is not influenced when the substrate is etched, and the form of the first groove formed by the first photoresist layer is protected, so that the problems of expansion, breakage and the like of the first groove are avoided, and the condition that the etching of the substrate cannot meet the expected parameter requirement is avoided.

The application provides a deep silicon etching method and a semiconductor process equipment, and relates to the technical field of semiconductors. The deep silicon etching method comprises a first cycle step and a second cycle step. The first cycle step and the second cycle step both comprise an etching step for etching a silicon substrate to form a groove, a removal step for removing by-products, and a deposition step for forming a protective layer on the sidewall of the groove. The protective gas used in the deposition step of the second cycle step comprises an oxygen-containing gas, and the lower electrode power of the deposition step of the second cycle step is greater than that of the deposition step of the first cycle step. The deep silicon etching method can balance the etching rate of different regions of the isolation groove, optimize the depth micro-loading effect, and improve the depth consistency of the isolation groove. Meanwhile, the deposition step does not consume the mask layer, thereby reducing the consumption of the mask layer, ensuring the effective height of the mask layer, improving the morphology precision of the formed isolation groove and AA, and improving the electrical properties and yield of the product.

The present invention provides a double silicon-gold bonded MEMS deformable mirror and its fabrication method. The MEMS deformable mirror comprises a silicon wafer substrate, a silicon nitride insulating layer, a lower polysilicon electrode, a first phosphosilicate glass sacrificial layer, an upper interdigitated electrode, a first bonding electrode layer, an SOI wafer structure, a second bonding electrode layer, and a gold-based reflective mirror surface. The fabrication method sequentially involves silicon wafer substrate pretreatment, silicon nitride insulating layer deposition, lower polysilicon electrode formation, first phosphosilicate glass sacrificial layer deposition and thinning, upper interdigitated electrode and related structure etching, first bonding electrode layer formation, SOI wafer pretreatment and solution channel formation, second phosphosilicate glass sacrificial layer filling, second bonding electrode layer formation, gold-to-gold hot-compression bonding, deep silicon etching, structural release and annealing, and gold-based reflective mirror surface fabrication and packaging. This invention can simplify the process flow, improve the correction performance of optical systems, and has broad market application prospects.

The invention discloses a non-polishing low-loss coupling optical fiber array adaptive to a deep silicon etching photon chip, a deep silicon etching photon chip coupling assembly and a method, and belongs to the technical field of silicon photon integration. The device comprises an optical fiber array main body, a V-shaped groove substrate and a special-shaped cover plate, the special-shaped cover plate is attached to the upper surface of the V-shaped groove substrate, an avoiding groove is formed in the position, corresponding to a deep silicon etching area of the end face of the chip, of the special-shaped cover plate, and the depth of the avoiding groove is not smaller than the total height of a residual step on the end face of the chip and a deep groove protruding structure so as to eliminate mechanical interference. The tail end of the optical fiber is positioned in the V-shaped groove, and the light-emitting end face is parallel and tightly butted with the end face of the chip. The customized avoiding groove is integrated in the cover plate, direct, lossless and low-loss coupling of the optical fiber array and the deep silicon etching silicon optical chip with the composite three-dimensional morphology end face can be achieved without extending the optical fiber, removing a bottom cover or polishing the end face of the chip, the integrity of the end face of the chip is effectively protected, and the coupling precision and the device yield are improved.

The invention discloses an in-plane three-axis large-displacement actuating platform based on MEMS and a manufacturing method thereof.The in-plane three-axis large-displacement actuating platform mainly comprises an outer frame, a cross island frame, a bidirectional comb-shaped driving unit, a long spring beam and a short spring beam, and the manufacturing method comprises the steps that a cavity structure on a glass substrate is anisotropically etched through magnetic neutral loop discharge plasma (NLD); the method comprises the following steps of: bonding a BF33 glass wafer with a cavity structure with a low-resistance silicon wafer by using an anodic bonding process, thinning the low-resistance silicon wafer, performing deep silicon etching (DRIE) on the low-resistance silicon wafer to form an electrical isolation channel and filling a BCB material, removing the BCB on the surface of the low-resistance silicon wafer by using a chemical mechanical polishing (CMP) process, sputtering a metal layer and forming a lead layer by using a lift-off process, and performing deep silicon etching (DRIE) on the low-resistance silicon wafer to form a final device. The method has the beneficial effects that the filling rate of the device is improved, the size is reduced, the structural rigidity, the response speed, the resonant frequency and the heat dissipation performance are improved, and meanwhile, a routing method for heterogeneously integrating the micro-motion platform and the CMOS chip is provided.

The present invention discloses a method for optimizing the sidewalls of a Bosch etching process, comprising the following steps: S1, pretreatment: providing a wafer subjected to a Bosch etching process; pre-treating the wafer subjected to the Bosch etching process using a first cleaning solution; S2, etching: placing the wafer subjected to the pre-treatment in step S1 in a silicon etching solution for room-temperature etching; S3, mask removal: cleaning the wafer subjected to the etching in step S2 using a second cleaning solution at room temperature to remove the SiO2 mask on the wafer surface. The optimization method of the present invention smoothes the sidewall ripples produced by the Bosch etching process, thereby improving device performance and lifespan.

The present invention relates to the field of circulator technology, in particular to the field of IPC H04B, and more specifically to a method for manufacturing a ceramic composite silicon-based circulator and its application. The present invention obtains a ceramic composite silicon-based circulator by cutting through eight steps: deep silicon etching through holes, making ferrite discs, preparing composite substrates, making dielectric bridges, photolithography patterns, vacuum coating, photoresist stripping, and scribing and slicing. The present invention adopts a silicon wafer commonly used in semiconductor technology, embeds a ferrite ceramic disc in the middle of each silicon wafer through hole, connects them into a completed circuit substrate substrate through a specific adhesive material, and then manufactures a microstrip circulator through a semiconductor thin film process. Dielectric bridge metallization technology is used at the connection between the two materials to ensure the continuity and reliability of the circuit connection. The circulator has a wide operating frequency band, high power resistance, good consistency, easy integration, and low cost. It is very suitable for use in isolators, duplexers, reflection amplifiers and other fields.

The invention provides compositions useful in the etching of polysilicon in the presence of silicon oxide and silicon nitride. The compositions comprise choline hydroxide, an oxidizing agent such as periodic acid, and optionally a surfactant, and are useful in the etching of polysilicon in general, and in particular in both the operation of polysilicon trim as well as polysilicon exhume. The utilization of an added oxidizing agent was found to reduce selectivity of silicon etching based on the silicon crystal orientation, which was found to reduce roughness and the presence of residual silicon residues, such as silicon (111) residues after the etching step.

The application discloses a piezoelectric MEMS device preparation process and a device structure, and relates to the technical field of piezoelectric MEMS device preparation. The preparation process comprises the following steps: forming a groove near an edge region on a front surface of a substrate, depositing a sacrifice layer on the front surface of the substrate and patterning the sacrifice layer, so that the sacrifice layer is separated into a center region and an edge support region, forming a piezoelectric-buffer stack on the sacrifice layer and patterning the piezoelectric-buffer stack, and opening a release hole, the release hole being communicated with the center region of the sacrifice layer, introducing etching medium into the release hole to remove the center region of the sacrifice layer, and then etching a back cavity on the back surface of the substrate. The application limits the size of a diaphragm region through the groove, etches the back cavity of the substrate after the sacrifice layer is released, and compared with a traditional method of defining the diaphragm by etching the back cavity, the application completely avoids the size error of the diaphragm caused by the angle deviation of deep silicon etching, accurately locks the profile of the diaphragm, and greatly improves the size consistency and performance stability of devices in the same batch.

The invention provides a method for protecting an anodic bonding surface in deep silicon etching, which comprises the following steps of: providing a wafer, and sequentially forming a protective layer and a barrier layer on the surface of the wafer; patterning the barrier layer and the protective layer by utilizing photoetching and etching processes; preparing a required structure through a deep silicon etching process by taking the patterned barrier layer as an etching mask; and removing the barrier layer by using a dry etching process, and removing the protective layer by using a dry photoresist removing process. A protective layer easy to remove is additionally arranged between a bonding surface and an etching barrier layer in deep silicon etching, and when the barrier layer is removed through subsequent dry etching, the problem that the roughness of the bonding surface becomes high due to ion bombardment can be prevented through the protective layer on the bonding surface.

The application provides a silicon-based three-dimensional capacitor and a manufacturing method thereof. The manufacturing method comprises the following steps: preparing a dielectric mask layer on the surface of a silicon substrate, etching a plurality of spaced-apart etching micropores on the dielectric mask layer until the silicon substrate is exposed, etching the plurality of spaced-apart etching micropores by using a deep silicon etching process to form a plurality of spaced-apart first deep holes, removing the remaining dielectric mask layer, preparing a first polysilicon layer on the silicon substrate with the plurality of spaced-apart first deep holes, etching the first polysilicon layer in the first deep holes by using a deep silicon etching process to form second deep holes in the first polysilicon layer in the first deep holes, and the bottom surface and the side surface of the second deep holes are provided with the first polysilicon layer, and growing an insulating dielectric layer, a second polysilicon layer and an electrode layer on the first polysilicon layer on the surface of the first silicon substrate and in all the spaced-apart second deep holes in sequence. The silicon-based three-dimensional capacitor prepared by the application can improve the density of the capacitor.