139 results about "Silicon etching" patented technology

The invention discloses a heat dissipation enhanced semiconductor packaging method, which comprises the following steps of: performing deep silicon etching to form a vertical through hole; insulation and metallization are carried out; thinning the wafer; performing hybrid bonding and stacking of multiple layers of chips; a heat dissipation design is adopted to form a vertical heat dissipation path; a three-dimensional thermal through hole network: adding pure copper thermal through holes in a non-functional area; performing microfluid cooling integration; molding and packaging; and thermal performance verification: verifying that the junction temperature can be controlled within 85 DEG C through infrared thermal imaging and finite element simulation. The TSV with the depth-to-width ratio of 10: 1 can be realized by adopting the Bosch process; a three-dimensional integrated TSV array supporting HBM and other high-speed memories is embedded into diamond or graphene heat dissipation columns, a low-heat-resistance vertical heat dissipation path is formed by combining a three-dimensional pure copper heat through hole network, and local hot spots are effectively dispersed; the high-thermal-conductivity epoxy molding compound and the embedded copper block enhance the overall mechanical strength and thermal diffusivity, so that the product can dissipate heat efficiently, and the overall area is not easy to influence.

The invention discloses a high aspect ratio deep silicon etching structure and a patterning method thereof. The patterning method comprises the following steps: providing a substrate made of silicon; forming a plurality of photoresist patterns on the surface of the substrate, wherein an opening is formed between every two adjacent photoresist patterns; bombarding the interface of the substrate at the inner bottom corner of the opening by using plasma of a first gas at a first ultralow temperature to form a first protective film; depositing a polymer layer on the substrate, the photoresist pattern and the first protective film for protection by using plasma of second gas at a second ultralow temperature; etching the polymer layer and the substrate by using plasma of a third gas at a third ultralow temperature; repeating the steps of depositing the polymer layer and etching until a high aspect ratio deep silicon etching structure is formed on the substrate; and removing the photoresist pattern. According to the invention, the uniform protection of the side wall under the conditions of smaller size and higher aspect ratio can be realized, and the etching rate can be improved.

Provided is an etching solution composition capable of preventing reduction in the etching rate of a silicon nitride film, achieving high etching selectivity with respect to silicon nitride, and suppressing deposition of silica on the surface of silicon oxide.　This etching solution composition is based on an inorganic acid and is for selectively etching silicon nitride from a semiconductor containing the silicon nitride and silicon oxide, and comprises: (a) a fluorine compound that increases the etching rate of silicon nitride; and (b) a volatilization inhibitor that inhibits volatilization of the fluorine compound.

The invention discloses a superconducting quantum chip, a substrate and a processing method thereof, and belongs to the technical field of deep silicon etching. The substrate processing method comprises the following steps: providing a substrate with a first photoresist layer on the surface; a first groove for exposing a part of the substrate is formed in the first photoresist layer; forming a protective layer on the inner wall of the first groove; the protective layer surrounds to form a second groove; and etching the substrate through the second groove in the thickness direction of the substrate. Through the mode, the first photoresist layer is not influenced when the substrate is etched, and the form of the first groove formed by the first photoresist layer is protected, so that the problems of expansion, breakage and the like of the first groove are avoided, and the condition that the etching of the substrate cannot meet the expected parameter requirement is avoided.

The application provides a deep silicon etching method and a semiconductor process equipment, and relates to the technical field of semiconductors. The deep silicon etching method comprises a first cycle step and a second cycle step. The first cycle step and the second cycle step both comprise an etching step for etching a silicon substrate to form a groove, a removal step for removing by-products, and a deposition step for forming a protective layer on the sidewall of the groove. The protective gas used in the deposition step of the second cycle step comprises an oxygen-containing gas, and the lower electrode power of the deposition step of the second cycle step is greater than that of the deposition step of the first cycle step. The deep silicon etching method can balance the etching rate of different regions of the isolation groove, optimize the depth micro-loading effect, and improve the depth consistency of the isolation groove. Meanwhile, the deposition step does not consume the mask layer, thereby reducing the consumption of the mask layer, ensuring the effective height of the mask layer, improving the morphology precision of the formed isolation groove and AA, and improving the electrical properties and yield of the product.

The invention discloses a non-polishing low-loss coupling optical fiber array adaptive to a deep silicon etching photon chip, a deep silicon etching photon chip coupling assembly and a method, and belongs to the technical field of silicon photon integration. The device comprises an optical fiber array main body, a V-shaped groove substrate and a special-shaped cover plate, the special-shaped cover plate is attached to the upper surface of the V-shaped groove substrate, an avoiding groove is formed in the position, corresponding to a deep silicon etching area of the end face of the chip, of the special-shaped cover plate, and the depth of the avoiding groove is not smaller than the total height of a residual step on the end face of the chip and a deep groove protruding structure so as to eliminate mechanical interference. The tail end of the optical fiber is positioned in the V-shaped groove, and the light-emitting end face is parallel and tightly butted with the end face of the chip. The customized avoiding groove is integrated in the cover plate, direct, lossless and low-loss coupling of the optical fiber array and the deep silicon etching silicon optical chip with the composite three-dimensional morphology end face can be achieved without extending the optical fiber, removing a bottom cover or polishing the end face of the chip, the integrity of the end face of the chip is effectively protected, and the coupling precision and the device yield are improved.

The invention provides compositions useful in the etching of polysilicon in the presence of silicon oxide and silicon nitride. The compositions comprise choline hydroxide, an oxidizing agent such as periodic acid, and optionally a surfactant, and are useful in the etching of polysilicon in general, and in particular in both the operation of polysilicon trim as well as polysilicon exhume. The utilization of an added oxidizing agent was found to reduce selectivity of silicon etching based on the silicon crystal orientation, which was found to reduce roughness and the presence of residual silicon residues, such as silicon (111) residues after the etching step.

The application discloses a piezoelectric MEMS device preparation process and a device structure, and relates to the technical field of piezoelectric MEMS device preparation. The preparation process comprises the following steps: forming a groove near an edge region on a front surface of a substrate, depositing a sacrifice layer on the front surface of the substrate and patterning the sacrifice layer, so that the sacrifice layer is separated into a center region and an edge support region, forming a piezoelectric-buffer stack on the sacrifice layer and patterning the piezoelectric-buffer stack, and opening a release hole, the release hole being communicated with the center region of the sacrifice layer, introducing etching medium into the release hole to remove the center region of the sacrifice layer, and then etching a back cavity on the back surface of the substrate. The application limits the size of a diaphragm region through the groove, etches the back cavity of the substrate after the sacrifice layer is released, and compared with a traditional method of defining the diaphragm by etching the back cavity, the application completely avoids the size error of the diaphragm caused by the angle deviation of deep silicon etching, accurately locks the profile of the diaphragm, and greatly improves the size consistency and performance stability of devices in the same batch.

The application provides a silicon-based three-dimensional capacitor and a manufacturing method thereof. The manufacturing method comprises the following steps: preparing a dielectric mask layer on the surface of a silicon substrate, etching a plurality of spaced-apart etching micropores on the dielectric mask layer until the silicon substrate is exposed, etching the plurality of spaced-apart etching micropores by using a deep silicon etching process to form a plurality of spaced-apart first deep holes, removing the remaining dielectric mask layer, preparing a first polysilicon layer on the silicon substrate with the plurality of spaced-apart first deep holes, etching the first polysilicon layer in the first deep holes by using a deep silicon etching process to form second deep holes in the first polysilicon layer in the first deep holes, and the bottom surface and the side surface of the second deep holes are provided with the first polysilicon layer, and growing an insulating dielectric layer, a second polysilicon layer and an electrode layer on the first polysilicon layer on the surface of the first silicon substrate and in all the spaced-apart second deep holes in sequence. The silicon-based three-dimensional capacitor prepared by the application can improve the density of the capacitor.

Disclosed are a method of forming a pattern structure including a silicon nitride. According to the embodiment of the present disclosure, the method of forming a pattern structure includes a step of providing, into a substrate processing apparatus, a substrate having one surface on which a pattern structure including a recess region in which an opening periphery portion and a bottom portion are made of a first silicon nitride is formed, a deposition step of depositing a second silicon nitride on the first silicon nitride, an etching step of etching the second silicon nitride, and a step of performing steps in one cycle n times until the first silicon nitride constituting the bottom portion is removed.

A method to create flexible mutli-conductor cables include fabricating wiring on silicon-on-insulator wafers with lithographic fabrication techniques followed by thinning some sections of the wafer with a silicon etch. Exemplary cables can have fine pitch and low thermal conductivity enabling high density superconducting interconnects between different temperature stages in cryogenic platforms or between superconducting circuits oriented perpendicular to each other. Also presented herein are methods for making and using exemplary cables.

This application provides a continuous titration method for the sulfuric acid and ammonium nitrate content of silicon etching solution. The continuous titration method includes the following steps: weigh m grams of silicon etching solution sample into a sample bottle, add phenolphthalein indicator, titrate with a first sodium hydroxide standard solution of concentration C1 until a pink color is achieved, and record the volume consumed V1. Calculate the sulfuric acid content. Add neutral formaldehyde solution to the same solution and let it stand for a first preset time to generate a free acid solution. Continue titrating the free acid solution with a second sodium hydroxide standard solution of concentration C2 until the solution turns pink. Gently heat the solution to a preset temperature and maintain this temperature for a second preset time. If the pink color persists, the titration endpoint is determined, and the volume consumed V2 is recorded. Calculate the ammonium nitrate content. This method achieves continuous titration of two components with a single sample, eliminates mutual interference between components, optimizes the endpoint determination method, and thus achieves a simple operation, high accuracy, low sample consumption, and high detection efficiency.

The invention provides a long-acting high-stability silicon nitride etching solution as well as a preparation method and application thereof. The long-acting high-stability silicon nitride etching solution comprises the following components in parts by weight: 1-5 parts of fluorophenylalkylamine; 80-90 parts of strong phosphoric acid; and 13 to 17 parts of ultrapure water. The fluorophenyl alkylamine is one or more of monofluoro substituted phenylamine, difluoro substituted phenylamine, monofluoro substituted benzylamine and difluoro substituted benzylamine. The invention also discloses a preparation method and application of the long-acting high-stability silicon nitride etching liquid. According to the long-acting high-stability silicon nitride etching solution, efficient etching of silicon nitride, dissolution control of byproducts, stability improvement of the etching solution and selective protection of silicon oxide are achieved at the same time, and the long-acting high-stability silicon nitride etching solution has very good application prospects and large-scale industrial popularization potential in the field of silicon nitride etching of 3D flash memory chips.

The invention discloses a manufacturing method of a U-shaped groove, which is characterized in that a photoresist reserved on a field oxide in an X-direction photoetching process of the U-shaped groove can protect a hard mask on the field oxide of a Y-direction opening of a non-U-shaped groove region, the loss of the hard mask on the field oxide of the Y-direction opening of the non-U-shaped groove region cannot be caused, and a U-shaped groove process window is enlarged; in the process of performing X-direction silicon etching to form a U-shaped groove, silicon at an X-direction opening at a non-overlapping position of an X-direction opening pattern and a Y-direction opening pattern is protected by a mask first silicon oxide layer and a mask second silicon nitride layer, when the mask at the position is removed, the mask second silicon nitride layer is removed firstly, then the first silicon oxide layer is removed, and the first silicon oxide layer is removed after the mask second silicon nitride layer is removed. The SIN hard mask on the field oxide is not damaged, and the morphology standard of the U-shaped groove can be ensured.

The invention discloses a silicon three-dimensional etching device and etching method, and relates to the technical field of silicon etching. The device comprises a pre-conveying assembly, a processing box, an etching assembly, an etching box fixed to the outer side wall of the processing box, a mounting positioning assembly, an operation box fixed to the lower end face of the processing box, a locking adsorption assembly, a linkage box fixed to the outer bottom of the etching box and communicated with the interior of the etching box, and a recycling separation assembly. Comprising a backflow cylinder located at the top position in a processing box, a centrifugal cylinder is arranged in the backflow cylinder, and a transfer storage assembly used for storing a plurality of silicon wafers up and down is arranged in the backflow cylinder. According to the invention, the centrifugal cylinder and the backflow cylinder are used in cooperation, so that the recycling of the etched mixed gas is realized, the electromagnet and the suction cylinder are used in cooperation, the rapid positioning of the silicon wafer is realized, the position stability of the silicon wafer is ensured, the gas is uniformly distributed and shunted by the honeycomb plate, the uniformity of plasma impact is realized, and the uniformity of the plasma impact is improved. And the etching quality is ensured not to be reduced.

The present invention provides an etching solution composition for silicon that yields an etching rate corresponding to the silicon dopant type, and a method for etching a surface having a first silicon region that is n-type and a second silicon region that differs from the first silicon region in terms of dopant type. [Solution] The etching solution composition provides an etching rate for silicon that corresponds to the silicon dopant type. The etching solution composition contains a base and an additive other than the base. The additive has 1 to 6 carbon atoms per molecule.

The invention discloses an MEMS (Micro Electro Mechanical System) thermal acceleration sensor for realizing wafer-level packaging by utilizing a silicon structure in glass and a preparation method. The sensor adopts a three-layer stacked structure, and comprises a silicon sealing cover in glass, an acceleration sensor body and a sealing laminated wafer. Wherein a silicon conductive through column which is electrically insulated from the glass medium is arranged in the glass-in-silicon sealing cover, so that electric signal transmission in the vertical direction is realized; the acceleration sensor body comprises a heating and temperature measuring module manufactured on a supporting layer; the sealing bonding wafer and the sealing cover jointly form a sealed cavity to package the working fluid. The preparation method comprises the following steps: preparing a silicon-in-glass sealing cover through two times of deep silicon etching, anodic bonding and a glass backflow process, manufacturing a sensor functional structure on a silicon substrate and forming a back cavity, and finally completing wafer-level integrated packaging through a surface mounting process. The wafer-level batch preparation and packaging complete solution of the thermal acceleration sensor is realized, and the problems of high packaging cost and low efficiency of a non-standard process are solved.

The invention relates to the field of ultrasonic transducer manufacturing, in particular to a micromechanical ultrasonic transducer and a manufacturing process thereof, and the manufacturing process comprises the following steps: S1, etching an etching boundary of a preset cavity at a monocrystalline silicon substrate; s2, performing oxidation treatment on the preset monocrystalline silicon substrate with the etched boundary to form an oxide layer; s3, growing monocrystalline silicon on the oxide layer to serve as a mechanical support layer; s4, carrying out planarization treatment on the surface of the mechanical supporting layer; s5, sequentially depositing a lower electrode metal layer, a piezoelectric layer, an upper electrode metal layer and a passivation layer on the planarized mechanical support layer to form a core stack structure; and S6, taking the etching boundary and the oxide layer as a two-dimensional etching stop layer, and performing deep silicon etching on the back surface to form a cavity. According to the micromechanical ultrasonic transducer and the manufacturing process thereof, the etching precision is improved, and the production cost is saved.

The application provides a deep silicon etching structure and a preparation method thereof. By introducing a sacrifice passivation layer into a first groove on the surface of a structure to be etched, a firm physical barrier is constructed by using the high etching selectivity of the sacrifice passivation layer relative to a deep silicon etching gas and the excellent etching resistance of the sacrifice passivation layer. When a deep silicon etching process is performed on an SOI substrate, the sacrifice passivation layer can effectively block the bombardment of high-energy plasma, greatly reducing the risk of damage to the metal layer, so as to ensure that the device will not fail due to the thinning, open circuit or short circuit of the metal layer, guaranteeing the electrical integrity of the device. Furthermore, compared with the traditional process, the application only needs to add one step of depositing the sacrifice passivation layer and one step of etching to open the window area of the deep silicon etching, so that the preparation process is simple and the production cost is significantly reduced.

This invention discloses a pneumatic micro-transport device, including an air compressor connected to a pneumatic solenoid valve via an air pump pipe. The pneumatic solenoid valve is connected to a microcontroller via a relay, and the microcontroller is connected to a LabVIEW host computer via a USB interface. The pneumatic solenoid valve is also connected to a micro-transport array via the air pump pipe, and a transport plate is placed above the micro-transport array. This device is designed based on pneumatic principles. Compared to traditional contact-type transport devices, its transport method avoids failures caused by friction-induced wear. Furthermore, thanks to its non-contact transport characteristics, its application range is further expanded. It employs deep silicon etching micromachining technology, with the silicon plate structure serving as the air chamber channel and nozzle of the micro-transport device, significantly reducing the structural size of the micro-transport device, improving space utilization, and solving problems such as low integration in traditional micro-transport devices.

This invention provides a MEMS structure and its fabrication method, specifically a MEMS piezoelectric microphone. The fabrication method includes: Step A, forming a thermo-oxidative layer with arc-shaped protrusions on the front side of a substrate; Step B, forming a composite vibration layer with an arc-shaped protrusion on the substrate containing the thermo-oxidative layer arc-shaped protrusions; Step C, performing deep silicon etching on the back side of the substrate and releasing the thermo-oxidative layer to form a substrate back cavity, thus suspending the composite vibration layer with the arc-shaped protrusion. In this invention, the amplitude and precision of the thermo-oxidative layer arc-shaped protrusions are controlled using a dry etching process. This process is simple, convenient, and highly accurate. Furthermore, the subsequently deposited composite vibration layer follows the arc-shaped protrusion of the thermo-oxidative layer, exhibiting a smoother and more natural shape, resulting in more effective stress release.

The present application relates to a kind of wafer cutting protection fluid for laser-assisted plasma etching process and its preparation method and application, according to weight parts, the wafer cutting protection fluid includes: water-soluble furan-based polyamide resin 70~85 parts;Solvent 15~25 parts;Plasticizer 1~5 parts;Ultraviolet light absorber 0.1~1 parts;Leveling agent 0.1~1 parts.The wafer cutting protection fluid provided by the present application can form a protective film with excellent mechanical properties, wear resistance and heat resistance, and easy to clean, widely used in thin wafer processing, deep silicon etching and TSV through hole and other processing processes.

This invention provides a double-sided deep silicon etching method and a MEMS device. The double-sided deep silicon etching method includes: providing an SOI substrate, on which a top silicon layer, a buried oxide layer, and a bottom silicon layer are sequentially formed; performing a first deep silicon etching on the top silicon layer to form multiple blind vias stopping at the buried oxide layer; after completing the first deep silicon etching, depositing a protective layer on the top silicon layer, the protective layer being deposited on the surface of the top silicon layer and at the corners of the top silicon layer at the openings of the blind vias; after completing the protective layer deposition, attaching an electrostatic film to the top silicon layer, flipping the SOI substrate, and performing a second deep silicon etching on the bottom silicon layer to form vias communicating with the blind vias; after completing the second deep silicon etching, removing the protective layer of the top silicon layer. The double-sided deep silicon etching method provided by this invention can effectively improve the problem of damage to the front morphology of the silicon substrate during double-sided deep silicon etching.

Embodiments of the disclosure include apparatus which includes a substrate disposed on a substrate support within a substrate processing chamber. A surface of the substrate has a layer of byproduct from a silicon etching process. A reactive layer is formed in the layer of byproduct by injecting hydrogen fluoride into the substrate processing chamber and maintaining a temperature of the substrate support at less than 0 degrees Celsius. The hydrogen fluoride is purged from the substrate processing chamber by flowing argon into the substrate processing chamber. A plasma is generated by ionizing the argon. A portion of the layer of byproduct is removed from the surface of the substrate by using the plasma for desorption of the reactive layer.

This invention relates to the field of deep silicon etching technology for semiconductors, and discloses a method, apparatus, and etching apparatus for reducing wafer drop rate during etching processes. The apparatus for reducing wafer drop rate includes a venting controller and a ceramic shielding disk. One end of the venting controller is connected to an air inlet pipe, and the other end is connected to the venting pipe of the etching equipment. The ceramic shielding disk is disposed on the lower electrode base of the etching equipment. After etching, the venting controller introduces gas into the etching equipment, causing the wafer to float and fall, thereby eliminating the residual electrostatic adhesion effect on the wafer after etching. The ceramic shielding disk limits the movement range of the wafer during the floating process. The apparatus for reducing wafer drop rate provided by this invention, through the combined use of the ceramic shielding disk and the venting controller, eliminates the residual electrostatic adhesion effect on the wafer after etching, solving the problem of high wafer drop rate in existing etching processes.

To provide a new chemical solution capable of wet-etching silicon at high speed when manufacturing a semiconductor device or the like.SOLUTION: A silicon etching agent comprises an alkaline aqueous solution containing peroxodisulfate ions in a range of 0.05 to 65 mmol / L, particularly preferably 0.2 to 10 mmol / L, free of metals such as Ag, Al, Ba, Ca, Cd, Co, Cr, Cu, Fe, K, Li, Mg, Mn, Na, Ni, Pb and Zn (preferably each metal is 1 ppbw or less), and having a pH of 12.5 or more, preferably 13.0 or more and 13.7 or less. Production thereof is made possible by mixing high-purity ammonium peroxodisulfate and high-purity quaternary ammonium hydroxide with ultrapure water and uniformly dissolving them.SELECTED DRAWING: None

To provide an etching solution composition for silicon that yields an etching rate corresponding to the silicon dopant type. [Solution] The etching solution composition provides an etching rate for silicon that corresponds to the silicon dopant type. The etching solution composition comprises a water-soluble etching solution, one or more water-miscible organic solvents, and one or more surfactants.

A method for forming back etching of source and drain silicon in a transistor comprises the steps that a substrate is provided, the substrate comprises a device area, and a channel protruding part protrudes from the top of the substrate in the device area; in the device region, forming a gate structure crossing the channel lug boss, and covering a part of the top and a part of the side wall of the channel lug boss by the gate structure; forming a side wall material layer on the surface of the channel lug boss and the surface of the gate structure; removing the side wall material layer covering the surface of the channel lug boss and the top of the gate structure; and forming a source-drain doping layer in the channel lug bosses at the two sides of the gate structure. According to the method, the side wall material layer covering the surface of the channel lug boss and the top of the gate structure is removed completely, so that the cleanliness of the surface of the channel lug boss can be improved, the morphology of a source-drain groove formed in the channel lug boss subsequently is further improved, the stress action of the source-drain region from top to bottom in the channel structure is more uniform, and the reliability of the device is improved. Therefore, the performance of the semiconductor structure is improved.

The present invention provides a method for forming self-transformed support plates in shallow trench isolation for advanced semiconductor devices, in which after a photolithography process to define active areas on a silicon substrate, an additional photomask is implemented to add a support plate patterning layer in areas where silicon will be etched during a STI etching step to form STI trenches. Tiny silicon support plates inside the STI trenches are formed after the silicon etching. These silicon support plates may provide mechanical support to hold neighboring patterned strips where the active areas are defined or neighboring active areas islands, and preventing them from bending, deformed or shifting. An alignment of photomask pattern at following photolithography process is eased.

The application discloses a high-etching-rate and high-smoothness silicon etching solution for wafer back thinning, which comprises HNO3, HF, H2SO4, H3PO4 and the rest water. The etching solution is compounded by HNO3, HF, H2SO4 and H3PO4 in a specific ratio, and can realize high etching rate and low roughness. The high etching rate can significantly improve the process efficiency of the thinning step, meet the process time of the etching machine, and meet the requirements of large-scale commercial production on efficiency and cost. The silicon etching solution can be used for wafer back thinning, and can realize the process requirements of fast etching (shortening process time) and smooth surface (low roughness).