1042 results about "Deep trench" patented technology

The invention discloses a semiconductor structure manufacturing method and a semiconductor structure, and the manufacturing method comprises the steps: carrying out the periodic cycle etching of a preset number of times on a substrate through employing an etching technology, forming a first intermediate structure on the substrate, and carrying out the first processing of the first intermediate structure, including employing a first gas and a second gas, removing a part of thickness of the passivation layer deposited on the side wall of the first intermediate structure, and reacting with the substrate material which exists on the side wall and is exposed on the surface of the convex part to generate a reaction product layer; and removing the reaction product layer by using a third gas and a fourth gas so as to remove at least part of the lug boss, and repeatedly executing the etching process and the first processing process until a high aspect ratio etching structure is formed on the substrate. According to the method, the etching process and the side wall processing technology are organically combined, the etching rate and the side wall quality are balanced through alternate circulation, and deep silicon etching with the higher aspect ratio and the smaller nanoscale size can be achieved.

The invention discloses a manufacturing method of a groove, a semiconductor device and a manufacturing method of the semiconductor device, and relates to the technical field of semiconductors, and the manufacturing method comprises the steps: providing a substrate, forming a first mask layer on the substrate, and etching the first mask layer by taking a photomask as a mask, so that the first mask layer covers the substrate of a first groove region, forming a second mask layer on the substrate, etching the second mask layer to enable the second mask layer to expose the first mask layer and the substrate in the second groove region, etching the substrate in the second groove region by taking the first mask layer and the second mask layer as masks to form a relatively shallow second groove, and etching the first mask layer to form a relatively shallow second groove; according to the method, the substrate of the first trench region and the substrate of the second trench region are exposed by the second mask layer, and the substrate of the first trench region and the substrate of the second trench region are etched by taking the second mask layer as a mask to form a deeper second trench and a shallower first trench, so that a shallow trench and a deep trench can be manufactured by adopting one photomask, and the manufacturing cost can be further reduced.

The invention relates to the technical field of semiconductors, in particular to a device integrated with a deep trench isolation structure and a preparation method of the device. The preparation method comprises the steps that a semiconductor structure is provided, the semiconductor structure comprises a substrate, a gate material layer stacked on the surface of the substrate and a mask layer stacked on the gate material layer, and a functional element of the semiconductor device is formed in the substrate; forming a deep trench in the semiconductor structure, wherein the deep trench penetrates through the mask layer and the gate material layer and goes deep into the substrate; the deep trench is filled to form a deep trench isolation structure, the deep trench isolation structure comprises a filling structure, the filling structure is not higher than the surface of the substrate, and the material of the filling structure is a conductive non-metal material; patterning and etching the gate material layer to form a gate structure; and removing the mask layer. According to the invention, the preparation process of the deep trench isolation structure can be integrated into the standard process for preparing the gate structure of devices such as a BCD, the integration process of deep trench isolation is simplified, and the preparation cost is reduced.

Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a deep trench via in a double diffusion region between a first dummy metal gate and a second dummy metal gate; a frontside metal wire conductively connected to a top surface of the deep trench via through a frontside via; and a backside metal wire conductively connected to a bottom surface of the deep trench via through a backside via and a backside contact, where the frontside metal wire and the backside metal wire are not vertically aligned but parallel to each other, and directions of the frontside and backside metal wires are orthogonal to a length direction of the deep trench via. A method of forming the same is also provided.

Technologies for components embedded in a substrate core are disclosed. In one embodiment, power components such as deep trench capacitors and multi-layer ceramic capacitors (MLCCs) are disposed in a cavity defined in a substrate core for a circuit board of an integrated circuit package, such as a processor. The power components are stacked on top of each other, allowing for the stack of power components to match the height of the substrate core, even when the height of the individual power components is less than the height of the substrate core. Configuring the power components in this manner can provide mechanical stability to the power components and substrate core and provide power to a semiconductor die mounted on the circuit board.

Aspects of the disclosed invention provide a semiconductor structure for a semiconductor chip with two layers of semiconductor devices, where the first layer of semiconductor devices directly contacts a semiconductor substrate and connects to a first frontside interconnect wiring. The first layer of semiconductor devices includes at least one trench semiconductor device such as a deep trench capacitor. The first frontside interconnect wiring is electrically connected to the second frontside interconnect wiring by one or more joined metal plugs. The second layer of active devices connects to a backside power delivery network and the second frontside interconnect wiring. The semiconductor chip with two layers of semiconductor devices that are bonded together provides one layer of semiconductor devices capable of being in a portion of the semiconductor substrate and a second layer of semiconductor devices with a backside power delivery network.

The invention relates to the technical field of semiconductor integrated circuit manufacturing, in particular to a manufacturing method of a semiconductor device. Comprising the following steps: providing a semiconductor substrate; forming a deep trench isolation structure in the isolation region, wherein the upper surface of the deep trench isolation structure is higher than the upper surface of the active region by a specific height; sequentially performing first etching and second etching on the active region of the high-voltage device region and the edge part, close to the active region, of the deep trench isolation structure of the high-voltage device region; etching the edge part, close to the active region, of the deep trench isolation structure of the high-voltage device region after the first etching and the second etching, and reducing the height difference between the upper surface of the active region of the high-voltage device region and the upper surface of the edge part, close to the active region, of the deep trench isolation structure of the high-voltage device region; and depositing to form a high-voltage oxide layer, wherein the high-voltage oxide layer covers the upper surface of the active region of the high-voltage device region and the upper surface of the edge part, close to the active region, of the deep trench isolation structure of the high-voltage device region.

Technologies for components embedded in a substrate core are disclosed. In one embodiment, power components such as deep trench capacitors are disposed in a cavity defined in a substrate core for a circuit board of an integrated circuit package, such as a processor. The power components are stacked on top of each other, allowing for the stack of power components to match the height of the substrate core, even when the height of the individual power components is less than the height of the substrate core. The stack may include, e.g., three or more power components. Through-silicon vias in some or all of the power components can allow for connections through one power component to another. Configuring the power components in this manner can provide mechanical stability to the power components and substrate core and provide power to a semiconductor die mounted on the circuit board.

Some embodiments relate to a CMOS image sensor disposed on a substrate. A plurality of pixel regions comprising a plurality of photodiodes, respectively, are configured to receive radiation that enters a back-side of the substrate. A boundary deep trench isolation (BDTI) structure is disposed at boundary regions of the pixel regions, and includes a first set of BDTI segments extending in a first direction and a second set of BDTI segments extending in a second direction perpendicular to the first direction to laterally surround the photodiode. The BDTI structure comprises a first material. A pixel deep trench isolation (PDTI) structure is disposed within the BDTI structure and overlies the photodiode. The PDTI structure comprises a second material that differs from the first material, and includes a first PDTI segment extending in the first direction such that the first PDTI segment is surrounded by the BDTI structure.

A trench capacitor manufacturing method is provided. The method includes forming a deep trench in a wafer, forming a trench capacitor structure including a plurality of dielectric films and a plurality of conductive layers in the deep trench; determining if the wafer has a tensile stress based on the forming of the trench capacitor structure; performing a high temperature heat treatment to the trench capacitor structure to change a form of the wafer to a direction that offsets the tensile stress; forming an inter-layer insulating film on the trench capacitor structure; and forming a metal interconnect on the inter-layer insulating film.

An image sensor including a substrate having first and second surfaces, the second surface opposite the first surface; a first deep trench isolation layer in the substrate and defining pixel region groups, each pixel region group having a pair of pixel regions; a second deep trench isolation layer between the pair of pixel regions of each pixel region group; photoelectric conversion areas in each pixel region; and a lens array on the second surface and composed of two-dimensionally arranged microlenses. Each microlens having a shape, in plan view, with a long axis and a short axis, the short axis being substantially perpendicular to the long axis and shorter than the long axis. The microlenses covering each pixel region group, and a width of at least a first portion of the second deep trench isolation layer being smaller than a width of the first deep trench isolation layer.

Structures for a high-voltage field-effect transistor that include a deep trench isolation region and methods of forming such structures. The structure comprises a semiconductor substrate, a semiconductor layer on the semiconductor substrate, and a doped layer between the semiconductor layer and the semiconductor substrate. The structure further comprises a trench isolation region including a metal layer that extends through the semiconductor layer and the doped layer into the semiconductor substrate.

Various embodiments of the utility model relate to a semiconductor device, the semiconductor device comprises a plurality of photodiode doped regions formed in a substrate and a deep trench isolation (DTI) structure formed in the substrate, the DTI structure separates the photodiode doped regions, and the DTI structure comprises a first filling material defining an air gap therein. The first filling material comprises a top, a side wall and a bottom. The semiconductor device also includes a first isolation layer surrounding and contacting the top, sidewalls, and bottom of the first fill material.

The invention relates to a machining method for large-diameter deep-blind-hole alloy structural steel complex-shape deep groove quenched hardware. The problems that the large-diameter deep-blind-hole alloy structural steel complex-shape deep groove quenched hardware is high in machining precision, long in period, high in cost and prone to causing part scrapping are solved by means of various special cutters and clamps in different working procedures. A large-hole and deep-hole adjustable U drill, a large-hole and deep-hole bottoming drill, a numerical control vibration reduction cutter bar special for a deep blind hole double-tool-bit endoscope, a rapid dividing device and a special inner cooling quenching device are used for solving the machining problem of large-diameter deep-hole alloy structural steel complex-shape deep groove quenching hardware. The roundness of a deep hole of a machined workpiece is smaller than or equal to 0.015 mm, the symmetry degree of six-equal-division grooves is smaller than or equal to 0.03 mm, and the technical requirements of high-precision complex parts are completely met.

The invention discloses a 950V super-junction MOS device with a deep groove filling structure and a manufacturing method of the 950V super-junction MOS device. The 950V super-junction MOS device is provided with polycrystalline silicon deposition with a discontinuous structure and additionally provided with an independent gate source ESD protection area, the whole device is subjected to secondary epitaxy through an N-type substrate, and a plurality of functional layers are expanded according to the optimal condition. According to the invention, charge imbalance caused by unequal groove width due to an etching angle is relieved through the N-type substrate which is subjected to two times of epitaxy; polycrystalline silicon of cells is separated through etching, one half of the polycrystalline silicon is connected with gate metal, the other half of the polycrystalline silicon is connected with source metal, a Dummy structure is formed, the ratio of true cells to false cells is 1: 1, the problem that input capacitance is too large is effectively solved, and the dynamic characteristic of a device is effectively optimized on the premise that voltage resistance and dynamic on resistance are not affected; by arranging ESD protection between the gate electrode and the source electrode, the device is prevented from being damaged under the condition of transient high voltage and large current.

An image sensor comprising a photodiode, an inter-layer dielectric layer, and a deep trench isolation structure is described. The photodiode is disposed within a semiconductor substrate having a front side and a backside opposite the front side. The inter-layer dielectric layer is disposed over the front side of the semiconductor substrate such that the front side is disposed between the inter-layer dielectric layer and the backside. The deep trench isolation structure is configured to isolate the photodiode from adjacent photodiodes included in the image sensor. The deep trench isolation structure includes a trench disposed within the inter-layer dielectric layer and the semiconductor substrate and a fill material disposed within the trench. The trench extends through the inter-layer dielectric layer and the front side of the semiconductor substrate towards the backside of the semiconductor substrate.

The invention relates to the technical field of wellhead protection, and particularly discloses an oil production wellhead pressure self-adaption protection device which comprises a protection shell, an indicator lamp is installed on the protection shell, the protection shell comprises a shell body, and a main pipeline is arranged on the inner side of the shell body. A partition cavity, a pressurizing groove and a pressure sensing groove are sequentially formed in the outer side of the main pipeline from top to bottom, the partition cavity is a multi-angle deep groove, a partition assembly is installed in the partition cavity, one end of the partition assembly is installed on a hydraulic input pipe, and the hydraulic input pipes are communicated through hydraulic oil communication holes; by arranging the partition assembly, when blowout occurs, a pressure sensor collects pressure information, an electric signal controls a hydraulic assembly to extend, the sharp ends of triangular fault blocks pierce the interior of a pipeline, multi-direction pressure synchronous operation is formed among the four triangular fault blocks, the pipeline is rapidly cut off, and the pipeline cannot transport oil again; and rapid and complete plugging in the pipeline is realized.

An image sensor structure including a substrate, a pixel structure, and a deep trench isolation (DTI) structure is provided. The substrate includes a first side and a second side opposite to each other. The pixel structure includes a transfer transistor, a light sensing device, and a floating diffusion region. The transfer transistor includes a first gate. The first gate is disposed on the first side of the substrate. The light sensing device is disposed in the substrate and is located on one side of the first gate. The floating diffusion region is disposed in the substrate and is located on another side of the first gate. The DTI structure extends into the substrate from the second side of the substrate. The top-view pattern of the floating diffusion region does not overlap the top-view pattern of the DTI structure.

A semiconductor device, a back-side deep trench isolation (BDTI) structure of a semiconductor device, and method of manufacturing a semiconductor structure are provided. The semiconductor device, comprising: a pixel region disposed within a substrate and comprising an image sensing element configured to convert electromagnetic radiation into an electrical signal; and one or more BDTI structures extending from a first-side of the substrate to positions within the substrate; wherein the one or more of BDTI structures comprise one or more ferroelectric materials.

A trench cell structure having Schottky barriers and a preparation method thereof are provided. The trench cell structure includes a silicon substrate. A back metal layer is disposed on a back surface of the silicon substrate. The silicon substrate is heavily doped. A body region, a dielectric layer, and a front metal layer are sequentially disposed on a front surface of the silicon substrate from bottom to top. The drift region is lightly doped. Deep trench regions and a shallow trench region are defined on the body region at intervals. The deep trench regions and the shallow trench region include shielding electrodes and ohmic contact structures. The Schottky contact barriers are disposed between the deep trench regions and the shallow trench region, which reduces anode carrier injection efficiency when the trench cell structure is forwardly conducted, reduces reverse recovery charge, and reduces a reverse recovery time.

A semiconductor device is provided including a backside deep trench capacitor present in a deep trench device region and electrically connected to a source / drain region of a transistor and to a backside back-end-of-the-line (BEOL) structure. In some embodiments, the semiconductor device can also include a logic device region including at least one logic transistor that is located adjacent to the deep trench device region.

Disclosed herein are IC structures and devices that aim to mitigate proximity effects of deep trench vias. An example IC structure may include a device region having a first face and a second face, the second face being opposite the first face, and further include a conductive via extending between the first face and the second face, wherein the conductive via includes an electrically conductive material, and wherein a concentration of titanium at sidewalls of the conductive via is below about 1015 atoms per cubic centimeter.

Provided is a light detection sensor including: a substrate including a first surface and a second surface opposite to the first surface, wherein the second surface is a light incident surface; a deep trench isolator within a deep trench in the substrate and defining a pixel area; at least one recess into the pixel area from the second surface; a transparent electrode on the second surface and an inner surface of the at least one recess; and a first insulating film between the transparent electrode and the second surface and between the transparent electrode and the inner surface of the at least one recess.

The invention provides a method for forming a super junction device. The method comprises the following steps: forming an Mth N-type epitaxial layer on the surface of a wafer; forming a plurality of parallel and spaced Mth-layer deep grooves in the Mth-layer N-type epitaxial layer along the first direction by using a double mask plate with the same size and shape as the wafer, wherein the Mth-layer deep grooves penetrate through the whole Mth-layer N-type epitaxial layer; forming an Mth layer P-type column in each of the plurality of Mth layer deep trenches; forming an (M + 1) th N-type epitaxial layer on the surfaces of the Mth N-type epitaxial layer and the Mth P-type column; using a double mask plate to form a plurality of parallel and spaced (M + 1) th layer deep grooves in the (M + 1) th layer N-type epitaxial layer along the second direction, exposing a part of the surface of the Mth layer P-type column in the (M + 1) th layer deep grooves, the first direction being perpendicular to the second direction, and the (M + 1) th layer deep grooves penetrating through the whole (M + 1) th layer N-type epitaxial layer; and forming an (M + 1) th layer of P-type column in the (M + 1) th layer of deep trench.

A semiconductor device is provided. The semiconductor device includes a first region having a first gate structure disposed on a substrate and a second region having a second gate structure disposed on the substrate, a hard mask formed on the substrate, the first gate structure, and the second gate structure, a deep trench formed in the substrate between the first region and the second region, and formed to penetrate the hard mask to reach an inside of the substrate, and a planarized gap-fill insulating layer formed on the second gate structure and formed inside the deep trench. A topmost surface of the planarized gap-fill insulating layer and a topmost surface of the hard mask are coplanar.

Semiconductor structures and methods of forming the same are provided. A semiconductor structure of the present disclosure includes a contact feature disposed in a first dielectric layer, a first etch stop layer (ESL) over the contact feature and the first dielectric layer, a second dielectric layer over the first ESL, a second ESL over the second dielectric layer, a third dielectric layer over the second ESL, a third ESL over the third dielectric layer, a fourth dielectric layer over the third ESL, and a capacitor. The capacitor includes a bottom electrode layer continuously extending along a top surface of the fourth dielectric layer and vertically through the fourth dielectric layer, the third ESL, the third dielectric layer, the second ESL, the second dielectric layer, and the first ESL, an insulator layer disposed over the bottom electrode, and a top electrode layer disposed over the insulator layer.

An embodiment semiconductor device may include a semiconductor die; one or more redistribution layers formed on a surface of the semiconductor die and electrically coupled to the semiconductor die; and an active or passive electrical device electrically coupled to the one or more redistribution layers. The active or passive electrical device may include a silicon substrate and a through-silicon-via formed in the silicon substrate. The active or passive electrical device may be configured as an integrated passive device including a deep trench capacitor or as a local silicon interconnect. The semiconductor device may further include a molding material matrix formed on a surface of the one or more redistribution layers such that the molding material matrix partially or completely surrounds the active or passive electrical device.

The invention discloses a process method for forming a cavity structure on a substrate, and the method comprises the following steps: providing a silicon substrate, the surface of the silicon substrate is provided with a mask layer, the mask layer is provided with a plurality of opening patterns, and the bottoms of the opening patterns are exposed out of the top surface of the silicon substrate; introducing a first etching gas to ignite the plasma, and etching the silicon substrate downwards according to the opening pattern to form a plurality of shallow trenches; forming a protective layer on the side wall of the shallow trench; introducing a second etching gas to ignite the plasma, and continuing to execute the vertical etching step downwards along the shallow trench to a preset depth so as to form a deep trench; and third etching gas is introduced to ignite the plasma, and the transverse etching step continues to be executed in the lateral direction along the lower portions of the deep grooves so that the multiple deep grooves can be communicated to form a cavity with a connecting bridge at the upper end. The method solves the problem that a cavity structure with a connecting bridge at the upper end is difficult to obtain on the substrate by a traditional semiconductor device manufacturing process.

The invention provides an image sensor pixel unit with a polarization response characteristic light trapping structure and a preparation method of the image sensor pixel unit. The image sensor pixel unit comprises a semiconductor substrate, a multi-layer structure arranged on the substrate and a polarization response unit. The multi-layer structure comprises an anti-reflection layer, a filling and leveling layer and a micro-lens layer. The polarization response unit adopts an all-dielectric sub-wavelength grating based on a backscattering technology, and the polarization response unit and the deep trench isolation structure are synchronously formed by adopting the same process, so that photoelectric isolation between pixels is realized, and a polarization selection function is also realized. The anti-reflection layer is a multi-layer dielectric film stack, and interface reflection is effectively restrained. By optimizing the design of a polarization selection-transmission-convergence cooperative structure, polarization selection and light enhancement functions are integrated, an all-dielectric material system is adopted to be completely compatible with a CMOS (complementary metal oxide semiconductor) process, and quantum efficiency is remarkably improved while high-efficiency polarization detection is realized.

Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a deep trench via in a single diffusion break region; a frontside metal wire conductively connected to a top surface of the deep trench via; and a backside metal wire conductively connected to a bottom surface of the deep trench via, where the frontside metal wire and the backside metal wire are parallel to each other and perpendicular to the deep trench via. A method of forming the same is also provided.