819 results about "Deep trench" patented technology

The invention relates to the technical field of semiconductors, in particular to a device integrated with a deep trench isolation structure and a preparation method of the device. The preparation method comprises the steps that a semiconductor structure is provided, the semiconductor structure comprises a substrate, a gate material layer stacked on the surface of the substrate and a mask layer stacked on the gate material layer, and a functional element of the semiconductor device is formed in the substrate; forming a deep trench in the semiconductor structure, wherein the deep trench penetrates through the mask layer and the gate material layer and goes deep into the substrate; the deep trench is filled to form a deep trench isolation structure, the deep trench isolation structure comprises a filling structure, the filling structure is not higher than the surface of the substrate, and the material of the filling structure is a conductive non-metal material; patterning and etching the gate material layer to form a gate structure; and removing the mask layer. According to the invention, the preparation process of the deep trench isolation structure can be integrated into the standard process for preparing the gate structure of devices such as a BCD, the integration process of deep trench isolation is simplified, and the preparation cost is reduced.

An image sensor including a substrate having first and second surfaces, the second surface opposite the first surface; a first deep trench isolation layer in the substrate and defining pixel region groups, each pixel region group having a pair of pixel regions; a second deep trench isolation layer between the pair of pixel regions of each pixel region group; photoelectric conversion areas in each pixel region; and a lens array on the second surface and composed of two-dimensionally arranged microlenses. Each microlens having a shape, in plan view, with a long axis and a short axis, the short axis being substantially perpendicular to the long axis and shorter than the long axis. The microlenses covering each pixel region group, and a width of at least a first portion of the second deep trench isolation layer being smaller than a width of the first deep trench isolation layer.

The invention relates to the technical field of wellhead protection, and particularly discloses an oil production wellhead pressure self-adaption protection device which comprises a protection shell, an indicator lamp is installed on the protection shell, the protection shell comprises a shell body, and a main pipeline is arranged on the inner side of the shell body. A partition cavity, a pressurizing groove and a pressure sensing groove are sequentially formed in the outer side of the main pipeline from top to bottom, the partition cavity is a multi-angle deep groove, a partition assembly is installed in the partition cavity, one end of the partition assembly is installed on a hydraulic input pipe, and the hydraulic input pipes are communicated through hydraulic oil communication holes; by arranging the partition assembly, when blowout occurs, a pressure sensor collects pressure information, an electric signal controls a hydraulic assembly to extend, the sharp ends of triangular fault blocks pierce the interior of a pipeline, multi-direction pressure synchronous operation is formed among the four triangular fault blocks, the pipeline is rapidly cut off, and the pipeline cannot transport oil again; and rapid and complete plugging in the pipeline is realized.

An image sensor structure including a substrate, a pixel structure, and a deep trench isolation (DTI) structure is provided. The substrate includes a first side and a second side opposite to each other. The pixel structure includes a transfer transistor, a light sensing device, and a floating diffusion region. The transfer transistor includes a first gate. The first gate is disposed on the first side of the substrate. The light sensing device is disposed in the substrate and is located on one side of the first gate. The floating diffusion region is disposed in the substrate and is located on another side of the first gate. The DTI structure extends into the substrate from the second side of the substrate. The top-view pattern of the floating diffusion region does not overlap the top-view pattern of the DTI structure.

A trench cell structure having Schottky barriers and a preparation method thereof are provided. The trench cell structure includes a silicon substrate. A back metal layer is disposed on a back surface of the silicon substrate. The silicon substrate is heavily doped. A body region, a dielectric layer, and a front metal layer are sequentially disposed on a front surface of the silicon substrate from bottom to top. The drift region is lightly doped. Deep trench regions and a shallow trench region are defined on the body region at intervals. The deep trench regions and the shallow trench region include shielding electrodes and ohmic contact structures. The Schottky contact barriers are disposed between the deep trench regions and the shallow trench region, which reduces anode carrier injection efficiency when the trench cell structure is forwardly conducted, reduces reverse recovery charge, and reduces a reverse recovery time.

A semiconductor device is provided including a backside deep trench capacitor present in a deep trench device region and electrically connected to a source / drain region of a transistor and to a backside back-end-of-the-line (BEOL) structure. In some embodiments, the semiconductor device can also include a logic device region including at least one logic transistor that is located adjacent to the deep trench device region.

Disclosed herein are IC structures and devices that aim to mitigate proximity effects of deep trench vias. An example IC structure may include a device region having a first face and a second face, the second face being opposite the first face, and further include a conductive via extending between the first face and the second face, wherein the conductive via includes an electrically conductive material, and wherein a concentration of titanium at sidewalls of the conductive via is below about 1015 atoms per cubic centimeter.

Provided is a light detection sensor including: a substrate including a first surface and a second surface opposite to the first surface, wherein the second surface is a light incident surface; a deep trench isolator within a deep trench in the substrate and defining a pixel area; at least one recess into the pixel area from the second surface; a transparent electrode on the second surface and an inner surface of the at least one recess; and a first insulating film between the transparent electrode and the second surface and between the transparent electrode and the inner surface of the at least one recess.

A semiconductor device is provided. The semiconductor device includes a first region having a first gate structure disposed on a substrate and a second region having a second gate structure disposed on the substrate, a hard mask formed on the substrate, the first gate structure, and the second gate structure, a deep trench formed in the substrate between the first region and the second region, and formed to penetrate the hard mask to reach an inside of the substrate, and a planarized gap-fill insulating layer formed on the second gate structure and formed inside the deep trench. A topmost surface of the planarized gap-fill insulating layer and a topmost surface of the hard mask are coplanar.

Semiconductor structures and methods of forming the same are provided. A semiconductor structure of the present disclosure includes a contact feature disposed in a first dielectric layer, a first etch stop layer (ESL) over the contact feature and the first dielectric layer, a second dielectric layer over the first ESL, a second ESL over the second dielectric layer, a third dielectric layer over the second ESL, a third ESL over the third dielectric layer, a fourth dielectric layer over the third ESL, and a capacitor. The capacitor includes a bottom electrode layer continuously extending along a top surface of the fourth dielectric layer and vertically through the fourth dielectric layer, the third ESL, the third dielectric layer, the second ESL, the second dielectric layer, and the first ESL, an insulator layer disposed over the bottom electrode, and a top electrode layer disposed over the insulator layer.

An embodiment semiconductor device may include a semiconductor die; one or more redistribution layers formed on a surface of the semiconductor die and electrically coupled to the semiconductor die; and an active or passive electrical device electrically coupled to the one or more redistribution layers. The active or passive electrical device may include a silicon substrate and a through-silicon-via formed in the silicon substrate. The active or passive electrical device may be configured as an integrated passive device including a deep trench capacitor or as a local silicon interconnect. The semiconductor device may further include a molding material matrix formed on a surface of the one or more redistribution layers such that the molding material matrix partially or completely surrounds the active or passive electrical device.

The invention provides an image sensor pixel unit with a polarization response characteristic light trapping structure and a preparation method of the image sensor pixel unit. The image sensor pixel unit comprises a semiconductor substrate, a multi-layer structure arranged on the substrate and a polarization response unit. The multi-layer structure comprises an anti-reflection layer, a filling and leveling layer and a micro-lens layer. The polarization response unit adopts an all-dielectric sub-wavelength grating based on a backscattering technology, and the polarization response unit and the deep trench isolation structure are synchronously formed by adopting the same process, so that photoelectric isolation between pixels is realized, and a polarization selection function is also realized. The anti-reflection layer is a multi-layer dielectric film stack, and interface reflection is effectively restrained. By optimizing the design of a polarization selection-transmission-convergence cooperative structure, polarization selection and light enhancement functions are integrated, an all-dielectric material system is adopted to be completely compatible with a CMOS (complementary metal oxide semiconductor) process, and quantum efficiency is remarkably improved while high-efficiency polarization detection is realized.

Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a deep trench via in a single diffusion break region; a frontside metal wire conductively connected to a top surface of the deep trench via; and a backside metal wire conductively connected to a bottom surface of the deep trench via, where the frontside metal wire and the backside metal wire are parallel to each other and perpendicular to the deep trench via. A method of forming the same is also provided.

According to the image sensor manufacturing method based on the guided self-assembly technology, the guided self-assembly technology is applied to a deep groove patterning process on the back face of a wafer and is combined with a photoetching technology, so that compared with a traditional deep groove patterning process utilizing a PTD or NTD photoetching technology, the deep groove patterning process has the advantages that the deep groove patterning process is simplified; according to the invention, the resolution limit of the photoetching technology can be broken through, the pixel pitch can be reduced, the cost advantage and the pixel density can be improved, the pixel resolution can be greatly improved, the edge roughness of the deep trench isolation pattern of the pixel can be improved, and the signal crosstalk between the adjacent pixels can be reduced.

A semiconductor device and a method of forming the same are provided. The semiconductor device includes a substrate, a deep trench capacitor (DTC) having a portion within the substrate, and an interconnect structure over the DTC and the substrate. The interconnect structure includes a seal ring structure in electrical contact with the substrate, a first conductive via in electrical contact with the DTC, and a first conductive line electrically coupling the seal ring structure to the first conductive via.

The invention provides a deep trench capacitor and a preparation method thereof. The preparation method comprises the following steps: forming a deep trench in a substrate; forming a first dielectric layer on the inner wall of the deep trench; forming a second dielectric layer on the surface of a part of the first dielectric layer on the deep trench to reduce the opening of the deep trench, the second dielectric layer further extending to the surface of the first dielectric layer above the substrate; the deep trench is filled with polycrystalline silicon, the polycrystalline silicon seals an opening of the deep trench, the polycrystalline silicon forms an air gap in the lower part of the deep trench, and the polycrystalline silicon further extends to the surface of a second dielectric layer above the substrate; forming grooves in the second dielectric layer, the first dielectric layer and the polycrystalline silicon on the surface of the substrate; forming a side wall on the side wall of the groove, wherein the side wall covers part of the surface of the substrate in the groove; a first metal silicide layer is formed on the surface of the polycrystalline silicon, a second metal silicide layer is formed on the surface of the substrate in the groove, and the first metal silicide layer and the second metal silicide layer form an upper pole plate and a lower pole plate of the capacitor respectively.

The invention discloses a photoelectric detector and electronic equipment, the photoelectric detector comprises a substrate, a light reflection structure, a micropore diaphragm, a heightening layer, a lens structure and a deep groove isolation structure arranged around the substrate, the micropore diaphragm is provided with a light hole, the micropore diaphragm is located at a first side of a first surface of the substrate in a depth direction, and the light hole is located at a second side of the first surface of the substrate. The first surface is a surface for absorbing light into the substrate, and the first side is a side opposite to the interior of the substrate; the heightening layer and the lens structure are located on the first side of the micropore diaphragm in the depth direction. The heightening layer is located between the lens structure and the micropore diaphragm in the depth direction. The reflective structure is located on the first side of the second surface of the substrate, and the second surface is a surface opposite to the first surface in the depth direction. And the light absorption efficiency of the photoelectric detector can be improved.

The invention discloses an image sensor and a manufacturing method thereof, and belongs to the technical field of semiconductors. The photodiode is arranged in the substrate, and a first concave part is arranged in the photodiode; the deep trench isolation structure is arranged in the substrate, the deep trench isolation structure is located between the adjacent photodiodes, the deep trench isolation structure comprises a light-transmitting graphene layer, and the light-transmitting graphene layer is attached to the photodiodes; the first concave part is filled with a graphene layer to form the photoelectric response region, and the depth of the photoelectric response region is firstly increased and then decreased in the width direction of the photoelectric response region. According to the image sensor and the manufacturing method thereof provided by the invention, the light response range and efficiency of the image sensor can be improved.

The invention relates to the technical field of semiconductors, in particular to a device based on an advanced technological process and a preparation method thereof, and the method comprises the steps: providing an initial device structure which comprises a substrate and at least one interconnection layer located on the substrate, and forming a functional element of a semiconductor device in the substrate, the at least one interconnection layer is located between the top metal layer and the substrate, and the interconnection layer is prepared based on an advanced technological process and comprises a metal layer, a metal interconnection structure and a dielectric layer; forming a deep groove in the initial device structure, wherein the deep groove penetrates through the at least one interconnection layer and then goes deep into the substrate; and performing isolation material filling on the deep trench to form a filling material layer which fills the deep trench and is laminated on the at least one interconnection layer, and reusing an area, laminated on the at least one interconnection layer, of the filling material layer by a next interconnection layer adjacent to the at least one interconnection layer. According to the invention, the preparation process of the DTI can be integrated into the preparation process of the interconnection layer of devices such as the BCD, and the integration process is simplified.

The invention discloses a silicon capacitor structure and a manufacturing method thereof, and the method comprises the steps: bonding a first substrate with a second substrate, the first substrate comprises a first surface and a second surface which are opposite to each other, and the second surface is bonded with the second substrate; forming a deep trench in the first substrate; a first insulating layer and a polycrystalline silicon layer are formed in the deep groove, the polycrystalline silicon layer and the first substrate are separated by the first insulating layer, the first substrate serves as one electrode plate of the silicon capacitor structure, and the polycrystalline silicon layer serves as the other electrode plate of the silicon capacitor structure; and releasing the bonding between the first substrate and the second substrate. According to the silicon capacitor structure and the manufacturing method thereof provided by the invention, the first substrate and the second substrate are bonded, so that the probability of warping of the first substrate is reduced when the deep groove is etched in the first substrate.

The invention discloses a design method for reducing stress of a high-density deep trench capacitor and a deep trench capacitor structure. The method comprises the steps that at least one first groove is designed to be of a disconnected structure at the preset position of a groove array; through the disconnection structure, at least two second grooves and a gap between the two second grooves are formed at the original position of the first groove, and the gap is used for releasing stress. Optionally, a contact is designed within the gap. By segmenting the long groove and forming the stress release gap, the stress of the groove is effectively dispersed and reduced, the deformation of the groove is reduced, and the reliability of the device is improved. The contact pieces are additionally arranged at the gaps, parasitic parameters can be reduced, and the electrical performance is improved. The design method and the structure are suitable for manufacturing the high-density deep groove capacitor.

The invention provides a preparation method of a calculation unit, a calculation module and a processor, and the method comprises the steps: forming a blind hole in a slide glass, and forming a first electrode plate layer based on the blind hole; preparing a first metallization layer of the Josephson junction, and enabling the first metallization layer to be electrically connected with the first electrode plate layer; performing in-situ oxidation on the first metallization layer and the first electrode plate layer to form a first dielectric layer and a second dielectric layer; preparing a second metallization layer on the first dielectric layer to form a Josephson junction; forming a second electrode plate layer on the second dielectric layer to be electrically connected with the second metallization layer; performing medium filling on the blind hole wrapped by the second electrode plate layer to form a filling medium layer of the deep groove capacitor; and growing a conductive material to be respectively connected with the first metallization layer and the second metallization layer to form a first bonding pad and a second bonding pad of the calculation unit. According to the preparation method of the calculation unit, the calculation module and the processor provided by the invention, the preparation performance and reliability of the calculation unit are improved.

A semiconductor structure is provided. The semiconductor structure includes a substrate, a deep trench isolation (DTI), an interconnect structure, and a conductive pillar. The DTI is disposed in the substrate and the interconnect structure is disposed over the substrate. The conductive pillar extends from the interconnect structure toward the substrate and penetrates the DTI. A method of manufacturing the semiconductor structure is also provided.

The invention discloses a photoelectric detector and electronic equipment, the photoelectric detector comprises a substrate, a reflective structure, a multilayer film filter and a deep trench isolation structure arranged around the substrate, the multilayer film filter is a multilayer film structure formed by alternately stacking at least two film materials, the multilayer film filter is located on the first side of the first surface of the substrate in the depth direction, the first surface is the surface which absorbs light into the substrate, and the first side is the side back to the interior of the substrate; the multilayer film filter is used for light of a target detection wave band to pass through, and the target detection wave band is a detection wave band of the photoelectric detector; the reflective structure is located on the first side of the second surface of the substrate, and the second surface is a surface opposite to the first surface in the depth direction. According to the technical scheme, the light absorption efficiency of the photoelectric detector can be improved.

Provided is a hybrid pixel including a semiconductor substrate, a pixel circuit including at least one transfer transistor, a sensing circuit configured to detect movement of an object, and at least one photodiode having one end connected to the pixel circuit and another end connected to the sensing circuit, the semiconductor substrate having a first conductivity type, the semiconductor substrate including a photoelectric conversion area corresponding to the at least one photodiode, the photoelectric conversion area including a first area of a second conductivity type and a second area, the second area is physically separated from a second area of an adjacent hybrid pixel by a deep trench isolation area, and the semiconductor substrate including the deep trench isolation area.

In an embodiment, a semiconductor structure includes a substrate having a plurality of deep trenches oriented in a first direction and a second direction and a plurality of mesas interposed by the deep trenches. The semiconductor structure also includes a plurality of capacitor groups, wherein each of the capacitor groups includes a stack of conductive layers and node dielectric layers alternately disposed in the deep trenches and a first conductive plug disposed on a first layer of the conductive layers. The semiconductor structure also includes an isolation wall penetrating through the stack of the conductive layers and the node dielectric layers and into at least one of the mesas, the isolation wall being a close loop in a top view.

The invention discloses a backside illuminated image sensing structure, a sensor and a preparation method, and belongs to the field of semiconductors, the backside of a substrate is thinned to form a laminated photosensitive structure through a deposition process, a deep trench isolation structure is prepared on the laminated photosensitive structure, a first section of metal grating is prepared, and ions of VA group elements are injected to form a second section of metal grating; an inclined reinforced doping belt is formed; then preparing a second section of metal grating to obtain a complete metal grating, obtaining a back-illuminated image sensing structure, and then performing the processes of activation, preparation of a filter layer and the like to obtain a complete back-illuminated image sensor; according to the invention, the stacked photosensitive structure and the reinforced doping band are combined, so that the crosstalk effect is greatly reduced while the problem of doping damage to the substrate is solved, and the performance of the image sensor is improved.

The invention relates to the technical field of semiconductors, in particular to a semiconductor device structure and a preparation method thereof, and the method comprises the steps: providing a semiconductor structure which comprises a device substrate and a metal interconnection layer located on the device substrate, and the device substrate is provided with a functional element of a semiconductor device; forming a deep groove in the semiconductor structure, wherein the deep groove penetrates through the metal interconnection layer and then extends into the device substrate; and depositing an isolation material to form an isolation material layer which is laminated on the metal interconnection layer and is filled with the deep trench, forming a deep trench isolation structure in the region, filled with the deep trench, in the isolation material layer, and forming a passivation opening layer in the region, laminated on the metal interconnection layer, in the isolation material layer. According to the invention, the deep trench etching is carried out after the preparation process of the metal interconnection layer is completed, so that the DTI process is integrated into the back-end process of a BCD device and the like, and the device damage risk and the preparation cost caused by DTI integration are reduced.

The disclosure provides approaches for forming complementary metal-oxide-semiconductor image sensors having passivated sidewalls using plasma doping and low-temperature thermal processes. One approach may include a method may include providing a main body of a complementary metal oxide semiconductor image sensor, and forming a plurality of trenches in a back side of the main body, wherein each of the plurality of trenches includes a set of sidewalls and a base extending between the set of sidewalls. The method may further include performing a plasma treatment to form a doped layer along the base and along each of the set of sidewalls, performing a thermal treatment on the doped layer, and forming a dielectric layer over the doped layer following the thermal treatment.

A semiconductor device may include a substrate may include one or more hexagonal trenches extending into the substrate from a first side of the substrate. The device may include one or more deep trench capacitors (DTCs), each formed in a respective hexagonal trench. Each DTC may include a liner layer, formed within the respective hexagonal trench and in contact with the substrate. The DTC may include a first conductor layer including a first metal, the first conductor layer formed within the respective hexagonal trench and in contact with the liner layer. The DTC may include a dielectric layer including a dielectric material, the dielectric layer formed within the respective hexagonal trench and in contact with the first conductor layer. The DTC may include a second conductor layer including a second metal, the second conductor layer formed within the respective hexagonal trench and in contact with the dielectric layer.