467 results about "Deep trench" patented technology

A semiconductor device is provided including a backside deep trench capacitor present in a deep trench device region and electrically connected to a source / drain region of a transistor and to a backside back-end-of-the-line (BEOL) structure. In some embodiments, the semiconductor device can also include a logic device region including at least one logic transistor that is located adjacent to the deep trench device region.

The invention provides an image sensor pixel unit with a polarization response characteristic light trapping structure and a preparation method of the image sensor pixel unit. The image sensor pixel unit comprises a semiconductor substrate, a multi-layer structure arranged on the substrate and a polarization response unit. The multi-layer structure comprises an anti-reflection layer, a filling and leveling layer and a micro-lens layer. The polarization response unit adopts an all-dielectric sub-wavelength grating based on a backscattering technology, and the polarization response unit and the deep trench isolation structure are synchronously formed by adopting the same process, so that photoelectric isolation between pixels is realized, and a polarization selection function is also realized. The anti-reflection layer is a multi-layer dielectric film stack, and interface reflection is effectively restrained. By optimizing the design of a polarization selection-transmission-convergence cooperative structure, polarization selection and light enhancement functions are integrated, an all-dielectric material system is adopted to be completely compatible with a CMOS (complementary metal oxide semiconductor) process, and quantum efficiency is remarkably improved while high-efficiency polarization detection is realized.

According to the image sensor manufacturing method based on the guided self-assembly technology, the guided self-assembly technology is applied to a deep groove patterning process on the back face of a wafer and is combined with a photoetching technology, so that compared with a traditional deep groove patterning process utilizing a PTD or NTD photoetching technology, the deep groove patterning process has the advantages that the deep groove patterning process is simplified; according to the invention, the resolution limit of the photoetching technology can be broken through, the pixel pitch can be reduced, the cost advantage and the pixel density can be improved, the pixel resolution can be greatly improved, the edge roughness of the deep trench isolation pattern of the pixel can be improved, and the signal crosstalk between the adjacent pixels can be reduced.

The invention provides a deep trench capacitor and a preparation method thereof. The preparation method comprises the following steps: forming a deep trench in a substrate; forming a first dielectric layer on the inner wall of the deep trench; forming a second dielectric layer on the surface of a part of the first dielectric layer on the deep trench to reduce the opening of the deep trench, the second dielectric layer further extending to the surface of the first dielectric layer above the substrate; the deep trench is filled with polycrystalline silicon, the polycrystalline silicon seals an opening of the deep trench, the polycrystalline silicon forms an air gap in the lower part of the deep trench, and the polycrystalline silicon further extends to the surface of a second dielectric layer above the substrate; forming grooves in the second dielectric layer, the first dielectric layer and the polycrystalline silicon on the surface of the substrate; forming a side wall on the side wall of the groove, wherein the side wall covers part of the surface of the substrate in the groove; a first metal silicide layer is formed on the surface of the polycrystalline silicon, a second metal silicide layer is formed on the surface of the substrate in the groove, and the first metal silicide layer and the second metal silicide layer form an upper pole plate and a lower pole plate of the capacitor respectively.

The invention discloses an image sensor and a manufacturing method thereof, and belongs to the technical field of semiconductors. The photodiode is arranged in the substrate, and a first concave part is arranged in the photodiode; the deep trench isolation structure is arranged in the substrate, the deep trench isolation structure is located between the adjacent photodiodes, the deep trench isolation structure comprises a light-transmitting graphene layer, and the light-transmitting graphene layer is attached to the photodiodes; the first concave part is filled with a graphene layer to form the photoelectric response region, and the depth of the photoelectric response region is firstly increased and then decreased in the width direction of the photoelectric response region. According to the image sensor and the manufacturing method thereof provided by the invention, the light response range and efficiency of the image sensor can be improved.

In an embodiment, a semiconductor structure includes a substrate having a plurality of deep trenches oriented in a first direction and a second direction and a plurality of mesas interposed by the deep trenches. The semiconductor structure also includes a plurality of capacitor groups, wherein each of the capacitor groups includes a stack of conductive layers and node dielectric layers alternately disposed in the deep trenches and a first conductive plug disposed on a first layer of the conductive layers. The semiconductor structure also includes an isolation wall penetrating through the stack of the conductive layers and the node dielectric layers and into at least one of the mesas, the isolation wall being a close loop in a top view.

A semiconductor device may include a substrate may include one or more hexagonal trenches extending into the substrate from a first side of the substrate. The device may include one or more deep trench capacitors (DTCs), each formed in a respective hexagonal trench. Each DTC may include a liner layer, formed within the respective hexagonal trench and in contact with the substrate. The DTC may include a first conductor layer including a first metal, the first conductor layer formed within the respective hexagonal trench and in contact with the liner layer. The DTC may include a dielectric layer including a dielectric material, the dielectric layer formed within the respective hexagonal trench and in contact with the first conductor layer. The DTC may include a second conductor layer including a second metal, the second conductor layer formed within the respective hexagonal trench and in contact with the dielectric layer.

The present invention provides a super junction device and a forming method therefor. The super junction device comprises: a substrate, the substrate comprising a first surface; a deep trench located in the substrate from the first surface; an insulating layer located on the sidewall surface of the deep trench; a doped pillar located in the deep trench, the doped pillar having first dopant ions therein, wherein in the direction perpendicular to the surface of the substrate, the concentration of the first dopant ions in the doped pillar and the width of the deep trench have a self-adaptive matching relationship, and wherein the doped pillar comprises: a first polysilicon layer located on the surface of the insulating layer and the bottom surface of the deep trench, the first polysilicon layer having the first dopant ions therein; and a second polysilicon layer located on the surface of the first polysilicon layer, wherein a portion of the first dopant ions in the first polysilicon layer diffuses into the second polysilicon layer. The super junction device effectively increases the breakdown voltage, provides the possibility for further reduction of the device size, and has a wide range of applications.

The invention provides a planarization method for a large-line-width deep groove. The planarization method comprises the following steps: depositing a dielectric layer above a substrate slice with the large-line-width deep groove; the dielectric layer is ground, and chippings generated by grinding are reserved in the groove; and repeating the deposition and grinding steps until a flat surface is formed. The invention also provides a wafer comprising the groove processed by using the planarization method. According to the scheme, the cracking risk can be reduced, and the product performance index is improved.

The invention relates to the technical field of semiconductors, and discloses a semiconductor packaging structure and a preparation method thereof, and the structure comprises a silicon wafer which is provided with an upper surface and a lower surface which are opposite to each other; the at least one first mounting groove and the at least one second mounting groove are formed in the silicon wafer; the mounting groove is formed in one side of the upper surface of the silicon wafer; the interconnection silicon bridge is embedded into the first mounting groove; the first chip and the second chip are located above the interconnection silicon bridge; the adjacent first chip and second chip are connected with each other through an interconnection silicon bridge; the deep groove capacitor is embedded into the second mounting groove; the deep trench capacitor is connected with the first chip; the structure further comprises a plurality of through silicon vias penetrating through the silicon wafer, and the through silicon vias are located on the side portions of the interconnection silicon bridges and the side portions of the deep groove capacitors. The thermal expansion coefficient matching degree between the silicon wafer and the first chip and the second chip above the silicon wafer can be improved, warping is reduced, meanwhile, the response speed of the first chip and the response speed of the second chip are increased, the decoupling path of the first chip is shortened, and the power supply decoupling performance is improved.

Active semiconductor devices in an integrated circuit are provided lateral electrical isolation by surrounding narrow deep trench isolation regions that are merged at shared portions of the narrow deep trench isolation regions. A wide deep trench isolation region laterally surrounds the merged narrow deep trench isolation regions.

An image sensor comprising a photodiode and a forked deep trench isolation (DTI) structure is described. The photodiode is disposed within a semiconductor substrate having a first side and a second side opposite the first side. The forked DTI structure is configured to isolate the photodiode from adjacent photodiodes included in the image sensor. The forked DTI structure includes a trench disposed within the semiconductor substrate between the first side and the second side, a forked structure disposed within the trench and including a first prong, a second prong, and an intermediary portion to form a first cavity within the trench, and a second cavity disposed within the trench. The first cavity includes a first material and the second cavity includes a second fill material.

The invention discloses a monitoring method for an infrared detector chip, and relates to the technology of infrared detectors and semiconductors, and the method comprises the steps: etching a monitoring structure in a region outside a photosensitive chip region in the process of etching and preparing a mesa structure of a photosensitive chip of the infrared detector chip; measuring the etching depths of the mesa structure of the etched photosensitive chip area and each deep groove structure at different line widths, so as to form a data group based on the measured etching depths; a back thinning process is carried out on the mixed chip; and in the back thinning process, comparing the thinned and exposed deep groove structure with the formed data set so as to judge whether the back thinning process is abnormal or not. Through a focal plane preparation process link of specific marking and monitoring chip preparation and a process link of mixing chip back thinning residual thickness and process quality, the process monitoring difficulty is reduced, the monitoring operability is improved, and the problem of tabletop preparation depth monitoring is solved.

An embodiment semiconductor device may include a semiconductor die; one or more redistribution layers formed on a surface of the semiconductor die and electrically coupled to the semiconductor die; and an active or passive electrical device electrically coupled to the one or more redistribution layers. The active or passive electrical device may include a silicon substrate and a through-silicon-via formed in the silicon substrate. The active or passive electrical device may be configured as an integrated passive device including a deep trench capacitor or as a local silicon interconnect. The semiconductor device may further include a molding material matrix formed on a surface of the one or more redistribution layers such that the molding material matrix partially or completely surrounds the active or passive electrical device.

A Deep Trench Isolation (DTI) structure is disclosed. A DTI structure formed in a semiconductor substrate. The DIT structure includes an isolation layer and filling material. The isolation layer is formed from a p-type semiconductor material. Sidewall portions of the isolation layer are in contact with the semiconductor substrate. A bottom portion of the isolation layer is in contact with a connection feature, which is connected to an interconnect structure and configured to apply a bias to the isolation layer of the DTI structure to achieve a controllable passivation in the semiconductor substrate.

The invention discloses a GaN power electronic device capable of realizing CMOS (complementary metal oxide semiconductor) monolithic integration. The device comprises a substrate, an AlN buffer layer, a first i-GaN channel layer, a p-GaN buried layer, a second i-GaN channel layer, an AlN insertion layer, an AlGaN barrier layer and a p-GaN cap layer from bottom to top, the deep groove for device isolation extends into the AlN buffer layer; the p-GaN cap layer on the AlGaN barrier layer is partially removed, a source electrode and a drain electrode are transversely and sequentially arranged on the AlGaN barrier layer, and a gate electrode is arranged on the reserved p-GaN cap layer; a passivation layer covers the AlGaN barrier layer and the p-GaN cap layer, and interconnection metal is arranged on the source electrode, the drain electrode and the gate electrode, so that the GaN power electronic device with a p-GaN / AlGaN / AlN / i-GaN / p-GaN / i-GaN / AlN structure is formed. According to the invention, not only are the characteristics of high voltage resistance, low power consumption and excellent thermal conductivity and can be applied to high-voltage and high-power application scenarios, but also an enhanced p-channel GaN FET device can be developed based on the structure, a CMOS monolithic integrated phase inverter can be prepared, and monolithic integration of the GaN-based semiconductor device and a driving circuit thereof is realized.

Aspects provide a device comprising: a substrate doped to form a first well; a first deep trench etched in the substrate; a dielectric in the first deep trench; a first conductor within the dielectric in the first deep trench and biased to create a first depletion region in the substrate proximate the first deep trench, wherein the substrate forms a bottom electrode of a first deep trench isolation varactor and the conductor in the first deep trench forms a top electrode of the first deep trench isolation varactor; a sense electrode operable to become electrically charged when interacting with an ionized fluid, wherein the sense electrode is operable to electrically charge the first deep trench isolation varactor; and a fluid property measurement circuit operable to determine a change in the capacitance of the first deep trench isolation varactor and output a fluid property signal.

The application provides a high-reliability silicon capacitor manufacturing method, comprising the following steps: deep groove etching of a silicon substrate; depositing a dielectric layer on the surface of the deep groove and the surface of the silicon substrate outside the deep groove; filling polycrystalline silicon in the deep groove and on the surface of the silicon substrate outside the deep groove; removing the dielectric layer and the polycrystalline silicon on the surface by using a CMP process; depositing a layer of silicon oxide with a thickness not less than 0.5 microns on the surface; etching a through hole; depositing a layer of metal as an upper electrode on the surface; and depositing a layer of metal as a lower electrode on the bottom of the silicon substrate. The application grinds all the dielectric and poly layers on the plane by using the CMP process, and then deposits a layer of thick silicon oxide, which can significantly improve the service life of the silicon capacitor, significantly improve the working voltage under the same working condition, enhance the reliability, reduce the poly etching step, save the mask plate, reduce the photoetching, and save the cost.

A deep trench structure may be formed to include a doped polysilicon core and dielectric isolation layers on the sidewalls of the doped polysilicon core. The deep trench structure may be provided as a deep trench isolation structure that laterally surrounds transistors in a semiconductor device. Additionally and / or alternatively, the deep trench structure may be included in a high-voltage transistor as a vertical drain region that extends into a semiconductor layer of a semiconductor device.

Deep trench capacitors (DTCs) employing bypass metal trace signal routing supporting signal bypass routing, and related integrated circuit (IC) packages and fabrication methods are disclosed. The DTC includes an outer metallization layer (e.g., a redistribution layer (RDL)) to provide an external interface to the DTC. In exemplary aspects, to make available signal routes that can extend through a DTC, an outer metallization layer of the DTC includes additional metal interconnects. These additional metal interconnects are not coupled the capacitors in the DTC. These additional metal interconnects are interconnected to each other by metal traces (e.g., metal lines) in the outer metallization layer of the DTC to provide bypass signal routes through the DTC. This is opposed to signal paths in a package substrate in which the DTC is coupled or embedded having to be routed around the DTC in the package substrate.

The application discloses a trench gate power MOSFET device with anti-single event burnout reinforcement and a preparation method thereof, which comprises the following steps: etching a deep trench at a center position of the device and forming a P-type shielding area and depositing N-type polysilicon; forming a current expansion layer between a boron-doped area and an N-type drift area by means of ion implantation; and forming a P-type high-concentration doped area and an N-type high-concentration source area above the boron-doped area by means of ion implantation. According to the technical scheme, the internal electric field of the device can be modulated, the electric field distribution on the heavy ion incident track is smoother, the instantaneous power density of the device is reduced, the local high temperature is reduced, the trench oxide layer is protected from high temperature, the forward conduction capability of the device is improved, and the anti-single event burnout capability of the device can be remarkably improved without sacrificing the basic electrical characteristics of the device.

An image sensor pixel includes a light sensor disposed in a semiconductor substrate. To provide isolation to reduce inter-pixel crosstalk and increase a modulation transfer function (MTF), an etch stop layer is disposed on a first surface of a semiconductor substrate, and a deep trench is etched on a second surface opposite the etch stop layer disposed on the first surface. Etching is stopped at the etching stop layer, and the bottom surface of the etching deep groove is the surface of the etching stop layer. At least one dielectric layer may be deposited on sidewalls and a bottom surface of the deep trench, and the remainder of the deep trench is filled with a metal or other opaque material. An image sensor pixel includes a semiconductor substrate and a photodiode disposed therein, and a metal barrier passing through the semiconductor substrate and arranged to provide optical isolation of the photodiode.

The invention provides a semiconductor structure forming method and a semiconductor structure. The forming method comprises the following steps: forming a substrate, and forming a first ion implantation region on the surface of the substrate; and forming a first epitaxial layer on the substrate, and forming a second ion implantation region on the surface of the first epitaxial layer. A second epitaxial layer is formed on the first epitaxial layer. Forming a second contact hole, enabling the second contact hole to penetrate through the second epitaxial layer along the stacking direction of the second epitaxial layer so as to expose the second ion implantation region, and forming a first contact hole, enabling the first contact hole to penetrate through the second epitaxial layer and the first epitaxial layer along the stacking direction of the second epitaxial layer so as to expose the first ion implantation region. A conductive interconnection layer is formed, and the conductive interconnection layer is located in the first contact hole and the second contact hole and connected with the first ion implantation region and the second ion implantation region, so that the substrate and the first epitaxial layer are electrically conducted through the conductive interconnection layer. The problem that the contact resistance is high when the deep groove contact hole is optimized can be solved.

The preparation method of the semiconductor structure comprises the following steps: firstly, providing a silicon substrate; and then a patterned mask layer is formed on the silicon substrate, the patterned mask layer comprises a first pattern located in the middle area of the silicon substrate and a second pattern located in the annular area on the edge of the silicon substrate, and the width of the annular area covered by the second pattern is larger than 5 mm. And etching the silicon substrate by taking the patterned mask layer as a mask to form a deep trench. The patterned mask layer is then removed. And then filling epitaxial material in the deep trench. And finally, carrying out surface planarization treatment on the silicon substrate to remove the excessive epitaxial material on the surface of the silicon substrate. According to the preparation method of the semiconductor structure, the patterned mask layer is formed in the annular area, with the width larger than 5 mm, of the edge of the silicon substrate, and damage to the edge area in the etching and epitaxial filling process is avoided. Therefore, the stress resistance of the edge of the silicon substrate is remarkably enhanced, and wafer cracking or dark damage in the subsequent chemical mechanical polishing process is prevented, so that the overall integrity and reliability of the silicon substrate are improved.

The invention discloses a non-polishing low-loss coupling optical fiber array adaptive to a deep silicon etching photon chip, a deep silicon etching photon chip coupling assembly and a method, and belongs to the technical field of silicon photon integration. The device comprises an optical fiber array main body, a V-shaped groove substrate and a special-shaped cover plate, the special-shaped cover plate is attached to the upper surface of the V-shaped groove substrate, an avoiding groove is formed in the position, corresponding to a deep silicon etching area of the end face of the chip, of the special-shaped cover plate, and the depth of the avoiding groove is not smaller than the total height of a residual step on the end face of the chip and a deep groove protruding structure so as to eliminate mechanical interference. The tail end of the optical fiber is positioned in the V-shaped groove, and the light-emitting end face is parallel and tightly butted with the end face of the chip. The customized avoiding groove is integrated in the cover plate, direct, lossless and low-loss coupling of the optical fiber array and the deep silicon etching silicon optical chip with the composite three-dimensional morphology end face can be achieved without extending the optical fiber, removing a bottom cover or polishing the end face of the chip, the integrity of the end face of the chip is effectively protected, and the coupling precision and the device yield are improved.

The application discloses an array type photoelectric tweezers chip and a manufacturing method thereof, and belongs to the technical field of micro-nano manipulation and semiconductor devices. The chip comprises a substrate layer, a transistor array structure, a liquid phase manipulation cavity and an upper plate structure. The transistor array structure comprises a plurality of NPN type or PNP type photoelectric transistors arranged in a horizontal array, and a deep trench isolation structure extending longitudinally into the substrate layer is arranged between adjacent units. The light receiving surface of each photoelectric transistor unit faces the liquid phase manipulation cavity, and is not covered by an upper light shielding metal layer. The virtual electrode working mode is adopted, a localized dielectrophoresis electric field is generated through light irradiation, and the accurate capture and manipulation of micro-nano particles in the liquid phase cavity are realized. The application solves the problems of low integration of a traditional optical tweezers chip, obstruction of light transmission caused by a metal light shielding layer and the like, has the advantages of compact structure, sensitive response, programmable array and the like, and can be widely applied to the fields of biological cell manipulation, nano material assembly and micro-fluidic analysis.

The invention provides an etching method and semiconductor process equipment, relates to the technical field of semiconductors, and is designed for solving the problem that the roughness of the side wall of a deep groove structure obtained by etching through an etching process provided by the related technology is large. The etching method comprises the following steps: providing a substrate; performing a photoetching step and a first etching step on the substrate to form a first groove in the substrate; performing normal-temperature oxidation to form a protection layer covering the first groove; removing the protection layer on the bottom wall of the first groove; and performing a second etching step on the first groove to form a second groove on the substrate. The invention can reduce the roughness of the side wall.

Deep trench isolation structures for high voltage semiconductor-on-insulator devices are disclosed herein. An exemplary deep trench isolation structure surrounds an active region of a semiconductor-on-insulator substrate. The deep trench isolation structure includes a first insulator sidewall spacer, a second insulator sidewall spacer, and a multilayer silicon-comprising isolation structure disposed between the first insulator sidewall spacer and the second insulator sidewall spacer. The multilayer silicon-comprising isolation structure includes a top polysilicon portion disposed over a bottom silicon portion. The bottom polysilicon portion is formed by a selective deposition process, while the top polysilicon portion is formed by a non-selective deposition process. In some embodiments, the bottom silicon portion is doped with boron.

The invention discloses a medium-voltage transistor with a fin-shaped structure and a manufacturing method thereof, and the medium-voltage transistor with the fin-shaped structure comprises a substrate, a fin-shaped structure which protrudes out of one surface of the substrate, a gate structure which stretches across the fin-shaped structure, a source electrode which is arranged at one side of the gate structure and is embedded in the fin-shaped structure, a drain electrode is disposed on the other side of the gate structure and embedded in the fin-shaped structure. A second deep trench insulator is embedded in the substrate and adjacent to the source electrode and the drain electrode. An insulating structure is embedded in the fin-shaped structure below the gate structure. Wherein the insulating structure comprises a first deep trench insulator and a first shallow trench insulator enlarged from the side wall of the first deep trench insulator to the source electrode.

The present invention relates to a vertically-charge-transferring pixel sensor (VPS) and methods of manufacture and operation thereof. In the VPS, deep trench isolation (DTI) structures and shallow trench isolation (STI) structures in a substrate contain deep trench electrodes and shallow trench electrodes, respectively. In a light sensing operation, a positive bias voltage can be applied between the substrate and the deep and shallow trench electrodes to raise a potential barrier at boundaries of the DTI and STI structures and the substrate. This reduces the likelihood of photoelectrons being captured at the boundaries, thus reducing loss of photoelectrons and contributing to enhanced quantum efficiency. In addition, in the STI structures, the shallow trench electrodes may be offset toward light sensing regions beside the STI structures. In this way, a voltage applied to the shallow trench electrodes has a greater impact on potentials in the light sensing regions than on potentials in charge readout regions, thus additionally reducing loss of photoelectrons and minimizing the influence on MOS transistors in the charge readout regions.