1274 results about "Deep trench" patented technology

The invention discloses a semiconductor structure manufacturing method and a semiconductor structure, and the manufacturing method comprises the steps: carrying out the periodic cycle etching of a preset number of times on a substrate through employing an etching technology, forming a first intermediate structure on the substrate, and carrying out the first processing of the first intermediate structure, including employing a first gas and a second gas, removing a part of thickness of the passivation layer deposited on the side wall of the first intermediate structure, and reacting with the substrate material which exists on the side wall and is exposed on the surface of the convex part to generate a reaction product layer; and removing the reaction product layer by using a third gas and a fourth gas so as to remove at least part of the lug boss, and repeatedly executing the etching process and the first processing process until a high aspect ratio etching structure is formed on the substrate. According to the method, the etching process and the side wall processing technology are organically combined, the etching rate and the side wall quality are balanced through alternate circulation, and deep silicon etching with the higher aspect ratio and the smaller nanoscale size can be achieved.

The invention discloses an MEMS device architecture, which comprises a cap layer, a device layer and a substrate layer, the cap layer is bonded with the device layer, the bonded whole is bonded with the substrate layer, the cap layer is manufactured based on a first silicon substrate, the bottom of the cap layer is provided with a cavity structure, and the cap layer is internally provided with a high-deep groove structure. A silicon dioxide film is arranged on the groove wall of the high-deep groove structure, polycrystalline silicon is deposited and filled in the high-deep groove structure, and a silicon dioxide layer is arranged on the upper surface of the first silicon substrate; the device layer is manufactured based on an SOI wafer and comprises a first silicon structure layer composed of top layer silicon, a buried oxide layer and a second silicon structure layer composed of back substrate silicon. The substrate layer comprises a second silicon substrate, a bottom layer cavity is formed in the top face of the second silicon substrate, and exhaust holes are formed in the bottom face of the second silicon substrate. According to the method, deep groove etching, polycrystalline silicon groove filling and bonding technologies are combined, advanced materials such as the SOI wafer and the polyimide layer are utilized, and excellent signal isolation and flexibility of various MEMS IMU applications are achieved.

The invention provides a preparation method of a stacked transistor, the stacked transistor and a semiconductor device. The method comprises the steps of performing primary etching on a semiconductor substrate to form a stack structure, wherein the stack structure comprises an active structure and a first sacrificial layer; forming a pseudo gate structure covering the stacked structure in the gate region; etching the stack structure which is not covered by the pseudo gate structure to form a first deep groove; epitaxially growing a first source drain structure in the first deep groove based on the first active structure in the gate region; removing the pseudo gate structure and the first sacrificial layer to expose the active structure in the gate region; depositing a gate dielectric material on the exposed active structure to form a gate dielectric layer; depositing a metal material on the first gate dielectric layer to form a first gate electrode layer; reversing and removing the semiconductor substrate; epitaxially growing a second source drain structure in the first deep groove based on a second active structure in the gate region; and depositing a metal material on the second gate dielectric layer to form a second gate electrode layer.

To provide an image sensor in which the conversion gain (CG) is improved, the arrangement efficiency and size of pixel transistors are increased, and a metal wiring layer is reduced.SOLUTION: An image sensor of the present invention includes a pixel including two photodiodes (PDs) disposed on both sides in a first direction, a deep trench isolation (DTI) structure including an internal DTI structure that separates the two PDs in the pixel from each other and extends in a second direction that is orthogonal to the first direction and an external DTI structure that separates the pixels from each other and extends in the first direction or the second direction, a floating diffusion (FD) region that is disposed between a central part of the external DTI structure extending in the first direction and an edge of the internal DTI structure, and a transmission gate (TG) disposed adjacent to the FD region and disposed at least one by one in the PD. The two PDs in the pixel share the FD region.SELECTED DRAWING: Figure 2

The invention discloses a manufacturing method of a groove, a semiconductor device and a manufacturing method of the semiconductor device, and relates to the technical field of semiconductors, and the manufacturing method comprises the steps: providing a substrate, forming a first mask layer on the substrate, and etching the first mask layer by taking a photomask as a mask, so that the first mask layer covers the substrate of a first groove region, forming a second mask layer on the substrate, etching the second mask layer to enable the second mask layer to expose the first mask layer and the substrate in the second groove region, etching the substrate in the second groove region by taking the first mask layer and the second mask layer as masks to form a relatively shallow second groove, and etching the first mask layer to form a relatively shallow second groove; according to the method, the substrate of the first trench region and the substrate of the second trench region are exposed by the second mask layer, and the substrate of the first trench region and the substrate of the second trench region are etched by taking the second mask layer as a mask to form a deeper second trench and a shallower first trench, so that a shallow trench and a deep trench can be manufactured by adopting one photomask, and the manufacturing cost can be further reduced.

The invention discloses a cellular structure of a shield gate trench MOSFET and a manufacturing method thereof, the cellular structure of the shield gate trench MOSFET comprises a substrate, a drift region and an interlayer dielectric layer, the drift region is provided with a deep trench, and the deep trench is internally provided with a shield gate, an intermediate oxide layer and a control gate; a body region and a source region are formed at the upper part of the drift region through injection, the interlayer dielectric is provided with a source electrode contact hole which penetrates through the source region and extends into the body region, and highly doped contact regions are formed on the side wall and the bottom of the source electrode contact hole through injection; and a charge balance region is formed below the source electrode contact hole through high-energy ion implantation. According to the invention, by arranging the charge balance region, the lateral depletion of the shield gate to the adjacent drift region can be enhanced when the shield gate trench MOSFET device is in a reverse bias state, the specific on-resistance of the device is reduced, the depletion of the drift region of the epitaxial layer is accelerated, and the reliability and radiation resistance of the device are improved.

The invention relates to the technical field of semiconductors, in particular to a device integrated with a deep trench isolation structure and a preparation method of the device. The preparation method comprises the steps that a semiconductor structure is provided, the semiconductor structure comprises a substrate, a gate material layer stacked on the surface of the substrate and a mask layer stacked on the gate material layer, and a functional element of the semiconductor device is formed in the substrate; forming a deep trench in the semiconductor structure, wherein the deep trench penetrates through the mask layer and the gate material layer and goes deep into the substrate; the deep trench is filled to form a deep trench isolation structure, the deep trench isolation structure comprises a filling structure, the filling structure is not higher than the surface of the substrate, and the material of the filling structure is a conductive non-metal material; patterning and etching the gate material layer to form a gate structure; and removing the mask layer. According to the invention, the preparation process of the deep trench isolation structure can be integrated into the standard process for preparing the gate structure of devices such as a BCD, the integration process of deep trench isolation is simplified, and the preparation cost is reduced.

The invention discloses a manufacturing method of an image sensor and the image sensor, and relates to the technical field of semiconductor manufacturing, and the manufacturing method comprises the steps: forming a first stacked structure on the surface of a substrate; forming a deep trench isolation structure in the first laminated structure to isolate the first laminated structure to form a plurality of photodiode regions; forming a plurality of doped regions in the photodiode region; wherein the doping elements are diffused from the surface of the photodiode region to the interior of the photodiode region to form a plurality of doping regions, the plurality of doping regions extend from the surface of the photodiode region to the interior of the photodiode region, and the extension depths of different doping regions are different, so that the doping regions with different layer structures are formed.

Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a deep trench via in a double diffusion region between a first dummy metal gate and a second dummy metal gate; a frontside metal wire conductively connected to a top surface of the deep trench via through a frontside via; and a backside metal wire conductively connected to a bottom surface of the deep trench via through a backside via and a backside contact, where the frontside metal wire and the backside metal wire are not vertically aligned but parallel to each other, and directions of the frontside and backside metal wires are orthogonal to a length direction of the deep trench via. A method of forming the same is also provided.

Technologies for components embedded in a substrate core are disclosed. In one embodiment, power components such as deep trench capacitors and multi-layer ceramic capacitors (MLCCs) are disposed in a cavity defined in a substrate core for a circuit board of an integrated circuit package, such as a processor. The power components are stacked on top of each other, allowing for the stack of power components to match the height of the substrate core, even when the height of the individual power components is less than the height of the substrate core. Configuring the power components in this manner can provide mechanical stability to the power components and substrate core and provide power to a semiconductor die mounted on the circuit board.

The problem of forming a deep trench isolation structure suitable for photodetectors with small pitch is solved by a process in which a grid of trenches is etched from the front side using high energy plasma followed by annealing. The trenches are filled with an oxide followed by etching to recess the oxide. The trench recesses are filled with semiconductor to form a grid-shaped semiconductor structure. After FEOL processing, BEOL processing, attachment to a second substrate, and thinning from the back side, an etch removes the oxide from the back side. The etch stops on the grid-shaped semiconductor structure. The trenches are then lined and filled from the back side. The front side etch allows the trenches to be made narrow and with highly vertical sidewalls. Lining and filling the trenches from the back side provides good optical and electrical isolation.

Aspects of the disclosed invention provide a semiconductor structure for a semiconductor chip with two layers of semiconductor devices, where the first layer of semiconductor devices directly contacts a semiconductor substrate and connects to a first frontside interconnect wiring. The first layer of semiconductor devices includes at least one trench semiconductor device such as a deep trench capacitor. The first frontside interconnect wiring is electrically connected to the second frontside interconnect wiring by one or more joined metal plugs. The second layer of active devices connects to a backside power delivery network and the second frontside interconnect wiring. The semiconductor chip with two layers of semiconductor devices that are bonded together provides one layer of semiconductor devices capable of being in a portion of the semiconductor substrate and a second layer of semiconductor devices with a backside power delivery network.

The invention relates to the technical field of semiconductor integrated circuit manufacturing, in particular to a manufacturing method of a semiconductor device. Comprising the following steps: providing a semiconductor substrate; forming a deep trench isolation structure in the isolation region, wherein the upper surface of the deep trench isolation structure is higher than the upper surface of the active region by a specific height; sequentially performing first etching and second etching on the active region of the high-voltage device region and the edge part, close to the active region, of the deep trench isolation structure of the high-voltage device region; etching the edge part, close to the active region, of the deep trench isolation structure of the high-voltage device region after the first etching and the second etching, and reducing the height difference between the upper surface of the active region of the high-voltage device region and the upper surface of the edge part, close to the active region, of the deep trench isolation structure of the high-voltage device region; and depositing to form a high-voltage oxide layer, wherein the high-voltage oxide layer covers the upper surface of the active region of the high-voltage device region and the upper surface of the edge part, close to the active region, of the deep trench isolation structure of the high-voltage device region.

The invention relates to a deep trench isolation structure and a preparation method thereof, and aims to solve the problems that the height difference of an etching stop layer is too large and the processing precision of a deep trench is insufficient in the prior art. According to the method, the sacrificial layer is deposited on the surface of the substrate after the shallow groove is machined, the sacrificial layer is used for protecting a non-target area in the deep groove machining process, and high-precision machining of the deep groove is achieved through the multi-stage etching technology. In the first stage, sacrificial layer materials in a deep groove region are removed step by step, and a target region is exposed; and in the second stage, the mask effect of the sacrificial layer is utilized to accurately etch to the target depth, and meanwhile, the side wall form is optimized. By reducing the height difference of the etching stop layer, the uniformity of the filling material is improved, and the smoothness of chemical mechanical polishing is improved. The method has the functions of mask protection and depth regulation and control, simplifies the process steps, reduces the manufacturing cost, is suitable for manufacturing high-density integrated circuits and power devices, and has excellent processing effect and industrial applicability.

Technologies for components embedded in a substrate core are disclosed. In one embodiment, power components such as deep trench capacitors are disposed in a cavity defined in a substrate core for a circuit board of an integrated circuit package, such as a processor. The power components are stacked on top of each other, allowing for the stack of power components to match the height of the substrate core, even when the height of the individual power components is less than the height of the substrate core. The stack may include, e.g., three or more power components. Through-silicon vias in some or all of the power components can allow for connections through one power component to another. Configuring the power components in this manner can provide mechanical stability to the power components and substrate core and provide power to a semiconductor die mounted on the circuit board.

Some embodiments relate to a CMOS image sensor disposed on a substrate. A plurality of pixel regions comprising a plurality of photodiodes, respectively, are configured to receive radiation that enters a back-side of the substrate. A boundary deep trench isolation (BDTI) structure is disposed at boundary regions of the pixel regions, and includes a first set of BDTI segments extending in a first direction and a second set of BDTI segments extending in a second direction perpendicular to the first direction to laterally surround the photodiode. The BDTI structure comprises a first material. A pixel deep trench isolation (PDTI) structure is disposed within the BDTI structure and overlies the photodiode. The PDTI structure comprises a second material that differs from the first material, and includes a first PDTI segment extending in the first direction such that the first PDTI segment is surrounded by the BDTI structure.

The invention relates to a deep and shallow trench isolation structure and process, and the process comprises the steps: providing a substrate, and depositing a multifunctional layer on the surface of the substrate; forming a first pattern on a partial region of the multifunctional layer through a photoetching technology; etching for the first time by using the first pattern, removing a part of material of the multifunctional layer and etching the substrate to form a shallow trench structure, and removing the first pattern mask; forming a second pattern on the non-etched region through the photoetching technology again; performing second etching by using the second pattern, removing the multifunctional layer in an unetched region to the surface of the substrate, and removing the second pattern mask; and under the protection effect of the multifunctional layer, carrying out third etching on the exposed region, and processing the exposed region to a designed depth to form a shallow trench structure and a deep trench structure with different depths. According to the invention, the height difference of the etching stop layer after STI etching in different areas is eliminated, so that the subsequent oxide filling and chemical mechanical polishing processes are easy to control, and the quality of the device is improved.

The invention discloses a deep trench isolation structure and a manufacturing process method thereof, an injection layer of a second conduction type is arranged on a substrate of a first conduction type, and a deep trap of the second conduction type is arranged on the injection layer; the surface layer of the deep well is provided with a shallow trench isolation structure, and the outer side of the shallow trench isolation structure is provided with a well region of a second conductive type; a deep trench is formed in the shallow trench isolation structure through etching; filling materials which are filled in sections are arranged in the deep grooves; wherein the lower part in the deep trench is filled with a silicon oxide material, and the upper part in the deep trench is filled with a polycrystalline silicon material; filling in the deep trench is divided into two sections of composite filling made of different materials, the portion located on the lower portion of the deep trench is made of silicon oxide, the portion located on the upper middle portion of the deep trench is made of polycrystalline silicon, the structure is further optimized, the bottom of DTI polycrystalline silicon is shortened to the position below an injection layer, the bottom of the DTI polycrystalline silicon can pull up a high peak electric field in a depletion region, and therefore the reliability of the deep trench is improved. And the breakdown voltage of the device is improved.

A trench capacitor manufacturing method is provided. The method includes forming a deep trench in a wafer, forming a trench capacitor structure including a plurality of dielectric films and a plurality of conductive layers in the deep trench; determining if the wafer has a tensile stress based on the forming of the trench capacitor structure; performing a high temperature heat treatment to the trench capacitor structure to change a form of the wafer to a direction that offsets the tensile stress; forming an inter-layer insulating film on the trench capacitor structure; and forming a metal interconnect on the inter-layer insulating film.

An image sensor including a substrate having first and second surfaces, the second surface opposite the first surface; a first deep trench isolation layer in the substrate and defining pixel region groups, each pixel region group having a pair of pixel regions; a second deep trench isolation layer between the pair of pixel regions of each pixel region group; photoelectric conversion areas in each pixel region; and a lens array on the second surface and composed of two-dimensionally arranged microlenses. Each microlens having a shape, in plan view, with a long axis and a short axis, the short axis being substantially perpendicular to the long axis and shorter than the long axis. The microlenses covering each pixel region group, and a width of at least a first portion of the second deep trench isolation layer being smaller than a width of the first deep trench isolation layer.

Structures for a high-voltage field-effect transistor that include a deep trench isolation region and methods of forming such structures. The structure comprises a semiconductor substrate, a semiconductor layer on the semiconductor substrate, and a doped layer between the semiconductor layer and the semiconductor substrate. The structure further comprises a trench isolation region including a metal layer that extends through the semiconductor layer and the doped layer into the semiconductor substrate.

The invention provides a manufacturing method of a semiconductor structure, which is applied to the technical field of semiconductors. According to the invention, before the second conductive layer is formed, the ion implantation process is carried out on the substrate, so that the first ion implantation region is formed in the substrate below the deep trench, and the second ion implantation region is synchronously formed in the substrate at two sides of the deep trench, thereby saving an ion implantation process. The conduction type of the first ion implantation region (located between the control gate and the drain electrode) is opposite to that of the substrate, so that carriers can be mutually depleted, and the purpose of increasing a depletion region and the breakdown voltage is achieved; and then a second conductive layer is formed and deposited in the deep trench, and a control gate in a special shape is formed by combining a first conductive layer on the side wall of the deep trench, so that the purposes of reducing the overlapping area between the control gate and a drain electrode, reducing the gate-drain capacitance of the power semiconductor device, reducing the switching loss and finally improving the switching speed are achieved.

Various embodiments of the utility model relate to a semiconductor device, the semiconductor device comprises a plurality of photodiode doped regions formed in a substrate and a deep trench isolation (DTI) structure formed in the substrate, the DTI structure separates the photodiode doped regions, and the DTI structure comprises a first filling material defining an air gap therein. The first filling material comprises a top, a side wall and a bottom. The semiconductor device also includes a first isolation layer surrounding and contacting the top, sidewalls, and bottom of the first fill material.

The invention relates to a machining method for large-diameter deep-blind-hole alloy structural steel complex-shape deep groove quenched hardware. The problems that the large-diameter deep-blind-hole alloy structural steel complex-shape deep groove quenched hardware is high in machining precision, long in period, high in cost and prone to causing part scrapping are solved by means of various special cutters and clamps in different working procedures. A large-hole and deep-hole adjustable U drill, a large-hole and deep-hole bottoming drill, a numerical control vibration reduction cutter bar special for a deep blind hole double-tool-bit endoscope, a rapid dividing device and a special inner cooling quenching device are used for solving the machining problem of large-diameter deep-hole alloy structural steel complex-shape deep groove quenching hardware. The roundness of a deep hole of a machined workpiece is smaller than or equal to 0.015 mm, the symmetry degree of six-equal-division grooves is smaller than or equal to 0.03 mm, and the technical requirements of high-precision complex parts are completely met.

The invention discloses a 950V super-junction MOS device with a deep groove filling structure and a manufacturing method of the 950V super-junction MOS device. The 950V super-junction MOS device is provided with polycrystalline silicon deposition with a discontinuous structure and additionally provided with an independent gate source ESD protection area, the whole device is subjected to secondary epitaxy through an N-type substrate, and a plurality of functional layers are expanded according to the optimal condition. According to the invention, charge imbalance caused by unequal groove width due to an etching angle is relieved through the N-type substrate which is subjected to two times of epitaxy; polycrystalline silicon of cells is separated through etching, one half of the polycrystalline silicon is connected with gate metal, the other half of the polycrystalline silicon is connected with source metal, a Dummy structure is formed, the ratio of true cells to false cells is 1: 1, the problem that input capacitance is too large is effectively solved, and the dynamic characteristic of a device is effectively optimized on the premise that voltage resistance and dynamic on resistance are not affected; by arranging ESD protection between the gate electrode and the source electrode, the device is prevented from being damaged under the condition of transient high voltage and large current.

An image sensor comprising a photodiode, an inter-layer dielectric layer, and a deep trench isolation structure is described. The photodiode is disposed within a semiconductor substrate having a front side and a backside opposite the front side. The inter-layer dielectric layer is disposed over the front side of the semiconductor substrate such that the front side is disposed between the inter-layer dielectric layer and the backside. The deep trench isolation structure is configured to isolate the photodiode from adjacent photodiodes included in the image sensor. The deep trench isolation structure includes a trench disposed within the inter-layer dielectric layer and the semiconductor substrate and a fill material disposed within the trench. The trench extends through the inter-layer dielectric layer and the front side of the semiconductor substrate towards the backside of the semiconductor substrate.

Fabrication methods and structures for forming integrated circuit (IC) porous semiconductor (π-Semi) isolation structures such as shallow trench isolation (STI) and / or deep trench isolation (DTI) structures. The methods speed up IC front-end-of-line processing and decrease the cost of IC fabrication. In general, exposed portions of a semiconductor layer are subjected to an electrochemical etching to form π-Semi isolation structures; in essence, the in situ semiconductor is restructured to π-Semi. The characteristics of π-Semi, particularly mesoporous π-Semi and microporous π-Semi, include good electrical insulation as well as hole trapping capability. Accordingly, π-Semi used for STI and / or DTI structures provides excellent electrical isolation. A first embodiment comprises a “pre-FET”π-Semi isolation structure, fabricated before formation of gate, drain, and source structures or regions of a field-effect transistor (FET). A second embodiment comprises a “post-FET”π-Semi isolation structure, fabricated after formation of gate, drain, and source structures or regions of a FET.

The invention relates to the technical field of wellhead protection, and particularly discloses an oil production wellhead pressure self-adaption protection device which comprises a protection shell, an indicator lamp is installed on the protection shell, the protection shell comprises a shell body, and a main pipeline is arranged on the inner side of the shell body. A partition cavity, a pressurizing groove and a pressure sensing groove are sequentially formed in the outer side of the main pipeline from top to bottom, the partition cavity is a multi-angle deep groove, a partition assembly is installed in the partition cavity, one end of the partition assembly is installed on a hydraulic input pipe, and the hydraulic input pipes are communicated through hydraulic oil communication holes; by arranging the partition assembly, when blowout occurs, a pressure sensor collects pressure information, an electric signal controls a hydraulic assembly to extend, the sharp ends of triangular fault blocks pierce the interior of a pipeline, multi-direction pressure synchronous operation is formed among the four triangular fault blocks, the pipeline is rapidly cut off, and the pipeline cannot transport oil again; and rapid and complete plugging in the pipeline is realized.

An image sensor structure including a substrate, a pixel structure, and a deep trench isolation (DTI) structure is provided. The substrate includes a first side and a second side opposite to each other. The pixel structure includes a transfer transistor, a light sensing device, and a floating diffusion region. The transfer transistor includes a first gate. The first gate is disposed on the first side of the substrate. The light sensing device is disposed in the substrate and is located on one side of the first gate. The floating diffusion region is disposed in the substrate and is located on another side of the first gate. The DTI structure extends into the substrate from the second side of the substrate. The top-view pattern of the floating diffusion region does not overlap the top-view pattern of the DTI structure.

A semiconductor device, a back-side deep trench isolation (BDTI) structure of a semiconductor device, and method of manufacturing a semiconductor structure are provided. The semiconductor device, comprising: a pixel region disposed within a substrate and comprising an image sensing element configured to convert electromagnetic radiation into an electrical signal; and one or more BDTI structures extending from a first-side of the substrate to positions within the substrate; wherein the one or more of BDTI structures comprise one or more ferroelectric materials.