96 results about "Reactive-ion etching" patented technology

The invention provides an infrared detector deep mesa etching process based on three layers of masks and an infrared detector, and belongs to the field of infrared detector mesa etching. The process comprises the following steps: spin-coating a stress buffer layer on the surface of a superlattice epitaxial layer, and curing and forming; depositing a hard mask serving as an etching barrier layer; depositing an inorganic oxide; spin-coating photoresist to form a composite patterned top layer, and then forming a mesa pattern through a photoetching process; taking the mesa pattern as a mask, and transferring the mesa pattern to the hard mask through reactive ion etching; etching the stress buffer layer by adopting plasma until the surface of the superlattice epitaxial layer is exposed; the three layers of masks are used as blocking, deep etching is carried out through inductively coupled plasma, and the etching depth is 5.6-6 microns; a post-processing step; according to the process provided by the invention, high-quality and high-aspect-ratio mesa etching can be realized on the premise of not introducing extra pollution and remarkably increasing the cost, and the process is suitable for preparing a deep-mesa and high-aspect-ratio device.

A method for etching a substrate includes pulsing an RF power at a given frequency to generate a plasma for etching the substrate where each pulse period has an ON-state and an OFF-state comprising a duty cycle, selecting an ON-state duration of the duty cycle based on, at least in part, a first duration for restriking the plasma, a second duration for a minimum on-time per a given RF power source providing the RF power, and a third duration for the plasma to reach a steady state, selecting an OFF- state duration of the duty cycle for each pulse period to alter a profile loading, a iso-dense depth loading, or a critical dimension (CD) loading etching effect associated with a feature to be formed on the substrate, and forming the feature by using the duty cycle for the RF power to etch the substrate.

The invention belongs to the technical field of electronic packaging and printed circuit boards, and particularly relates to a method for improving the bending resistance of a flexible circuit board, which comprises the following steps: after plasma pretreatment is carried out on the surface of a polyimide substrate, a three-dimensional nano-column array structure is constructed by depositing gold nanoparticles as a mask and combining reactive ion etching; then removing the mask to obtain a clean polyimide nano structure; and depositing a titanium / copper seed crystal layer through magnetron sputtering, and realizing conformal filling and coating of the copper conductive layer on the nano structure by adopting pulse reverse electroplating to form an adhesive-free mechanical interlocking interface. An adhesive-free three-dimensional mechanical interlocking structure is used for replacing an adhesive layer which is weak in physical performance and prone to fatigue failure, and the structural weak link that a traditional flexible circuit board is layered and cracked first under dynamic bending stress is thoroughly removed.

The utility model discloses waste gas treatment equipment for a reactive ion etching machine and belongs to the field of etching machines. An air inlet and an air outlet are formed in the side surface of the shell; an induced draft fan is arranged on the air inlet; the interior of the shell is fixedly connected with an isolation box; a through hole communicated with the isolation box is formed in the side surface of the shell; the top end of the side face of the isolation box is fixedly connected with a partition plate I. The other end of the partition plate I is fixedly connected to the inner wall of the shell. An air inlet is formed in the center of the top end of the isolation box, an air outlet I is formed in the center of the bottom end of the isolation box, and air outlets II are formed in the two sides of the air outlet; the partition plate II is provided with a through hole I. The top end of the side face of the isolation box is provided with a through hole II. The air outlet I is communicated with the through hole I through a pipe; a plurality of rows of sealing plates perpendicular to the penetrating holes are fixedly connected into the isolation box. And a pumping box is arranged in the isolation box. According to the utility model, not only is the filter material convenient to replace, but also the waste gas can be filtered twice when being purified, so that the purified waste gas is ensured to meet the standard.

This invention relates to a GaN-based pn junction diode device with a polarized beveled termination structure and its fabrication method. The device includes a cathode, a GaN substrate, an epitaxial layer, and an anode. The epitaxial layer comprises a lightly doped n-type GaN layer, an intrinsic GaN layer, and a p-type doped GaN layer grown in a single epitaxial growth process. The anode ohmic contact metal is placed on the p-type doped GaN layer, and the cathode ohmic contact metal is placed on the back side of the GaN substrate. It also includes a polarized beveled termination structure formed at the interface containing the pn junction, using inductively coupled plasma reactive ion etching (ICP-R) and a photoresist mask. The photoresist mask is formed using thick photoresist, followed by high-temperature heating and annealing to form the reflow morphology of the photoresist. Finally, wet repair and a passivation layer are applied to suppress the beveled n-type donor surface states of the polarized beveled termination structure. This invention effectively alleviates the boundary electric field concentration problem of GaN-based pn junctions and improves the breakdown voltage of GaN-based pn junctions.

A method tests the stress robustness of a semiconductor substrate. The method includes: forming a nitride layer on a surface of the semiconductor substrate, the nitride layer being directly deposited on the surface of the semiconductor substrate or on a native oxide layer that is interposed on the surface; cooling the semiconductor substrate and the nitride layer; patterning the nitride layer into a patterned nitride by photolithography including a step of reactive ion etching with ions produced from a gas, which includes hydrogen or a hydrogen compound or both; processing the patterned nitride and the semiconductor substrate at a temperature of not less than 800° C. and not more than 1300° C. in a nitrogen atmosphere to induce the formation of dislocations at an interface between the patterned nitride and the semiconductor substrate; and evaluating at least one property that is related to the formed dislocations.

The application provides an infrared detector deep mesa etching process based on a three-layer mask and an infrared detector, and belongs to the field of infrared detector mesa etching. The process comprises the following steps: spin-coating a stress buffer layer on the surface of a superlattice epitaxial layer and curing the stress buffer layer; depositing a hard mask as an etching barrier layer; depositing an inorganic oxide; spin-coating a photoresist to form a composite patterned top layer, and then forming a mesa pattern through a photolithography process; taking the mesa pattern as a mask, transferring the mesa pattern to the hard mask through reactive ion etching; etching the stress buffer layer by using plasma until the surface of the superlattice epitaxial layer is exposed; taking the three-layer mask as a barrier, performing deep etching by using inductively coupled plasma, and the etching depth is 5.6-6 microns; and performing a post-processing step. The process of the application can realize high-quality and high-aspect-ratio mesa etching without introducing additional pollution and significant cost increase, and is suitable for the preparation of deep mesa and high-aspect-ratio devices.

The invention discloses a preparation method of an efficient graphene-carbon nanotube transistor sensor and a method for detecting Hg < 2 + > by using the sensor, and the preparation method of the efficient graphene-carbon nanotube transistor sensor comprises the following steps: S1, preparing graphene; s2, transferring the graphene; s3, carrying out reactive ion etching and thermal evaporation on the gold electrode; s4, surface functional modification of the sensor; the high-quality graphene film is prepared by a chemical vapor deposition method, and is transferred to the surface of the silicon wafer on which the carbon nanotubes are pre-grown by a PMMA (polymethyl methacrylate) auxiliary transfer method to form a unique bent and curled structure, and the structure not only greatly increases the effective specific surface area of the material, but also gives full play to the synergistic effect of the graphene and the carbon nanotubes, so that the performance of the material is improved. The electrochemical activity of the sensor is obviously improved, so that the Hg < 2 + > detection sensitivity reaches a picomole level.

The application discloses a method for improving the moisture and heat resistance reliability of a bump connection structure, which comprises the following steps: (1) performing hydroxylation treatment on the bump connection structure for semiconductor device connection; (2) performing treatment on the bump connection structure with an organic compound to form a self-assembled molecular film; (3) performing dehydration treatment on the bump connection structure; and (4) performing etching on the self-assembled molecular film by using a reactive ion etching technology. Finally, the self-assembled molecular film with regular orientation and close arrangement is formed on the surface of the bump connection structure, especially at the undercut structure. The preparation method is simple, the self-assembled molecular film formed has high stability and corrosion resistance, and the reliability and stability of the bump in a moisture and heat environment can be effectively improved.

A method of dicing a semiconductor wafer comprises steps of a) positioning a stencil mask over the semiconductor wafer, with the stencil mask being spaced from the semiconductor wafer by a gap such that the stencil mask does not touch a component arranged on the semiconductor wafer, the stencil mask having an aperture; and b) subsequently etching through the semiconductor wafer by performing a reactive ion etch, wherein the stencil mask controls the etch. The method may allow a wafer to be diced without the use of die attach tape and without need for a cleaning step, and may be useful for dicing wafers bearing microelectromechanical systems. Also provided are a stencil mask and system useful in the method.

The invention belongs to the field of micro-nano structures, and relates to a double-layer gold nanopore structure supported by a nano needle tip as well as a preparation method and application of the double-layer gold nanopore structure. According to the preparation method, the double-layer gold nanopore structure supported by the nano needle tip is obtained through an electron beam thermal evaporation system, a polystyrene microsphere self-assembly technology and reactive ion etching (RIE), the preparation process is simple, the cost is low, the repeatability is good, the structural stability is good, and the tolerance is high. Compared with a single-layer gold nanopore structure, the single-layer gold nanopore structure not only has more modes, but also presents complex multi-mode response dependent on pumping wavelength.

The invention relates to a method for determining crystal defects in a workpiece made of monocrystalline silicon, comprising the following steps: (i) reactive ion etching at least one surface of the workpiece in a gas mixture comprising oxygen and one or more halogen-containing compounds selected from the group consisting of elemental halogen X2, hydrogen halide HX and nitrogen halide NHnX3-n, wherein X is selected from the group of Cl and Br, and 0 ≤ n ≤ 2, the flow rate of oxygen and of each of the one or more halogen-containing compounds is not less than 5 sccm and not more than 100 sccm, and the at least one surface of the workpiece to be etched is exposed to the gas mixture for no less than 10 seconds and no more than 20 minutes; and (ii) identifying defects on the etched surface of the workpiece by means of light scattering measurement.

This invention discloses a method for fabricating a gallium oxide photodetector based on reactive ion etching to enhance the synaptic effect, comprising the following specific steps: Step 1: Growing a gallium oxide layer on a substrate; Step 2: Patterning the gallium oxide layer using photolithography; Step 3: Etching the gallium oxide layer; Step 4: Forming a gallium oxide substrate on the etched gallium oxide layer using photolithography, and depositing a stacked metal on the surface of the gallium oxide layer; after peeling the gallium oxide layer and the stacked metal from the substrate, an electrode is obtained; Step 5: Annealing the electrode to alloy it and form an ohmic contact. This invention uses reactive ion etching to etch the gallium oxide layer, inducing the formation of more oxygen vacancies within the gallium oxide layer, thereby effectively enhancing the synaptic properties of the gallium oxide photodetector in biomimetic applications; it can better meet the needs of large-scale industrial applications while reducing manufacturing costs and process difficulty.

The present disclosure provides an article including a multilayer optical film including first optical layers and second optical layers, plus a boundary layer directly attached to a major surface of the multilayer optical film. The boundary layer includes a major surface opposite the multilayer optical film that has a nanostructured anisotropic surface. A method of making the article is also provided, including attaching a boundary layer directly to a major surface of a multilayer optical film, depositing an etch mask material on a major surface of the boundary layer opposite the multilayer optical film, and subsequently or concurrently reactive ion etching to anisotropically remove material in unmasked areas.

The invention discloses reactive ion etching equipment and an etching method for processing a semiconductor device, and relates to the technical field of semiconductor etching, and the reactive ion etching equipment comprises a reaction cavity which is provided with an upper gas distribution area and a lower sample placement area; wherein at least a first chamber and a second chamber are formed in the reaction chamber, the first chamber and the second chamber cover part of the wafer, and airflow control units are arranged in the first chamber and the second chamber; etching gas passes through the plasma from top to bottom and forms a sheath layer above the sample stage, so that ions generated by the plasma pass through the sheath layer and then are incident towards the surface of the wafer. Through the combination of structural partition, movable recovery and variable gas supply, sample table cooperation and closed-loop sequential control, the etching stability in a continuous mode is kept, the influence of by-product accumulation on the etching precision in a pulse mode is reduced, and the repeatability, the selective control capability and the device yield of pulse etching are improved.

The invention relates to a preparation method of a supporting table structure for reducing deformation stress of a linear array detector, solves the problems of height difference, difficulty in inverted interconnection process and large internal stress of a common electrode groove of an existing II-type superlattice linear array detector, and belongs to the technical field of infrared detectors. The preparation method comprises the following steps: (1) cleaning an epitaxial wafer; (2) depositing a SiO2 hard mask in a PECVD (plasma enhanced chemical vapor deposition) mode; (3) photoetching; (4) etching the SiO2 hard mask by adopting an RIE (Reactive Ion Etching) process; (5) degumming and cleaning; (6) etching by using an ICP (inductively coupled plasma) dry method; (7) corroding, cleaning and blow-drying the etched epitaxial wafer; (8) etching residual SiO2 by using RIE (Reactive Ion Etching); (9) carrying out pixel etching and passivation trepanning; and (10) electrode deposition. According to the design, the internal stress of the infrared column detector chip is reduced, the stress of pixels near the common electrode grooves is more uniform, and the photoelectric response uniformity of the detector is improved.

The invention relates to a method for regulating and controlling the retentivity of a ferroelectric domain wall memory through the size of a device, which comprises the following steps of: epitaxially growing a BiFeO3 film with the thickness of 200nm on a SrTiO3 (001) substrate which is beveled by 2 degrees, ensuring the quality of the film by adopting pulsed laser deposition, and forming a Pt planar electrode structure on the surface of the film through magnetron sputtering, electron beam photoetching and reactive ion etching, the polarization overturning area is controlled by adjusting the electrode gap, the retentivity is tested by combining an I-V curve and a PFM spectrum, and the result shows that when the overturning area is larger than 7 * 10 < 6 > nm < 2 >, the device can keep the polarization state for a long time, and when the area is reduced to 1.3 * 10 < 4 > nm < 2 >, the retentivity disappears. According to the invention, the retention rule of size dependence is defined, the influence of a depolarization field and ferroelastic energy is effectively overcome, and the reliability and information retention time of the memory are remarkably improved.

The invention provides a method for adjusting the steady-state pipe diameter of a self-crimping inductor. The method comprises the steps of cleaning a substrate slice, depositing a germanium sacrificial layer, depositing a dual-frequency silicon nitride stress layer and depositing an aluminum oxide protection layer. The first photoetching and the reactive ion etching define a mesa structure, the second photoetching forms a metal conductive layer, and the third photoetching and the reactive ion etching define an etching window. In the step of forming the metal conducting layer through secondary photoetching, HMDS and negative photoresist are spin-coated on the surface of the high-frequency silicon nitride stress layer of the unit substrate, and overlay alignment, exposure and development are carried out by using a second mask plate designed with a width continuous or quasi-continuous progressive increase type plane pattern, namely a hollow pattern. Then, depositing a layer of copper film on the surface of the whole substrate by adopting electron beam evaporation equipment to form a metal conductive layer; and finally, stripping operation is carried out by utilizing photoresist removing liquid, and the region with the negative photoresist and the copper film covering the region are removed, so that a firmly attached copper conductive layer pattern with a specific cross section shape is formed in the region without the photoresist.

The invention discloses an ultrathin electromagnetic shielding layer based on a magnetron sputtering technology and a preparation method thereof, and the method comprises the steps: carrying out the oxygen plasma etching of the surface of a flexible substrate through a reactive ion etching technology, the reactive ion etching power ranges from 100 W to 140 W, so that an activated substrate surface chemical group is formed on the surface of the flexible substrate; a seed layer is formed on the etched surface of the flexible substrate in a sputtering mode through the magnetron sputtering technology, the thickness of the seed layer ranges from 1 nm to 100 nm, and the roughness of the seed layer is 10 nm or below; forming a layer of shielding metal film on the surface of the seed layer through sputtering by using a magnetron sputtering technology, wherein the thickness of the shielding metal film is less than 1 [mu] m; wherein the sputtering temperature in the magnetron sputtering process ranges from 100 DEG C to 150 DEG C.

A wafer-scale silicon substrate includes through-silicon spring structures incorporating fracture-arrest features that prevent crack propagation and maintain functionality under overload or thermal stress. Each spring structure may include widened nodes, rounded etch termini, or stress-dissipating anchor points positioned along compliant beams. These structures limit fracture length and localize strain damage, allowing the wafer to remain mechanically and electrically functional even after partial spring failure. The fracture-arrest features are defined lithographically and formed concurrently with the springs using a deep reactive-ion etch, providing robust mechanical reliability for wafer-scale assemblies operating under high thermal and mechanical stress.

The invention provides a method for adjusting a curling gap of a self-curling inductor. The method comprises the steps of cleaning a substrate slice, depositing a germanium sacrificial layer, depositing a dual-frequency silicon nitride stress layer and depositing an aluminum oxide protection layer. The first photoetching and the reactive ion etching define a mesa structure, the second photoetching forms a metal conductive layer, and the third photoetching and the reactive ion etching define an etching window. In the step of forming the metal conducting layer through secondary photoetching, HMDS and negative photoresist are spin-coated on the surface of the high-frequency silicon nitride stress layer of the unit substrate, and overlay alignment, exposure and development are carried out by using a second mask plate which is provided with a locally widened plane pattern, namely a hollow pattern, designed at a predetermined front half part contact position. And then, depositing a layer of copper film on the surface of the whole substrate by adopting electron beam evaporation equipment to form a metal conductive layer. According to the invention, the curling gap can be independently or flexibly adjusted, and the limitation that the stress is changed only by changing all materials or the curling gap is controlled through the thickness in the prior art is broken through.

FIELD OF THE DISCLOSURE Embodiments of the present disclosure generally relate to systems used in semiconductor device manufacturing processes. More specifically, embodiments provided herein generally include apparatus and methods for synchronizing and controlling the delivery of RF bias signals and pulsed voltage waveforms to one or more electrodes in a plasma processing chamber. The apparatus and methods disclosed herein can be useful for at least minimizing or eliminating microloading effects that occur during processing of small dimension features that vary in density across various regions of a substrate. The plasma processing methods and apparatus described herein are configured to improve control of various characteristics of the generated plasma and control the ion energy distribution (IED) of plasma-generated ions that interact with the surface of the substrate during plasma processing. The ability to synchronize and control the waveform characteristics of the voltage waveform bias established on the substrate during processing enables improved control of the generated plasma and processes for forming high aspect ratio features on the substrate surface, for example, by reactive ion etching processes. As a result, greater precision can be achieved for plasma processing, as described in more detail herein.

The invention provides a chip local layer removing method. The method comprises the steps that after a chip is uncovered, a non-conductive layer is adjacent to the lower portion of a surface metal layer; filling a test pad region corresponding to the surface metal layer with a protective layer, and exposing a to-be-removed region; removing the surface metal layer of the to-be-removed area, and exposing the lower structure layer below the surface metal layer of the to-be-removed area; and removing the protective layer, and positioning the electrical fault point of the chip by using the test bonding pad. According to the method, the surface of the uncovered chip is filled with the hot melt wax to protect the test bonding pad, subsequent chip cleaning is facilitated, and the electrical fault point positioning effect is improved; meanwhile, local layer removal is carried out on the chip without a conducting layer under the surface metal layer, so that the fault point can still be accurately positioned under the condition that hot spot analysis of the surface metal layer is difficult, and failure analysis of a special chip is facilitated; in addition, a fault area is obtained through an electrical performance test before filling of the protective layer, and the efficiency and accuracy of subsequent electrical fault point positioning are improved; and finally, the passivation layer in the fault area is thinned and then removed, so that the influence of the passivation layer and reactive ion etching on fault point positioning is avoided, and the fault point positioning effectiveness is improved.

The utility model discloses a sample table for a reactive ion etching machine, and belongs to the field of etching machines. Comprising a sample stage and a cover; a plurality of sample grooves are formed in the upper end of the sample table, and grooves are formed in the bottom ends of the sample grooves; a supporting rod is fixedly connected to the bottom face of the groove, and a containing table is fixedly connected to the upper end of the supporting rod. An air inlet I is formed in the bottom end of the groove, an air inlet II is formed in the center of the bottom end of the sample table, and the air inlet II is communicated with the air inlet I through an air inlet channel; a vertical through hole is formed in the placing table, and a plurality of centrosymmetric exhaust channels communicated with the through hole are formed in the placing table; a plurality of etching grooves are formed in the cover, and the cover is buckled at the upper end of the sample table; a plurality of exhaust holes vertically penetrating through the sample table are formed in the sample table; and the inner wall of the sample groove is fixedly connected with a spiral plate. Through the spiral plate on the inner wall of the sample groove, the gas guide channel is added, so that cooling gas can circulate on the side surface of the sample in the processing process, the heat dissipation effect of the side surface of the sample is improved, and the heat dissipation effect of the whole sample is further improved.

The embodiment of the application relates to a dry etching method of a glass via, comprising: providing a glass substrate, the surface of the glass substrate having a mask opening; placing the glass substrate in a reaction cavity of a reaction ion etching device, alternately performing a main etching step and a sidewall passivation step until a glass via penetrating through the glass substrate is formed. By adopting the process strategy of alternately circulating the main etching step and the sidewall passivation step, the contradiction that the vertical etching rate and the sidewall protection capability are difficult to be considered in the traditional continuous etching process is effectively solved; the circulating mechanism not only significantly improves the sidewall perpendicularity of the glass via, avoids common “hourglass type” or conical defects, but also refreshes the hole bottom environment through periodic gas switching, helps to discharge reaction by-products in the deep hole, so that the micro channel effect is eliminated and stable processing of a high aspect ratio structure is realized. The application also provides a reaction ion etching device.

The application discloses an in-situ vacuum preparation system and a preparation method of a memristor, and belongs to the technical field of electronic device manufacturing. The in-situ vacuum preparation system comprises a glove box, and a vacuum collecting and connecting pipeline is connected to one side of the glove box; the vacuum collecting and connecting pipeline can be used for carrying out the following processes respectively: insulating material thermal evaporation, metal material thermal evaporation, reactive ion etching, ion beam etching, electron beam evaporation and magnetron sputtering; the insulating material evaporation and the electron beam evaporation both adopt an electron beam evaporation device; the metal material thermal evaporation and the magnetron sputtering both adopt a magnetron sputtering device; the reactive ion etching adopts a reactive ion etching device; and the ion beam etching adopts an ion beam etching device. Material deposition and electrode manufacturing in the preparation process of the memristor are carried out in the in-situ vacuum preparation system, material pollution and interface defects are avoided, the performance of the memristor is significantly improved, and the preparation process is simplified.

The invention discloses a gallium oxide photoelectric detector preparation method for enhancing a synaptic effect based on reactive ion etching. The gallium oxide photoelectric detector preparation method comprises the following specific steps: step 1, growing a gallium oxide layer on a substrate; 2, performing photoetching on the gallium oxide layer to perform patterning treatment; step 3, carrying out etching treatment on the gallium oxide layer; 4, photoetching on the etched gallium oxide layer to form a gallium oxide substrate, depositing laminated metal on the surface of the gallium oxide layer, and stripping the gallium oxide layer and the laminated metal from the substrate to obtain an electrode; and 5, annealing the electrode to alloy the electrode, and forming ohmic contact. The gallium oxide layer is etched through reactive ion etching, and more oxygen vacancies are formed in the gallium oxide layer through induction, so that the synaptic characteristic of the gallium oxide photoelectric detector in neural synaptic bionic application is effectively enhanced; and the manufacturing cost and the process difficulty can be reduced, and meanwhile, the requirements of large-scale industrial application can be better met.

A method for depositing copper onto a substrate includes grain engineering to control the internal structure of the copper. In some embodiments, the method comprises depositing a grain control layer conformally onto a copper seed layer in a structure on the substrate where the grain control layer is a non-conducting material, etching the grain control layer using a direct deep reactive ion etch (DRIE) process to remove portions of the grain control layer on horizontal surfaces within the structure, and depositing a copper material onto the structure such that at least one grain parameter of the copper material is controlled, at least in part, by a remaining portion of the grain control layer on vertical surfaces of the structure. In some embodiments, the deposited copper material in the structure has a <111> grain orientation normal to a horizontal surface of the structure.

This invention provides a TEM sample, its preparation method, and its application. The TEM sample preparation method provided by this invention, without affecting the pore structure of the semiconductor device, first uses reactive ion etching to remove some residual polymer deposits blocking the pore openings on the semiconductor device. This enlarges the pore openings, preventing blockage and facilitating the entry of colloidal materials into the pore structure for filling and the deposition of precursor materials for atomic layer deposition. This enhances the clarity of the pore sidewalls, effectively improving the quality of the TEM sample and the final observation results. Furthermore, the TEM sample preparation method provided by this invention requires less equipment and technical investment, and the operation process is simpler and faster than Fab etching. It also enables batch laboratory-scale sample processing. In addition, compared to wet chemical etching cleaning techniques for removing residual polymers, it avoids problems such as chemical reagent residues at the bottom of deep pore structures and chemical reactant contamination.

The invention provides a surface acoustic wave filter and a preparation method thereof, and the preparation method comprises the following steps: S1, selecting a piezoelectric substrate; s2, sequentially carrying out spin coating of photoresist, photoetching and developing on one side of the piezoelectric substrate to expose an electrode groove region; s3, performing reactive ion etching on each electrode groove area to form an electrode groove which is recessed inwards; step S4, removing the residual photoresist; s5, a capacitor electrode is embedded in each electrode groove; and S6, manufacturing a plurality of acoustic electrodes to obtain the surface acoustic wave filter. An included angle is formed between the second direction and the sound wave propagation direction, and the included angle is larger than-10 degrees and smaller than 10 degrees. According to the preparation method of the surface acoustic wave filter, the capacitance value of the interdigital capacitor can be improved without increasing the overall area of the surface acoustic wave filter, and the filtering performance of the surface acoustic wave filter is not affected.