19 results about "Reactive-ion etching" patented technology

A method of dicing a semiconductor wafer comprises steps of a) positioning a stencil mask over the semiconductor wafer, with the stencil mask being spaced from the semiconductor wafer by a gap such that the stencil mask does not touch a component arranged on the semiconductor wafer, the stencil mask having an aperture; and b) subsequently etching through the semiconductor wafer by performing a reactive ion etch, wherein the stencil mask controls the etch. The method may allow a wafer to be diced without the use of die attach tape and without need for a cleaning step, and may be useful for dicing wafers bearing microelectromechanical systems. Also provided are a stencil mask and system useful in the method.

A wafer-scale silicon substrate includes through-silicon spring structures incorporating fracture-arrest features that prevent crack propagation and maintain functionality under overload or thermal stress. Each spring structure may include widened nodes, rounded etch termini, or stress-dissipating anchor points positioned along compliant beams. These structures limit fracture length and localize strain damage, allowing the wafer to remain mechanically and electrically functional even after partial spring failure. The fracture-arrest features are defined lithographically and formed concurrently with the springs using a deep reactive-ion etch, providing robust mechanical reliability for wafer-scale assemblies operating under high thermal and mechanical stress.

The embodiment of the application relates to a dry etching method of a glass via, comprising: providing a glass substrate, the surface of the glass substrate having a mask opening; placing the glass substrate in a reaction cavity of a reaction ion etching device, alternately performing a main etching step and a sidewall passivation step until a glass via penetrating through the glass substrate is formed. By adopting the process strategy of alternately circulating the main etching step and the sidewall passivation step, the contradiction that the vertical etching rate and the sidewall protection capability are difficult to be considered in the traditional continuous etching process is effectively solved; the circulating mechanism not only significantly improves the sidewall perpendicularity of the glass via, avoids common “hourglass type” or conical defects, but also refreshes the hole bottom environment through periodic gas switching, helps to discharge reaction by-products in the deep hole, so that the micro channel effect is eliminated and stable processing of a high aspect ratio structure is realized. The application also provides a reaction ion etching device.

This invention provides a TEM sample, its preparation method, and its application. The TEM sample preparation method provided by this invention, without affecting the pore structure of the semiconductor device, first uses reactive ion etching to remove some residual polymer deposits blocking the pore openings on the semiconductor device. This enlarges the pore openings, preventing blockage and facilitating the entry of colloidal materials into the pore structure for filling and the deposition of precursor materials for atomic layer deposition. This enhances the clarity of the pore sidewalls, effectively improving the quality of the TEM sample and the final observation results. Furthermore, the TEM sample preparation method provided by this invention requires less equipment and technical investment, and the operation process is simpler and faster than Fab etching. It also enables batch laboratory-scale sample processing. In addition, compared to wet chemical etching cleaning techniques for removing residual polymers, it avoids problems such as chemical reagent residues at the bottom of deep pore structures and chemical reactant contamination.

This invention discloses a semi-flexible sealed composite material beam-membrane-island structure for micro / nano devices and its fabrication method. The invention employs both rigid and flexible materials to construct the beam-membrane-island structure of the micro / nano device. The beam and island structures are made of rigid materials that can be fabricated in micro / nano dimensions, while flexible materials fill the periphery of the beam and island structures. The flexible filling layer acts as a "displacement coordination layer," ensuring a clear mechanical response while maintaining the high modulus of the silicon beam. Simultaneously, the local deformation of the flexible layer absorbs lateral coupling stress, allowing strain fields in different directions to be separated and amplified in the beam / island region. The flexible material forms a stress transition zone between the beam and island, preventing strong stress concentration in the pure silicon beam-island structure under concentrated loads. This invention still uses materials compatible with micro / nano fabrication processes as the main structural material, enabling integration with standard photolithography, reactive ion etching, deep silicon reactive ion etching, anodic bonding processes, through-silicon vias (TSVs), and glass vias, among other micro / nano processes.

The application discloses a kind of semi-flexible sealing composite beam membrane island structure formula micro-nano device and its processing method.The application uses hard material and flexible material to constitute the beam membrane island structure of micro-nano device, wherein the hard material that can be micro-nano processed is used in beam structure and island structure, and flexible material is filled in the periphery of beam structure and island structure.Flexible filling layer plays the role of "displacement coordination layer", and by the local deformation of flexible layer, transverse coupling stress is absorbed, so that strain field in different directions is separated and enlarged in beam / island area.Flexible material forms stress transition zone between beam and island, to avoid strong stress concentration of pure silicon beam island structure under concentrated load.The application still uses material compatible with micro-nano processing technology as main structure material, and can be integrated with standard photolithography, reactive ion etching, deep silicon reactive ion etching and anodic bonding process, through silicon via, through glass via and other micro-nano processes.

The invention relates to a method for preparing a single-domain thin film (4) of piezoelectric material, comprising finishing a first layer (8) transferred onto a substrate (2). The finishing process includes heat treatment of the free face (9) of the first layer, followed by its thinning to form the single-domain thin film (4). According to the invention, the thinning of the first layer (8) comprises reactive ion etching using a plasma prepared by a mixture of a noble gas and a chlorinated gas. Figure 2

This invention relates to a method and system for fabricating an ultra-small AWG chip, comprising: using ICP-VD technology on a silicon substrate to controllably grow a low-stress, low-optical-absorption silicon nitride thin film by adjusting plasma power and gas flow rate; covering the silicon nitride thin film with a hybrid mask, and determining a reactive ion etching combination with a primary etching gas and an auxiliary passivation gas according to a target volume ratio; etching the silicon nitride thin film based on the reactive ion etching combination to form a silicon nitride waveguide structure with a sidewall roughness less than a preset roughness threshold; adjusting the thickness and width of the waveguide to achieve a design goal of ultra-thin and ultra-wide waveguide compatible with single-mode transmission characteristics and low bending loss, and designing the bending transition section of the waveguide as a gradually curved structure by transforming optical principles; integrating the designed waveguide into the AWG chip in a preset array configuration, and using a Rowland circle overlapping lithography to compress the overlapping area between the input and output waveguides in the array.

A wafer-scale silicon substrate includes lithographically defined through-silicon spring structures that mechanically isolate rigid silicon islands while preserving electrical continuity through a multilayer redistribution network routed across the spring regions. The springs are formed by deep reactive-ion etching and provide anisotropic mechanical compliance, allowing in-plane and out-of-plane deflection to relieve thermal and assembly stresses. Redistribution-layer wiring traverses the spring contours, enabling dense interconnect between adjacent islands while maintaining elastic operation of the substrate. The structure forms an electrically continuous yet mechanically compliant wafer base suitable for mounting multiple semiconductor stacks without interconnect fatigue or warpage.

The SiC wafer is smoothed after mechanical polishing, supporting the epitaxial growth of SiC films with a low defect rate. [Solution] The method comprises the steps of placing a workpiece equipped with a SiC substrate on a substrate support in a plasma chamber, introducing a process gas into the plasma chamber, and reducing the surface roughness of the SiC substrate by plasma etching the SiC substrate, and alternately performing the steps of generating reactive ion etching plasma in the plasma chamber by applying bias RF power to the substrate support and etching the SiC substrate at a first plasma chamber pressure for a first period, and generating inductively coupled plasma in the plasma chamber by applying source RF power to the plasma chamber, applying bias RF power to the substrate support and etching the SiC substrate at a second plasma chamber pressure for a second period.

The application aims to provide a method for preparing YBCO nanowires at low temperature and low pressure, and belongs to the technical field of single photon detection. The method adopts inductively coupled plasma reactive ion etching (ICP-RIE) technology to prepare nanowires. The YBCO nanowires prepared by the method have a thickness of 5 nm and a width of 68 nm, and excellent morphology and electrical characteristics of the nanowires are ensured. By accurately adjusting the temperature and pressure parameters, the damage caused by the thermal effect in the etching process is effectively reduced, and a very small lateral etching damage width (about 15 nm) is obtained. At the same time, the switching current (I s ) coefficient of variation of the batch-prepared nanowires is less than 6%, and the coefficient of variation of the resistance-temperature (R-T) characteristics is less than 1%, which proves the excellent uniformity.

The present invention relates to a method and system for atomic layer etching (ALE) using a single gas or a mixture of gases throughout the process without the need for gas switching. The ALE process includes a continuous surface modification process in which the substrate surface is first chemically altered and then removed by intermittent ion pulse sputtering steps. The process eliminates undesirable reactive ion etching (RIE) and achieves the ideal ALE process through a novel bias unit design. The method and system disclosed are particularly suitable for forming high aspect ratio (HAR) structures.

Provided is an efficient method for attaching a tissue section. In the invention, one of problems is solved by changing attachment conditions of the tissue section depending on an organ from which the tissue section is derived. A technique of achieving good adhesiveness between a microscope slide and a section by introducing unevenness on a front surface of the microscope slide using reactive ion etching as one of the attachment conditions is provided. Further, a technique of optimizing the attachment of the section using a machine learning technique or the like is provided.

The application discloses a kind of plasma processing equipment and its control method, for the problem that remote plasma source or ion trap is needed in existing free radical etching, leading to the complexity of equipment, low efficiency of gas inlet and outlet, independent controllable radio frequency coil structure is used in center and edge.In the first process based on free radical processing, the edge coil is controlled to run at high power, and the center coil can run at zero power, the plasma excitation is transferred to the edge of the reaction cavity, and the characteristics of long-life diffusion of free radicals and short-life annihilation of ions are used to remove ions in situ.The application does not need additional ion filtering device, greatly simplifies the structure of the equipment, reduces the gas flow resistance, improves the response speed of gas inlet and outlet and the process cycle efficiency;At the same time, the diffusion of ions to the substrate is effectively inhibited, the pure free radical reaction characteristics are maintained, the conversion to reactive ion etching is avoided, especially suitable for atomic layer etching process, significantly improves the production capacity and processing precision.

A method of dicing a semiconductor wafer comprises steps of a) positioning a stencil mask over the semiconductor wafer, with the stencil mask being spaced from the semiconductor wafer by a gap such that the stencil mask does not touch a component arranged on the semiconductor wafer, the stencil mask having an aperture; and b) subsequently etching through the semiconductor wafer by performing a reactive ion etch, wherein the stencil mask controls the etch. The method may allow a wafer to be diced without the use of die attach tape and without need for a cleaning step, and may be useful for dicing wafers bearing microelectromechanical systems. Also provided are a stencil mask and system useful in the method.

A semiconductor structure and process eliminate redistribution-layer overhang at openings that define compliant silicon elements used for stress relief. A silicon substrate includes a trench with substantially vertical sidewalls. A redistribution-layer stack above the substrate is patterned with an aperture intentionally larger than the trench mouth to form an annular indent that laterally clears lithographic alignment and etch-profile variations so the redistribution-layer stack does not project over the trench perimeter. The configuration reduces stress concentration at the redistribution-layer-silicon transition and improves long-term reliability under thermal cycling. Methods include forming the aperture in the redistribution-layer stack, deep reactive-ion etching the silicon trench through the aperture, and controlling aperture-to-trench sizing using a single hardmask and inspection to verify clearance.

This invention provides a metasurface-based light field display system and method. The metasurface-based light field display system includes: a light source device for emitting outgoing light rays, the intensity of which is calculated by a computer using ray tracing based on a three-dimensional light field model to be displayed; wherein the intensity of the outgoing light rays carries RGB information of different intensities; a metasurface device for freely stereoscopically modulating the light field of the outgoing light rays to reconstruct the three-dimensional light field model to be displayed, resulting in a naked-eye visible three-dimensional light field model; the metasurface device is fabricated based on superatoms and phase templates through electron beam exposure and reactive ion etching; wherein the light source device and the metasurface device are arranged sequentially in the optical path of the outgoing light rays; the outgoing light rays are collimated rays. This invention has the advantages of small size, light weight, and stable structure, achieving naked-eye three-dimensional display with less limitation on viewing angle and controllable display effect.