4906 results about "Volatile memory" patented technology

Technology for reading memory cells in three-dimensional memory having multiple tiers. The memory system erases the tiers within each block independently. Then, memory cells in the tiers are programmed by units such as word lines. The memory system determines one or more read parameters for the selected tier based on the programmed / erased states of the other tiers in the block. For example, the memory system may select read reference levels for the selected tier based on the programmed / erased states of the other tiers. In an aspect, the one or more read parameters are used to determine the set of reference voltages for a bit error rate estimation scan (BES).

A non-volatile memory device for performing compute in memory operations for a neural network uses a three dimensional NOR architecture in which vertical NOR strings are formed of multiple memory cells connected in parallel between a source line and a bit line. Weights of the neural network are encoded as threshold voltages of the memory cells and activations are encoded as word line voltages applied to the memory cells of the NOR strings. The memory cells are operated in the subthreshold region, where the word line voltages are below the threshold voltages. The NOR structure naturally sums the resultant subthreshold currents of the individual memory cells to generate the product of the activations and the weights of the neural network by concurrently applying input voltages to multiple memory cells of a NOR string.

The present disclosure describes apparatuses and methods for implementing secure verification of a physical unclonable function (PUF). In various aspects, a PUF verifier generates a PUF reagent value by obtaining a key from a PUF and a message value useful for PUF verification. The PUF verifier computes a digest value of the PUF key and the message value and selects a portion of the hash digest as a PUF reagent value. The PUF verifier writes the PUF reagent value to a non-volatile memory to enable subsequent verification of the PUF. The PUF verifier may also generate error-correction code information for the PUF reagent value and write this information to the non-volatile memory to enable error correction. Upon device hardware reset, the PUF verifier can securely verify PUF operation by generating a PUF key hash digest and comparing the hash digest with the PUF reagent value without exposing the PUF key.

A system and method for using a semi-polling model to monitor a Non-Volatile Memory Express (NVMe) completion queue (CQ). The method, implemented at an interrupt thread, includes receiving an input / output (I / O) request from an application and submitting a submission queue (SQ) entry into an NVMe SQ in response to the I / O request. The method further includes registering for notifications from a polling thread after submitting the SQ entry and receiving, from the polling thread, a notification of the presence of a CQ entry within an NVMe CQ. Additionally, the method involves removing the CQ entry from the NVMe CQ and notifying the application of completion of the I / O request.

An IoT system for sensing, monitoring, logging and transmitting events that is assembled on a firearm and the holster of said firearm, made up of at least two IoT modules, wherein a first IoT module is located in the firearm and a second IoT module is located in the holster of the firearm. Said system further includes sensing, logging, storing, and transmitting the real-time (or near-real-time) location of the firearm and the user thereof in an ongoing manner, so as to be able to reconstruct the path of the firearm of interest over time. Transmitting the events selected from the set including data indicating the state of the firearm (holstered or drawn), battery charge of both modules, position of the firearm and the bearer thereof; direction of the firearm, firearm fired and the absolute orientation of each shot. In the presence of any of said events, storing in a non-volatile memory a preset time before and after the data of all the sensors before, during and after the event. Said log includes the encoding of the sensed data, the interleaving of said data and the encryption thereof.

A computer system and method are disclosed for replicating logs in a distributed environment. The method includes identifying a write input / output (I / O) operation and identifying a log to be replicated based on the write I / O operation. The log is then persisted to local non-volatile memory in the computer system. Subsequently, the log is replicated to multiple remote hosts, where each remote host of the plurality of remote hosts stores the log in its corresponding local non-volatile memory without de-staging the log to a backing store. The write I / O operation is committed once the log is replicated to at least a subset of the remote hosts that forms a quorum. Finally, the log is de-staged to the backing store after the write I / O operation is successfully committed.

The invention relates to the technical field of computer system structures and storage, in particular to a non-volatile memory quick recovery method based on metadata priority and on-demand loading. The method comprises the following steps: in response to a system fault signal detected by a voltage monitoring unit, freezing a processor context and traversing a page table structure to extract system configuration information; writing the system configuration information and business data codes in the volatile memory into a nonvolatile medium to generate a persistent state mirror image; analyzing the persistent state mirror image, extracting address conversion metadata, and reconstructing a mapping relation from a virtual address to a physical page frame in a volatile memory; and generating an address mapping table, wherein the physical page frame pointed by the address mapping table is set to be in an existing state but is not associated with the effective service data. According to the method, decoupling of the control flow and the data flow is realized by constructing a virtual ready state, and quick starting of the system and immediate response of key services are realized on the premise of not depending on the total capacity of a memory.

A work vehicle capable of automatic steering driving includes a positioning system to perform positioning of the work vehicle, and a controller including a non-volatile memory. The controller is configured or programmed to estimate an orientation of the work vehicle based on a change over time of a position of the work vehicle measured by the positioning system, perform automatic steering control of the work vehicle based on the position and the orientation of the work vehicle and a set target route, store the orientation of the work vehicle in the non-volatile memory in response to a key-off operation of the work vehicle, and after a key-on operation of the work vehicle is performed, initiate the automatic steering control using the orientation stored in the non-volatile memory as an initial orientation of the work vehicle.

An example CXL (Compute eXpress Link)-based memory module includes a memory device and a controller. The memory device includes a plurality of volatile memory cells and stores data or reads the stored data. The controller communicates with a host device through a CXL interface and controls the memory device. The controller includes an error correction code (ECC) circuit that generates a first codeword by adding a parity vector generated based on Reed-Solomon encoding to data received from the host device, an error injecting circuit that generates an error symbol and generates a second codeword by injecting the error symbol into at least a portion of the first codeword, and a memory device interface that controls the memory device such that the second codeword where the error symbol is injected is stored in the memory device. The controller determines a number of error symbols to be injected into the second codeword.

Methods and apparatus for energy management in data storage devices are provided. One such data storage device (DSD) includes a non-volatile memory (NVM), a set of hardware processing engines, and a power sensor to detect a total power consumption of the set of hardware processing engines. A processor is configured to determine an energy-per-processing event value for each of the set of processing engines based on total power consumption measurements and processing event duration values, then control energy delivery to the processing engines based on the energy-per-processing event values in accordance with an energy budget. In some examples, the DSD employs a least-squares procedure to estimate power-per-processing event values so the values can be determined without needing to measure individual power consumption of the processing engines. The power-per-processing event values are converted to energy-per-processing event values based on corresponding processing event durations. A recursive least-squares update procedure is also described.

A non-volatile memory device for performing compute in memory operations for a neural network uses a three dimensional NAND architecture. Multi-bit weight values are stored encoded as sets of threshold voltages for sets of memory cells. A weight value is stored in multiple memory cells on the same word line and connected between a bit line and a source line, each of the memory cells programmed to one of multiple threshold voltages. When multiplying an input value with the weight value, the word line is biased so that, for at least one of the threshold voltages, the memory cell will be in the linear operation region. Input values are encoded as a set of one or more voltage levels applied to a corresponding set of bit lines, each bit line connected memory cells also storing the weight value, connected to the word line, and connected to the source line.

Systems and methods are disclosed for implementing a Non-Volatile Memory Express (NVMe) driver in a computer system. The method involves mapping a memory buffer into a user mode address space to facilitate data transfer with an NVMe device via direct memory access (DMA). Additionally, a first NVMe queue pair, including a submission queue (SQ) and a completion queue (CQ), is mapped into the user mode address space, allowing a user mode component to submit commands to the NVMe device. The method further enables the user mode component to ring a doorbell at the NVMe device. Finally, an NVMe command is processed in kernel mode using a second NVMe queue pair comprising a second SQ and a second CQ.

A system is disclosed. The system has an ultra-low latency data and video streaming module, comprising computer-executable code stored in non-volatile memory, a processor, a control center device, and a plurality of vehicle, robot or drone units that operate remotely from the control center device, each of the plurality of units including a control device. The control module, the processor, the control center device, and the control devices are configured to video stream using one or more camera modules disposed at each of the plurality of units, transfer the video streams from the control devices to the control center device.

A programmable driver circuit (54) and related method (600) for simultaneously controlling multiple tunable probabilistic bit generators are disclosed. The driver circuit comprises a plurality of programmable voltage generators (52; 30), a programming unit (35) and a non-volatile memory unit (34a-b). Input terminals of the plurality of programmable voltage generators are jointly connectible to a single voltage supply source. The programming unit is configured to generate a sequence of programming pulses for the different voltage generators. Each voltage generator comprises a single-stage or multi-stage voltage divider circuit (31) formed by a series of resistive elements (32-1; 32-2; 33). The non-volatile memory unit (34a-b) comprises at least the resistive element positioned first in the series of resistive elements as a programmable resistance and a program control transistor (34-1) connected in series between the programmable resistance and a fixed reference voltage. A control gate of the program control transistor is operatively coupled to the programming unit to receive the sequence of programming pulses for the programmable voltage generator when operated in a programming mode.

A storage device includes a non-volatile memory and a storage controller, wherein the storage controller includes a cache memory storing some of data stored in the non-volatile memory, an interface circuit receiving, from a first external host, a first request including a source address related to the external storage device, a destination address related to the storage device, and cache update information indicating an update method of the cache memory, provide a second request including the source address to the external storage device, and receive, from the external storage device in response to the second request, a response including first data corresponding to the source address, an address translation circuit generating a physical address of a first type based on the destination address, and a cache controller updating a cache area indicated by the physical address of the first type based on the cache update information.

Numerous embodiments are disclosed for splitting an array of non-volatile memory cells in an analog neural memory in a deep learning artificial neural network into multiple parts. Each part of the array interacts with certain circuitry dedicated to that part and with other circuitry that is shared with one or more other parts of the array.

A memory apparatus includes memory cells and a control means configured to adjust at least one of blind program pulses applied to word lines connected to the memory cells and bit line voltages applied to bit lines coupled to the memory cells in response to determining one of the word lines connected to the memory cells being programmed is susceptible to over-programming. The control means programs non-checkpoint ones of the memory cells associated with a checkpoint state to a verify low voltage for the checkpoint state and programs the non-checkpoint ones of the memory cells to respective non-checkpoint states associated with the checkpoint state by applying the blind program pulses to each non-checkpoint one of the memory cells without verifying whether the non-checkpoint ones of the memory cells have reached their respective non-checkpoint states while applying the bit line voltages to the bit lines associated therewith.

A storage device comprises a first non-volatile memory, a storage controller configured to receive a memory command for writing data in the first non-volatile memory or reading the data from the first non-volatile memory from a processor of a host device through a first channel, a microcontroller configured to receive a command related to a firmware update executed in the storage device from a baseboard management controller (BMC) of the host device through a second channel different from the first channel, and a second non-volatile memory configured to receive and store firmware data from the BMC of the host device.

Various techniques are provided for providing a root of trust chain, updating security protocols, and generating trusted customer configuration bitstreams for a programmable logic device (PLD). In one example, a method includes configuring hardware components of a PLD with an inherently trusted default set of operations immutably stored in a non-volatile memory and comprising a first root of trust for the PLD. The method also includes authenticating, by the hardware components configured with the default set of operations, a customer configuration bitstream comprising an updated set of operations. The method also includes reconfiguring the hardware components to replace the default set of operations with the updated set of operations if the authenticating is successful, wherein the updated set of operations comprise a second root of trust for the PLD. Additional devices, systems and methods are also provided.

To reduce noise for compute in memory vector-matrix multiplications using non-volatile memory, such in large language models or other neural networks, the matrix of values is independently programmed in multiple arrays. The input vector is then independently applied to the multiple arrays to generate a corresponding set of multiple results. The independent results can then be combined by ensemble algorithms, as an averaging, to generate the output. The combined output can then be used as input to a subsequent layer of weights, which can again be independently written in to multiple arrays.

An apparatus for storing data in a nonvolatile memory includes a controller configured to erase a group of physical memory cells in the nonvolatile memory. The controller is configured to write multiple bits of information to each of a first group of physical memory cells in the nonvolatile memory. The controller is configured to map a logical address range to a physical address range for the first group of physical memory cells in the nonvolatile memory. The controller is configured to determine if the first group of physical memory cells fails a data integrity test. If the first group of physical memory cells fails the data integrity test, the controller writes at least some of the information stored in the first group of physical memory cells to a second group of physical memory cells in the nonvolatile memory. The controller writes a single bit of information per cell in the second group of physical memory cells. The controller is configured to map the logical address range to a second physical address range for the second group of physical memory cells.

A data storage device and method are provided for using a dynamic floating flash region to secure a firmware update. In one embodiment, a data storage device is provided comprising a first non-volatile memory, a second non-volatile memory, and a controller. The controller is configured to communicate with the first and second non-volatile memories and further configured to: determine addresses in the second non-volatile memory to store portions of a firmware update, wherein the addresses are determined on-the-fly as opposed to being predetermined; and store the portion of the firmware update in the addresses in the second non-volatile memory. Other embodiments are provided.

The invention provides a dual-storage system starting method and device. An architecture in which a master control chip SOC works cooperatively with an external memory DDR, a nonvolatile memory SPI NOR and an SD card is adopted. After the SOC is powered on, a BootROM guide code is executed, a system is initialized, ID Blocks containing a DDR initialization program and an SPL secondary loading program are sequentially obtained and verified from multiple storage media, the DDR initialization program is loaded, DDR is initialized, and the SPL secondary loading program is loaded to the DDR to run. The method comprises the following steps of: firstly, loading an SD (Secure Digital) card, then loading U-Boot firmware, completing initialization of residual hardware and security mirror verification, then detecting and verifying a kernel mirror format and Header information in the SD card, then loading a Linux kernel, an equipment tree and a ramdisk, mounting rootfs to an RAM (Random Access Memory) space, and mounting the SD card as a user data storage space. According to the method, high reliability of system guiding is ensured through the SPI NOR, large-capacity storage and flexible upgrading are achieved through the SD card, and the comprehensive performance of the embedded system in the aspects of reliability, storage expansibility and cost effectiveness is remarkably improved.

A controller, of a solid state drive (SSD), may perform, on one or more blocks of a non-volatile memory device of the SSD, read operations using pre-determined threshold voltages associated with two overlapped charge states. The read operations may be performed after a power-on condition following a power-off condition on the non-volatile memory device. The controller may determine, using a machine learning model, a change in threshold voltages associated with the two overlapped charge states, after the power-off condition. The machine learning model may determine the change in threshold voltages using bit error rates associated with the read operations. The machine learning model may be trained to determine changes in threshold voltages for the two overlapped charge states, after power-off conditions. The controller may determine adjusted threshold voltages associated with the two overlapped charge states based on the change in threshold voltages.

A semiconductor memory device is implemented as strings of storage transistors, where the storage transistors in each string have drain terminals connected to a bit line and gate terminals connected to respective word lines. In some embodiments, the semiconductor memory device includes a reference bit line structure to provide a reference bit line signal for read operation. The reference bit line structure configures word line connections to provide a reference bit line to be used with a storage transistor being selected for read access. The reference bit line structure provides a reference bit line having the same electrical characteristics as an active bit line and is configured so that no storage transistors are selected when a word line is activated to access a selected storage transistor associated with the active bit line.

Aspects of a storage device are provided for handling detection and operations associated with an erase block type of the block. The storage device includes one or more non-volatile memories each including a block, and one or more controllers operable to cause the storage device to perform erase type detection and associated operations for single blocks or metablocks. For instance, the controller(s) may erase the block prior to a power loss event, perform at least one read of the block following the power loss event, identify the erase block type of the block in response to the at least one read, and program the block based on the identified erase block type without performing a subsequent erase prior to the program. The controller(s) may also perform metablock operations associated with the identified erase block type. Thus, unnecessary erase operations during recovery from an ungraceful shutdown (UGSD) may be mitigated.

Systems and methods for autonomous space-mission coordination integrate ground-based prediction with on-orbit execution. A processing system in a ground station may ingest multi-source environmental data, produce near-term nowcasts through an prediction model, rank pending spacecraft tasks against current resource telemetry, select a high-value task subset, convert the subset into time-tagged command packets, and transmit the packets through a communications link. A processing system aboard each spacecraft may receive the packets, merge them into a persistent schedule, and at each time tag slews attitude, activate an imaging or radar sensor with specified parameters, capture data, and store the data in non-volatile memory. The spacecraft may generate quality metrics for the captured data and return the metrics to the ground station.

Exemplary methods and apparatus are provided for implementing a deep learning accelerator (DLA) or other neural network components within the die of a non-volatile memory (NVM) apparatus using, for example, under-the-array circuit components within the die. Some aspects disclosed herein relate to configuring the under-the-array components to implement feedforward DLA operations. Other aspects relate to backpropagation operations. Still other aspects relate to using an NAND-based on-chip copy with update function to facilitate updating synaptic weights of a neural network stored on a die. Other aspects disclosed herein relate to configuring a solid state device (SSD) controller for use with the NVM. In some aspects, the SSD controller includes flash translation layer (FTL) tables configured specifically for use with neural network data stored in the NVM.

Described are techniques for write protecting a non-volatile memory (NVM) after the contents of the NVM have been set. In some examples, a computing device or system having an NVM also includes a Root of Trust (RoT) configured to generate a write protect command as an input to the NVM. The RoT generates the write protect command in response to detecting a write protect signal from an electronic controller. The write protect command sets one or more areas in the NVM to be read-only. Further, the write protect command can make the one or more areas read-only on a power-on basis so that write protection is maintained until the next power cycle. The electronic controller can be configured to assert the write protect signal each time the computing device or system is powered on, for instance during a reboot, thereby causing the RoT to renew the write protection.

Methods, systems, and devices for front-to-front bonding in a stacked memory system are described. The stacked memory system may include a package substrate and a volatile memory die with a front side. The stacked memory system may also include a logic die with a front side that is bonded with the front side of the volatile memory die. The back side of the stacked memory system may be coupled with a conductive bump that in turn is coupled with the package substrate.