3673 results about "Volatile memory" patented technology

The present disclosure describes apparatuses and methods for implementing secure verification of a physical unclonable function (PUF). In various aspects, a PUF verifier generates a PUF reagent value by obtaining a key from a PUF and a message value useful for PUF verification. The PUF verifier computes a digest value of the PUF key and the message value and selects a portion of the hash digest as a PUF reagent value. The PUF verifier writes the PUF reagent value to a non-volatile memory to enable subsequent verification of the PUF. The PUF verifier may also generate error-correction code information for the PUF reagent value and write this information to the non-volatile memory to enable error correction. Upon device hardware reset, the PUF verifier can securely verify PUF operation by generating a PUF key hash digest and comparing the hash digest with the PUF reagent value without exposing the PUF key.

The invention relates to the technical field of computer system structures and storage, in particular to a non-volatile memory quick recovery method based on metadata priority and on-demand loading. The method comprises the following steps: in response to a system fault signal detected by a voltage monitoring unit, freezing a processor context and traversing a page table structure to extract system configuration information; writing the system configuration information and business data codes in the volatile memory into a nonvolatile medium to generate a persistent state mirror image; analyzing the persistent state mirror image, extracting address conversion metadata, and reconstructing a mapping relation from a virtual address to a physical page frame in a volatile memory; and generating an address mapping table, wherein the physical page frame pointed by the address mapping table is set to be in an existing state but is not associated with the effective service data. According to the method, decoupling of the control flow and the data flow is realized by constructing a virtual ready state, and quick starting of the system and immediate response of key services are realized on the premise of not depending on the total capacity of a memory.

A work vehicle capable of automatic steering driving includes a positioning system to perform positioning of the work vehicle, and a controller including a non-volatile memory. The controller is configured or programmed to estimate an orientation of the work vehicle based on a change over time of a position of the work vehicle measured by the positioning system, perform automatic steering control of the work vehicle based on the position and the orientation of the work vehicle and a set target route, store the orientation of the work vehicle in the non-volatile memory in response to a key-off operation of the work vehicle, and after a key-on operation of the work vehicle is performed, initiate the automatic steering control using the orientation stored in the non-volatile memory as an initial orientation of the work vehicle.

A non-volatile memory device for performing compute in memory operations for a neural network uses a three dimensional NAND architecture. Multi-bit weight values are stored encoded as sets of threshold voltages for sets of memory cells. A weight value is stored in multiple memory cells on the same word line and connected between a bit line and a source line, each of the memory cells programmed to one of multiple threshold voltages. When multiplying an input value with the weight value, the word line is biased so that, for at least one of the threshold voltages, the memory cell will be in the linear operation region. Input values are encoded as a set of one or more voltage levels applied to a corresponding set of bit lines, each bit line connected memory cells also storing the weight value, connected to the word line, and connected to the source line.

A storage device includes a non-volatile memory and a storage controller, wherein the storage controller includes a cache memory storing some of data stored in the non-volatile memory, an interface circuit receiving, from a first external host, a first request including a source address related to the external storage device, a destination address related to the storage device, and cache update information indicating an update method of the cache memory, provide a second request including the source address to the external storage device, and receive, from the external storage device in response to the second request, a response including first data corresponding to the source address, an address translation circuit generating a physical address of a first type based on the destination address, and a cache controller updating a cache area indicated by the physical address of the first type based on the cache update information.

Numerous embodiments are disclosed for splitting an array of non-volatile memory cells in an analog neural memory in a deep learning artificial neural network into multiple parts. Each part of the array interacts with certain circuitry dedicated to that part and with other circuitry that is shared with one or more other parts of the array.

To reduce noise for compute in memory vector-matrix multiplications using non-volatile memory, such in large language models or other neural networks, the matrix of values is independently programmed in multiple arrays. The input vector is then independently applied to the multiple arrays to generate a corresponding set of multiple results. The independent results can then be combined by ensemble algorithms, as an averaging, to generate the output. The combined output can then be used as input to a subsequent layer of weights, which can again be independently written in to multiple arrays.

A data storage device and method are provided for using a dynamic floating flash region to secure a firmware update. In one embodiment, a data storage device is provided comprising a first non-volatile memory, a second non-volatile memory, and a controller. The controller is configured to communicate with the first and second non-volatile memories and further configured to: determine addresses in the second non-volatile memory to store portions of a firmware update, wherein the addresses are determined on-the-fly as opposed to being predetermined; and store the portion of the firmware update in the addresses in the second non-volatile memory. Other embodiments are provided.

The invention provides a dual-storage system starting method and device. An architecture in which a master control chip SOC works cooperatively with an external memory DDR, a nonvolatile memory SPI NOR and an SD card is adopted. After the SOC is powered on, a BootROM guide code is executed, a system is initialized, ID Blocks containing a DDR initialization program and an SPL secondary loading program are sequentially obtained and verified from multiple storage media, the DDR initialization program is loaded, DDR is initialized, and the SPL secondary loading program is loaded to the DDR to run. The method comprises the following steps of: firstly, loading an SD (Secure Digital) card, then loading U-Boot firmware, completing initialization of residual hardware and security mirror verification, then detecting and verifying a kernel mirror format and Header information in the SD card, then loading a Linux kernel, an equipment tree and a ramdisk, mounting rootfs to an RAM (Random Access Memory) space, and mounting the SD card as a user data storage space. According to the method, high reliability of system guiding is ensured through the SPI NOR, large-capacity storage and flexible upgrading are achieved through the SD card, and the comprehensive performance of the embedded system in the aspects of reliability, storage expansibility and cost effectiveness is remarkably improved.

Systems and methods for autonomous space-mission coordination integrate ground-based prediction with on-orbit execution. A processing system in a ground station may ingest multi-source environmental data, produce near-term nowcasts through an prediction model, rank pending spacecraft tasks against current resource telemetry, select a high-value task subset, convert the subset into time-tagged command packets, and transmit the packets through a communications link. A processing system aboard each spacecraft may receive the packets, merge them into a persistent schedule, and at each time tag slews attitude, activate an imaging or radar sensor with specified parameters, capture data, and store the data in non-volatile memory. The spacecraft may generate quality metrics for the captured data and return the metrics to the ground station.

Exemplary methods and apparatus are provided for implementing a deep learning accelerator (DLA) or other neural network components within the die of a non-volatile memory (NVM) apparatus using, for example, under-the-array circuit components within the die. Some aspects disclosed herein relate to configuring the under-the-array components to implement feedforward DLA operations. Other aspects relate to backpropagation operations. Still other aspects relate to using an NAND-based on-chip copy with update function to facilitate updating synaptic weights of a neural network stored on a die. Other aspects disclosed herein relate to configuring a solid state device (SSD) controller for use with the NVM. In some aspects, the SSD controller includes flash translation layer (FTL) tables configured specifically for use with neural network data stored in the NVM.

Described are techniques for write protecting a non-volatile memory (NVM) after the contents of the NVM have been set. In some examples, a computing device or system having an NVM also includes a Root of Trust (RoT) configured to generate a write protect command as an input to the NVM. The RoT generates the write protect command in response to detecting a write protect signal from an electronic controller. The write protect command sets one or more areas in the NVM to be read-only. Further, the write protect command can make the one or more areas read-only on a power-on basis so that write protection is maintained until the next power cycle. The electronic controller can be configured to assert the write protect signal each time the computing device or system is powered on, for instance during a reboot, thereby causing the RoT to renew the write protection.

Methods, systems, and devices for front-to-front bonding in a stacked memory system are described. The stacked memory system may include a package substrate and a volatile memory die with a front side. The stacked memory system may also include a logic die with a front side that is bonded with the front side of the volatile memory die. The back side of the stacked memory system may be coupled with a conductive bump that in turn is coupled with the package substrate.

Techniques are disclosed for sending downloadable software packages that may be executed to perform tests of a network device without requiring the network device to update firmware. In one example, the network device obtains a software package comprising instructions for simulating a network instance and stores the software package in a volatile memory of the network device. The network device simulates, based on the instructions, the network instance to obtain data indicative of a performance of the network instance. The network device sends, via a communication channel established with a network management system (NMS) based on the software package, the data indicative of the performance of the network instance. In some examples, the NMS uses the data indicative of the performance of the network instance to identify a root cause of a failure of the network device or a remedial action to be performed upon the network device.

According to an embodiment, a method includes adjusting a reference generator into a first configuration based on a temporary trim value resulting, in a first reference voltage and a first reference current being generated for a first memory. The method further includes performing an integrity check on an initial set of data downloaded from the first memory based on the first reference voltage and the first reference current. The initial set of data includes a first trim value. The method further includes downloading contents from the first memory into a second memory in response to a successful integrity check after adjusting the reference generator into a second configuration. In the second configuration, the reference generator generates a second reference voltage and a second reference current for the first memory. The reference generator is adjusted by the first trim value in response to a successful integrity check.

A firmware management operation. The firmware management operation includes providing an information handling system with a distributed BIOS, the distributed BIOS including a BIOS component and a BIOS variable, the BIOS variable being stored within a firmware variable non-volatile memory store; instantiating a firmware variable transaction; and, authenticating, via a secure authenticated BIOS interface, the firmware variable transaction.

This disclosure is directed to circuits and techniques for configuring a driver circuit for a power switch when entering a fail-safe state. The driver circuit includes a volatile memory connected to a plurality of independent power supplies, the volatile memory configured to store a fail-safe configuration for the driver circuit. The driver circuit includes driver logic connected to the volatile memory that is configured to determine to enter a fail-safe state and, in response to determining to enter the fail-safe state, configure the driver circuit or a power switch according to the fail-safe configuration stored in the volatile memory.

A facility for predicting on site electric power requirements for maintaining a fully electric fleet of vehicles in a mining operation to ensure sustainable electric operations, comprising a server comprising communications module configured to receive data and to transmit load management instructions; plurality of electrical charging stations; plurality of electric vehicles configured to be recharged by a selected electrical charging station; wherein the server comprises processor coupled with non-volatile memory, the non-volatile memory storing processing instructions that, when executed by the processor, causes the processor to simulate a total electrical power demand of the mine site due to the plurality of cabled mine equipment and the plurality of electric vehicles for each electric vehicle and each charging station within the facility over a prescribed period thereby to simulate and determine an energy storage capacity requirement of the charging stations of the facility through the prescribed period; thereby to forecast the electrical load management needs of the facility through the prescribed period.

The invention discloses a key value storage system indexing method oriented to an NVM-NVMe SSD (Non-Volatile Memory-Non-Volatile Memory Express Solid State Disk) hybrid architecture, which comprises the following steps of: constructing a heterogeneous storage architecture taking cold and hot data perception as a core driving mechanism, coordinating and managing two types of storage media, namely a non-volatile memory NVM and a solid state disk NVMe SSD, and realizing efficient identification, layered writing and dynamic migration of cold and hot data. According to the method, the characteristics of low delay, durability and byte addressing of the NVM are utilized, the frequency and I / O overhead of Flush and Compaction operations are reduced in a data write-in path, meanwhile, the problem of mixed storage of cold and hot data is avoided, and therefore the overall performance and storage efficiency of a system are remarkably improved. In addition, by introducing an asynchronous migration module, the method can dynamically adapt to the change of data popularity along with time evolution, and effectively support high performance and high availability of the key value system in long-term operation.

Methods and apparatus are disclosed for implementing data augmentation within a storage controller of a data storage device based on machine learning data read from a non-volatile memory (NVM) array of a memory die. Some particular aspects relate to configuring the storage controller to generate augmented versions of training images for use in training a Deep Learning Accelerator of an image recognition system by rotating, translating, skewing, cropping, etc., a set of initial training images obtained from a host device and stored in the NVM array. Other aspects relate to controlling components of the memory die to generate noise-augmented images by, for example, storing and then reading training images from worn regions of the NVM array to inject noise into the images. Data augmentation based on data read from multiple memory dies is also described, such as image data spread across multiple NVM arrays or multiple memory dies.

The invention discloses a cost-effective solid state disk based on host end resource borrowing and a host. The hard disk comprises a nonvolatile memory, a memory resource, a CXL TSP characteristic module, a CXL driven communication module, a load detection module and a firmware binary code. The firmware binary code is stored in a nonvolatile memory and is used for executing a solid state disk management function by borrowing computing resources of a host after being uploaded to an enclave of the host; the communication module driven by the CXL is responsible for performing communication interaction with an SGX enclave in a host end; the CXL TSP characteristic module is used for ensuring confidentiality and integrity of communication interaction; the load detection module is used for monitoring the load of the I / O request, and when the load is higher than a threshold value, a daemon thread located at a host end is notified to load a firmware binary code to a host and start the host; the nonvolatile memory is used for storing data. According to the invention, efficient and safe host end resource use can be realized.

The invention relates to the technical field of hard disks, in particular to a data protection method of a solid state disk and the solid state disk, the method comprises the steps that a flash memory medium is divided into a data block area, a log block area and a metadata area, and the metadata area comprises a mapping directory, a mapping block and a check point block; a block mapping table and a log page mapping table are established in a volatile memory, and dbMSN and lbMSN are stored. Adding write-in data to a log block page, updating a log page mapping table, and generating check points according to full writing of a log area. When no free page exists, the damaged log blocks are selected in a rotating mode to be combined, new data block migration pages are distributed, mapping is updated, the MSN is progressively increased, changes are written into the mapping blocks, and the mapping catalogue is updated when the mapping blocks are addressed. After restarting, positioning a mapping block by a mapping directory to recover block mapping, reading check points in a reverse order, and traversing an uncovered log area to reconstruct log page mapping; and comparing the dbMSN with the lbMSN, setting inconsistent log pages to be invalid, establishing consistent access and shielding invalid pages. According to the method and the device, the problems of data consistency and availability caused by metadata loss, uncertain merging state and low recovery efficiency of the hybrid mapping FTL in a crash scene can be solved.

A non-transitory storage system is constructed based on the converged architecture system and includes: a plurality computing nodes in a computing resource pool, an adapter board, and a plurality of solid-state drives configured to establish a communication connection with the plurality of computing nodes through the adapter board to expand a storage resource pool. Through the foregoing design, the storage resource pool is expanded based on the third-generation converged architecture system and a bus interconnection technology, to achieve remote expansion of storage. In addition, the plurality of computing nodes share decoupled storage resources, thereby solving the problems that a storage capacity of conventional Just a Bunch of Flash (JBOF) may only be expanded to a limited extent and remote decoupled access to storage resources by a plurality of hosts is not capable to be achieved.

Technology for a hybrid memory system that allows host access both non-volatile storage and volatile memory (e.g., RAM). The hybrid memory system may send a command to the host requesting that the host select a mode of access that may include a first mode in which the host has access to only the volatile memory and a second mode in which the host has access to at least the non-volatile storage. While in a mode in which the host has access to the volatile memory, the hybrid memory system may analyze data packets received from the host to determine whether a data packet is a request to access the volatile memory or the non-volatile storage. Responsive to a determination that the host is seeking access to the volatile memory the hybrid memory system converts the packet from the host to a packet suitable to access the volatile memory.

A quasi-volatile memory (QV memory) stack includes at least one semiconductor die, having formed thereon QV memory circuits, bonded to a second semiconductor on which a memory controller for the QV memory (“QV memory controller”) is formed. The circuits in the bonded semiconductor dies are electrically connected using numerous copper interconnect conductors and conductive through-silicon vias (TSVs). The QV memory controller may include one or more interfaces to additional devices (“back-channel devices”) to enable the QV memory controller to also serve as a controller for each back-channel device and to provide additional services. The QV memory controller performs data transfers between a back-channel device and the QV memory without intervention by the host CPU.

The invention relates to a large model training method and device, electronic equipment, a storage medium and a program product. The method comprises the following steps: for any item of training data of a target large model, segmenting the training data into a plurality of parts of segmented data, storing the plurality of parts of segmented data in a nonvolatile memory, and sequentially performing forward propagation calculation and back propagation calculation on the plurality of parts of segmented data; for any part of segmented data, reading the segmented data from a nonvolatile memory to a video memory, and executing forward propagation calculation on the segmented data through a GPU (Graphics Processing Unit) to obtain an activation value corresponding to the segmented data; and for any part of segmented data, executing back propagation calculation based on the activation value corresponding to the segmented data through the GPU to obtain gradient data corresponding to the segmented data, and moving the gradient data corresponding to the segmented data from the video memory to a nonvolatile memory or a CPU memory. The display memory occupation of the activation value can be reduced.

A hardware apparatus for isolated virtual environments includes graphics processing unit comprising a first dedicated memory and a first plurality of processing cores, a central processing unit comprising a second dedicated memory and a second plurality of processing cores, a field programmable gate array comprising a third dedicated memory, a control and data bus assembly connecting the field programmable gate array, the central processing unit, and the graphics processing unit, and a hypervisor located on a non-volatile memory of the hardware apparatus, the hypervisor configured to create one or more virtual machines by isolating the graphics processing unit, the central processing unit and the field programmable gate array.

A non-volatile memory device includes a peripheral circuit structure including a peripheral circuit, a lower insulating structure, and lower bonding pads, a cell array structure having a cell region and a peripheral connection region, the cell array structure including an upper insulating structure contacting the lower insulating structure, an upper bonding pad bonded to the lower bonding pads, a cell stack in the cell region of the upper insulating structure, a common source line layer arranged on the cell stack and including a common source opening, a base insulating layer filling the common source opening and covering the common source line layer, and cell channel structures penetrating the cell stack and extending into the common source line layer, and a pad pattern extending from the peripheral connection region to the cell region and partially overlapping the common source opening in a vertical direction, on the cell array structure.

A system includes application processors (APs) at least some of which communicate over a network. The system includes a non-volatile memory device to store at least one of configuration data or firmware that is accessed by the APs. The configuration data or firmware enables operation of respective APs. The system includes a controller communicatively coupled to the APs and the non-volatile memory device. The controller is configured to centralize processing of messages received from the APs and to manage shared access to the non-volatile memory device by the APs.

Methods, systems, and devices for reconstructed semiconductor die evaluation in stacked memory architectures are described. A semiconductor device may be formed based on reconstructed wafers of operable dies. In some examples, a first side of an interface block may be bonded with one or more volatile memory stacks. The interface block may also be formed with one or more conductive pads in a second side of the interface block which may provide an evaluation interface for the interface block and the one or more volatile memory stacks. The second side of the interface block may then be bonded to a host chip, and the host chip may be operable to couple with the interface block and control one or more functions of the interface block and the one or more volatile memory stacks.