2053 results about "Volatile memory" patented technology

The invention relates to the technical field of computer system structures and storage, in particular to a non-volatile memory quick recovery method based on metadata priority and on-demand loading. The method comprises the following steps: in response to a system fault signal detected by a voltage monitoring unit, freezing a processor context and traversing a page table structure to extract system configuration information; writing the system configuration information and business data codes in the volatile memory into a nonvolatile medium to generate a persistent state mirror image; analyzing the persistent state mirror image, extracting address conversion metadata, and reconstructing a mapping relation from a virtual address to a physical page frame in a volatile memory; and generating an address mapping table, wherein the physical page frame pointed by the address mapping table is set to be in an existing state but is not associated with the effective service data. According to the method, decoupling of the control flow and the data flow is realized by constructing a virtual ready state, and quick starting of the system and immediate response of key services are realized on the premise of not depending on the total capacity of a memory.

This disclosure is directed to circuits and techniques for configuring a driver circuit for a power switch when entering a fail-safe state. The driver circuit includes a volatile memory connected to a plurality of independent power supplies, the volatile memory configured to store a fail-safe configuration for the driver circuit. The driver circuit includes driver logic connected to the volatile memory that is configured to determine to enter a fail-safe state and, in response to determining to enter the fail-safe state, configure the driver circuit or a power switch according to the fail-safe configuration stored in the volatile memory.

The invention discloses a key value storage system indexing method oriented to an NVM-NVMe SSD (Non-Volatile Memory-Non-Volatile Memory Express Solid State Disk) hybrid architecture, which comprises the following steps of: constructing a heterogeneous storage architecture taking cold and hot data perception as a core driving mechanism, coordinating and managing two types of storage media, namely a non-volatile memory NVM and a solid state disk NVMe SSD, and realizing efficient identification, layered writing and dynamic migration of cold and hot data. According to the method, the characteristics of low delay, durability and byte addressing of the NVM are utilized, the frequency and I / O overhead of Flush and Compaction operations are reduced in a data write-in path, meanwhile, the problem of mixed storage of cold and hot data is avoided, and therefore the overall performance and storage efficiency of a system are remarkably improved. In addition, by introducing an asynchronous migration module, the method can dynamically adapt to the change of data popularity along with time evolution, and effectively support high performance and high availability of the key value system in long-term operation.

The invention relates to the technical field of hard disks, in particular to a data protection method of a solid state disk and the solid state disk, the method comprises the steps that a flash memory medium is divided into a data block area, a log block area and a metadata area, and the metadata area comprises a mapping directory, a mapping block and a check point block; a block mapping table and a log page mapping table are established in a volatile memory, and dbMSN and lbMSN are stored. Adding write-in data to a log block page, updating a log page mapping table, and generating check points according to full writing of a log area. When no free page exists, the damaged log blocks are selected in a rotating mode to be combined, new data block migration pages are distributed, mapping is updated, the MSN is progressively increased, changes are written into the mapping blocks, and the mapping catalogue is updated when the mapping blocks are addressed. After restarting, positioning a mapping block by a mapping directory to recover block mapping, reading check points in a reverse order, and traversing an uncovered log area to reconstruct log page mapping; and comparing the dbMSN with the lbMSN, setting inconsistent log pages to be invalid, establishing consistent access and shielding invalid pages. According to the method and the device, the problems of data consistency and availability caused by metadata loss, uncertain merging state and low recovery efficiency of the hybrid mapping FTL in a crash scene can be solved.

The invention provides a firmware online upgrading method, embedded equipment, a medium and a product, and relates to the technical field of intelligent terminals. The method comprises the following steps: after the embedded equipment is powered on, running a primary bootstrap program, and checking a first mark state: if the state is a state of updating a secondary bootstrap program, executing online updating of the program and resetting a system; and if the state is the default state, loading and running the secondary bootstrap program. Checking a second mark state; if the second mark state is an updating mirror image state, executing firmware mirror image online updating and resetting; and if the state is the default state, determining a target mirror image, copying the target mirror image from the nonvolatile memory to the random access memory, and skipping to run. And the equipment simultaneously monitors the running state of the target mirror image in real time, and executes successful confirmation or abnormal recovery operation according to the state. In this way, quick response of faults is achieved through running state feedback, the stability and reliability of firmware upgrading of the embedded device are effectively improved, and the risk of device paralysis in the upgrading process is reduced.

The invention discloses a cache control system and a cache control method, and relates to the technical field of memorizers, the cache control system adopts the characteristics of low time delay and low energy consumption of a volatile cache module to realize high-performance cache of read-write data, and on the basis of adopting the volatile cache module, the cache of the read-write data is realized. A dirty queue module used for recording addresses of dirty cache lines in a volatile cache module is introduced, a counter used for recording the number of the dirty cache lines of the dirty queue module and a waterline threshold value is configured, the cache state is dynamically monitored, and then the cache state of the passive computing device is dynamically adjusted according to the number of the dirty cache lines and the waterline threshold value. According to the technical scheme, high-performance caching in a high-performance mode is met, non-volatile memory does not need to be accessed, asynchronous write-back operation is executed concurrently after the number of dirty cache lines reaches a waterline threshold value, caching of read-write data can continue to be achieved, and the cached read-write data can be written back to the non-volatile memory under the non-blocking condition.

Predictive block health assessment of a non-volatile memory can be performed by storing a pre-trained neural network for this purpose on the memory device itself. As operational errors occur during operation of the memory device, this defect data is saved by the non-volatile memory and used as input data for the neural network to identify and retire potential bad blocks before data loss occurs.

A method for dynamically estimating interference compensation thresholds of a page of memory includes performing a mock read on a target row using a mock read threshold, performing a read operation on an interference source and reading an interference state of the interference source, computing a histogram and a corresponding threshold based on the mock read threshold and the interference state of the interference source, and estimating a read threshold to dynamically compensate the interference state of the target row based on the histogram.

A trapezoidal approximation of the Arrhenius equation provides an accurate determination of an acceleration factor for aging, while using minimal storage. The current temperature is periodically sampled. Based on the current temperature, a previous temperature, and a reference temperature, an acceleration factor for the device is updated. Then the sampled temperature is stored in place of the previous temperature, for use in updating the acceleration factor in the next period. The remaining lifespan may be determined based on a reference lifespan and the acceleration factor. As a result, the benefits of more accurate lifespan prediction are obtained without the costs of storing a sequence of temperatures experienced by the device.

The present: invention addresses the problem of providing a silicon nitride etching liquid composition which is capable of selectively etching Si3N4 with a practical etching selectivity with respect to SiO2, while suppressing regrowth of SiO2, and which is also capable of suppressing pattern collapse of an SiO2 film in the production of a 3D nonvolatile memory cell. A silicon nitride etching liquid composition for producing a 3D nonvolatile memory cell, which contains phosphoric acid, one or more silane coupling agents and water, but which does not contain ammonium ions.

The invention provides a data recording method for a vehicle, which is executed by a second electronic control unit of the vehicle, and comprises the following steps: during operation of the vehicle, receiving to-be-recorded data related to an intelligent driving function from a first electronic control unit through the second electronic control unit of the vehicle in real time, the to-be-recorded data is non-duplicated data of data specified to be recorded in data recording requirements of the second electronic control unit, and the second electronic control unit has redundant power supply capability; and storing the received to-be-recorded data to the nonvolatile memory through the second electronic control unit in response to meeting a preset triggering condition. The invention further provides a data recording device for the vehicle and a computer program product. The intelligent driving data and the non-repetitive data of the EDR are transmitted to the second electronic control unit with redundant power supply in real time, so that bus overload can be avoided under the condition that an existing whole vehicle power supply framework is not changed, and the power-off storage requirement is met.

A method is disclosed for programming analog-valued weights in a non-volatile memory array using feedback-based estimation and adaptive pulse modulation. The method includes initializing a target weight, applying one or more programming pulses to a memory cell, estimating a weight state of the memory cell based on analog-to-digital conversion, determining a residual error between the estimated weight state and the target weight, and computing a subsequent programming pulse based on the residual error. The subsequent pulse may be adjusted by selecting a programming voltage from a quantized set of levels responsive to the recent weight response dynamics. The programming process may iterate until convergence may be achieved within a defined threshold. The technique supports precise control of conductance programming using closed-loop feedback and may be compatible with pulse-width, amplitude, and polarity modulation schemes.

The invention relates to the technical field of data acquisition and storage of underwater detection equipment, and discloses a dual-channel data storage and export method, device, equipment and medium, comprising: controlling a data acquisition unit to acquire an environmental analog signal and convert the environmental analog signal into a digital signal, and caching the digital signal to a volatile memory of a main control unit in real time; when it is monitored that the cache data size reaches a preset threshold value, the switching unit establishes a first communication path with the mass memory, writes the cache data in batches and enables the mass memory to enter a dormancy state; when an external reading instruction is received, the switching unit disconnects the first communication path and establishes a second communication path between the mass memory and the data reading unit to export the stored data. According to the method, the access times of the large-capacity memory are reduced and the working period is shortened by combining an independent data reading path through a batch writing mechanism triggered by a threshold value and dormancy control, so that the power consumption is remarkably reduced and the cruising ability of underwater equipment is improved.

Systems, methods, and a bridge device for a data storage device array that enables data transfer between data storage devices without transferring data to the host system are described. The bridge device receives a data transfer command from the host system, such as a fused read and write command, and converts it to separate read and write commands for the source and destination storage devices. The bridge device may operate in a non-volatile memory express over fabric (NVMe-oF) environment and manage the command queues, connection verifications, and command conversions to enable data transfer among storage devices connected to a shared peripheral component interface express (PCIe) root complex without using host network bandwidth or memory.

A multiturn angle detection device generates the multiturn absolute angle detection value of a rotating body. The multiturn angle detection device includes: a segment counter; a precision absolute angle detector; and an arithmetic device to generate the multiturn absolute angle detection value by combining the outputs of the segment counter and the precision absolute angle detector with each other. The segment counter includes: a single power generation sensor; a magnetic field generation source; a sensor element; and a nonvolatile memory to store a count value. The magnetic field generation source applies a k-cycle alternating magnetic field (wherein k is an integer not smaller than 3) per each turn of the rotating body axially of a magnetic wire. The arithmetic device uses the count value stored in the nonvolatile memory as it is, and combines the count value with the absolute angle detection value of the precision absolute angle detector.

The invention relates to the technical field of phase change liquid cooling energy storage, in particular to an immersed phase change liquid cooling battery thermal load dynamic modeling and prediction method, and the method comprises the steps: dividing the surface of a battery into n independent calculation regions based on the geometric structure and thermal characteristics of a battery module, static thermal resistance coefficients, dynamic thermal capacity coefficients and thermal diffusion weight coefficients of all the areas are simulated and calibrated through experiments and computational fluid mechanics, and a calibrated parameter matrix is stored in a nonvolatile memory of a BMS; the method comprises the following steps: acquiring battery temperature data at high frequency through a multi-source sensor network arranged in each partition, performing Kalman filtering and derivation calculation through a preprocessing module of a data processing layer to obtain a temperature change rate, calling a pre-stored coefficient by a regionalization modeling module, and calculating an instantaneous thermal load of each partition and a total thermal load of the module; a traditional'uniform temperature body 'hypothesis is broken through, a battery module is divided into a plurality of subareas, and the device is particularly suitable for capturing a non-uniform heat phenomenon caused by non-uniform flow field and local bubble generation under an immersed liquid cooling condition.

In some implementations, a memory apparatus may receive, from a host system, a first read command indicating first data, wherein the first read command includes a read ahead indication. The memory apparatus may obtain, based on the first read command including the read ahead indication, second data from a non-volatile memory location. The memory apparatus may store the second data in a volatile memory location.

The utility model discloses a dynamic signal acquisition circuit based on an FPGA kernel, and belongs to the technical field of signal acquisition. Comprising a field programmable gate array (FPGA) which is connected with a first synchronous dynamic random access memory (SDRAM), an ARM processor and a plurality of analog-to-digital converters (ADC). The input end of the analog-to-digital converter ADC is connected with the output end of the signal conditioning board; the input end of the signal conditioning board is connected with the dynamic acceleration sensor, the strain sensor and the displacement sensor and receives signals output by the sensors; the ARM processor is connected with a nonvolatile storage device FLASH and a second synchronous dynamic random access memory SDRAM; and the field programmable gate array FPGA is used for filtering and converting the acquired data and transmitting the data to the ARM processor. According to the utility model, synchronous acquisition, synchronous processing, synchronous analysis and synchronous transmission can be realized; the signal conditioning circuit adopts a modular design and can be compatible with sensors of various dynamic signals.

A computer express link fabric having: a plurality of computer express link switches; a plurality of computer express link connections among the computer express link switches; and a controller. The controller is configured to: map memory addresses in a mapped memory space to physical addresses of random access memory cells of memory devices connected to the computer express link fabric; and implement, in a storage space of a memory sub-system connected to the computer express link fabric and having non-volatile memory cells, a persistent copy of data stored by memory access requests received in the computer express link fabric and having memory addresses in the mapped memory space.

A non-volatile memory device includes a memory string, a select gate line coupled to the memory string, word lines coupled to the memory string and including a selected word line, and a control circuit coupled to the select gate line and the word lines, and configured to apply word line pre-pulse signals to at least two groups of the word lines disposed between the select gate line and the selected word line during a pre-charge period. The at least two groups of the word lines include a first group and a second group disposed between the first group and the select gate line. A voltage level of a second word line pre-pulse signal applied to the second group is greater than a voltage level of a first word line pre-pulse signal applied to the first group. A voltage level of at least one word line pre-pulse signal of the word line pre-pulse signals is greater than 0.

A non-volatile memory device comprises a substrate, a mold structure that includes gate electrodes stacked on the substrate and mold insulating layers alternately stacked with the gate electrodes, a cell contact on the substrate, wherein the cell contact is electrically connected to a selection gate electrode of the gate electrodes and is not electrically connected to a non-selection gate electrode of the gate electrodes, an insulating ring on the substrate, wherein the insulating ring is between the non-selection gate electrode and a sidewall of the cell contact and is in contact with the non-selection gate electrode, and a high dielectric constant layer between respective ones of the gate electrodes and the mold insulating layers, wherein the insulating ring includes a first portion that overlaps the high dielectric constant layer in a vertical direction, and a second portion that does not overlap the high dielectric constant layer in the vertical direction.

The invention belongs to the technical field of spaceflight electronic integrated circuits, and particularly relates to a satellite load FPGA configuration data error correction method and system capable of resisting single event upset, in particular to a bit-symbol double-layer error correction method of RS decoding operator error correction based on finite field algebra cascading on the basis of two-out-of-three majority voting logic. Single-particle independent upset and multi-copy common-mode failure can be corrected at the same time, and the problem of traditional TMR error locking is solved. Meanwhile, when configuration data are written into a nonvolatile memory, a cross-sector space staggered and dispersed storage mechanism is introduced, symbols in the same RS code word are separated as far as possible in physical positions, and therefore aggregated physical damage is converted into dispersed symbol-level errors.

A method of programming non-volatile memory cells comprising determining a target read current for respective ones of the memory cells based upon incoming data, associating respective ones of the memory cells with a respective one of a plurality of cell groups based upon the determined target read current for the respective memory cell being within a target read current range associated with the respective cell group, fast programming respective ones of the memory cells to a coarse target read current associated with the cell group to which the respective memory cell is associated, wherein the coarse target read current for respective ones of the cell groups is greater than the target read current range for the respective cell group, and then slow programming respective ones of the memory cells until the target read current determined for the respective memory cell is achieved.

An apparatus is provided that includes a memory array including non-volatile memory cells configured to store weights of an artificial neural network, a bit line coupled to a plurality of the non-volatile memory cells, and an interface circuit coupled to the bit line, the interface circuit configured to amplify an output impedance of the memory array.

In one example, a system comprises an array of non-volatile memory cells arranged in rows and columns, wherein each non-volatile memory cell comprises a word line terminal and a bit line terminal; and a row circuit to receive a row address and a bias voltage and to output the bias voltage when the row address corresponds to a row of the array associated with the row circuit, wherein the bias voltage is provided to terminals of non-volatile memory cells in the row of the array associated with the row circuit.

This application is directed to resource management in a storage system that includes a non-volatile memory and a collection of resources having one or more processing cores. The storage system allocates a first subset of resources to process queues of I / O access operations requested by a host device. The first subset of resources includes a storage controller corresponding to a subset of processing cores. The storage system obtains a first request for adjusting resource allocation of the storage device, and the first request includes a target performance requirement for processing the queues of I / O access operations. The storage system determines that the target performance requirement can be satisfied by allocation of at least a target subset of resources. In response to the first request and based on the target subset of resources, a second subset of resources is allocated for processing the one or more queues of I / O access operations.

In one example, a system comprises a vector-by-matrix multiplication array comprising non-volatile memory cells arranged into rows and columns; and an output block coupled to the vector-by-matrix multiplication array to receive current from the columns of the array, the output block comprising a current-to-voltage converter to receive current from one or two columns and convert the current into a voltage, the current-to-voltage converter comprising one or more variable resistors configurable to adjust the range of the voltage; and an analog-to-digital converter to convert the voltage into digital bits.

Apparatuses, systems, and methods for dynamic self-refresh rate in volatile memory are disclosed. An example memory device determines a number of refresh operations performed between self-refresh exit and subsequent self-refresh entry, and the memory device determines a self-refresh rate based on the number of refresh operations. In some examples, the memory device selects a refresh rate curve from a plurality of refresh rate curves to determine the self-refresh rate. In some examples, the memory device selects a refresh rate curve for auto-refresh, which is applied to determine timing of self-refresh operations, when no refresh operations or few refresh operations were performed between the self-refresh exit and the subsequent self-refresh entry.

Disclosed are a service lifetime monitoring and early warning method, a memory storage device, and a memory control circuit unit. The method includes: reading a history information from a rewritable non-volatile memory module, calculating a remaining lifetime based on the history information and a user habit, generating an early warning signal, and outputting the remaining lifetime and the early warning signal in response to the remaining lifetime being lower than a preset lifetime.

Devices, systems, and methods for improving performance of a non-volatile memory are described. An example method includes generating, based on a number of program erase cycles of the non-volatile memory, an inversion seed for a page type of the non-volatile memory, and then generating a circular shift flip sequence based on the inversion seed and a flip sequence. The method further includes performing a bit-flipping operation on an input bit sequence based on the circular shift flip sequence to generate an intermediate bit sequence, processing the intermediate bit sequence to generate an output bit sequence, and finally, writing the output bit sequence to a page in the non-volatile memory. In this example, the page that the output bit sequence is written (or programmed) to is of the page type for which the inversion seed and circular shift flip sequence are generated.