274 results about "Dram" patented technology

The invention relates to the technical field of DRAM (Dynamic Random Access Memory) dynamic repair, in particular to a DRAM dynamic repair method based on unit damage trend identification. The method comprises the following steps: receiving a logic address request sent by a CPU (Central Processing Unit), sending a reading command to a DRAM (Dynamic Random Access Memory), and obtaining return data and ECC (Error Correction Code When a single-bit error is detected, the error is corrected according to ECC verification data, correct data is returned, meanwhile, the damage trend of a surrounding area is pre-judged based on physical correlation of DRAM unit damage, a DRAM address and the surrounding area are marked as isolation addresses, and the data are moved to an SRAM; establishing a repair mapping table in the SRAM, and writing the repair mapping table into the nonvolatile memory through the bus interface; reading the mapping table during cold start of the system, judging whether the address is an isolation address or not according to the mapping table in subsequent access, and if yes, accessing the SRAM to obtain data. According to the invention, a single-bit error is prevented from being evolved into a multi-bit error, and the system reliability is improved.

The invention discloses an IC (integrated circuit) chip packaging detection method for realizing system-in-package and 3D (three-dimensional) packaging, which relates to the technical field of chip packaging detection, and comprises the following steps: vertically stacking a plurality of DRAM (dynamic random access memory) core particles on a basic logic core particle with a micro-bump array on the surface through silicon through holes, and activating a self-detection circuit to obtain a suspicious area coordinate list; dividing regional risk levels through a targeted scanning scheduling algorithm, and generating a differentiated scanning parameter set; for each suspicious area, controlling an external X-ray source to collect multispectral projection data according to the differential scanning parameter set; performing three-dimensional reconstruction on the multiple groups of multispectral projection data by using an enhanced reconstruction model embedded with physical priori knowledge to obtain enhanced three-dimensional body data; and performing automatic defect identification on the enhanced three-dimensional body data, and outputting the identified defect as a detection result. The invention aims to solve the problems of difficulty in perspective imaging and insufficient resolution of internal defects of the high-density 3D stacked chip.

The invention belongs to the technical field of semiconductor testing, and particularly relates to an HBM-DRAM grouping testing system and method, and the system comprises a main testing controller and a plurality of testing execution units configured in the system. And the main test controller is in communication connection with the plurality of test execution units through a preset test coordination bus. By physically segmenting the test interface into a plurality of independent, low-needle-count probe card modules, challenges of designing and manufacturing a single, huge, ultra-high-needle-count probe card are fundamentally avoided. Therefore, the manufacturing cost, the calibration difficulty and the maintenance cost of each probe card module are greatly reduced, and the overall yield and the service life of the probe card are remarkably improved.

The invention relates to the technical field of DRAM (Dynamic Random Access Memory) repairing, in particular to a DRAM failure unit repairing method based on SOC (System On Chip) driving mapping adjustment. The method comprises the following steps: detecting a physical address of a failed CELL unit in a DRAM particle through test equipment, and generating repair mapping data; recording the repair mapping data on the surfaces of the DRAM particles in a two-dimensional code form and storing the repair mapping data in a nonvolatile memory; loading the repair mapping data to a driving program when the SOC is started; and synchronously modifying the address mapping relationship between the MMU and the IOMMU through a driving program, and redirecting the access to the invalid physical address to the standby physical address. By modifying MMU and IOMMU mapping on a driving layer at the same time, unified address remapping of access paths of CPU and DMA equipment is achieved, DRAM particles containing failure units can be used in a capacity reduction mode, PCBA cost is greatly reduced, hardware modification is not needed, and implementation is flexible.

The invention discloses a data processing method and electronic equipment, relates to the technical field of computers, and aims to realize hot data preliminary screening through performance data, refine access features by compressing a heat map, dynamically update a heat score, and realize dynamic classification and hierarchical storage of data by comparing a target threshold with the heat score. According to the method and the device, the distribution of the data between the DRAM and the CXL memory is completed, and the technical effects of accurately identifying the hot data and optimizing the storage position are achieved on the premise of ensuring low overhead, so that the overall performance of the system is improved.

The invention belongs to the field of Transform model acceleration, and discloses a hybrid bonding 3D stacked accelerator and acceleration method oriented to Transform reasoning, the accelerator adopts a 3D stacked architecture, and comprises a DRAM storage bare chip and a logic bare chip, the DRAM storage bare chip comprises 16 DRAM storage blocks, the logic bare chip comprises 16 processing groups, each processing group corresponds to one DRAM storage block, and the processing groups correspond to the DRAM storage blocks. Each processing group is integrated with two attention processing units, and the DRAM storage blocks are connected with the processing groups through 32 copper-copper hybrid bonding vertical channels. According to the method, the problems of dense calculation and high memory bandwidth requirement in the reasoning process are solved, efficient model reasoning acceleration is realized, and the method is suitable for natural language processing, computer vision, video analysis and other application scenes depending on the Transform model.

An exemplary device and method for detecting and mitigating data-disturbance errors in a DRAM array, including Row-Press exploits or phenomenon as well as Rowhammer exploits or phenomenon. By mitigating both types of disturbance errors, the exemplary device and method can comprehensively protect DRAM from various vulnerabilities and enhancing its reliability, and doing so, with minimal hardware overhead addition. The exemplary device and method can be integrated with circuitries employed for Row-Press and Rowhammer detection and correction. The exemplary device and method can employ a counter as a proxy to detect when a Rowhammer threshold is met. In some embodiments, the Row-Press detection circuit can trigger an increment (whole or fractional) to the Rowhammer counter.

The invention discloses a flash memory and near memory acceleration system of an end-side large language model, and belongs to the technical field of calculation, reckoning or counting. According to the system, a 3D NAND flash memory chip with near memory computing capability is adopted, and model weights and key value caches are uniformly stored in the flash memory. Storage-intensive operations involved in the big language model inference decoding stage are all completed in a logic layer of a flash memory, and an NPU only executes non-linear operations such as normalization and activation and residual connection; in the pre-filling stage, the NPU obtains weight and key value cache data from the flash memory and is used for completing all calculations. Redundant read-write is reduced through a flash memory page-level key value cache mapping mechanism; and meanwhile, attention head group parallel data stream optimization is provided, so that the parallelism of a decoding stage is improved. A discrete framework and a compact framework are further provided, and optimal configuration is automatically selected in combination with a design space exploration strategy. According to the method, the requirement of edge end large language model reasoning on the DRAM can be omitted, delay is reduced, throughput is improved, and system cost and power consumption are remarkably reduced.

Overhang architectures for high bandwidth memory (HBM) multi-die assemblies and methods for making same. The overhang architecture places the DRAM (HBM) underneath the top IC die. The signal interconnects between the top IC die and the DRAM die are direct signal interconnects without lateral routing on a package substrate or on a motherboard.

A three-dimensional (3D) stacked memory package is described. The 3D stacked memory package includes a first plurality of stacked memory dies. The 3D stacked memory package also includes a first base die stacked on the first plurality of stacked memory dies. The 3D stacked memory package further includes a package substrate supporting the first plurality of stacked memory dies. The 3D stacked memory package also includes a first plurality of through silicon vias (TSVs) extending between the first plurality of stacked memory dies and a first compute block on the first base die. The 3D stacked memory package further includes a first set of wire-bonds coupled between the package substrate and a first physical IO interface (PHY) on the first base die.

The invention discloses an R-tree spatial index design method oriented to a DRAM-NVM hybrid storage architecture, relates to the technical field of computer data storage, and provides a write optimization spatial index HR-Tree under the DRAM-NVM hybrid architecture. The core design thought is that internal nodes are deployed on a DRAM, leaf nodes are placed on an NVM, and a targeted data read-write operation process is designed; in the aspect of an index structure and an operation mechanism, a minimum expansion strategy is adopted around a scene of less reading and more writing, a leaf node data structure and an in-situ updating algorithm on the NVM are designed in a targeted manner, and the write request processing efficiency can be improved on the premise of ensuring data consistency. And the multi-character data expansion and efficient fault recovery are provided, so that the actual requirements of the user are better met by allowing more flexible personalized configuration and shortening the service pause time. The method is suitable for the application fields of computer technology, database technology, data storage and the like.

A stacked system-on-chip (SoC) is described. The stacked SoC includes a first memory die comprising a dynamic random-access memory (DRAM). The stacked SoC also includes a compute logic die. The compute logic die comprises a static random-access memory (SRAM) having a first SRAM partition and a second SRAM partition. The first memory die is stacked on the compute logic die. The compute logic die includes a memory controller. The memory controller is coupled between the first SRAM partition and the second SRAM partition. Additionally, the memory controller is coupled to a DRAM bus of the first memory die.

The invention provides a DRAM (Dynamic Random Access Memory) data reading time sequence calibration method and device, and the method comprises the steps that in a DRAM initialization stage, a DRAM controller writes specific data into a fixed address, sends a reading instruction, and receives a fed-back data gating signal and a data signal; carrying out delay processing on the data strobe signal, delaying the data strobe signal into a plurality of data strobe signals with different delay values, and selectively outputting the data strobe signals by using a multiplexer; the asynchronous FIFO module is used for receiving a data signal, and the multiplexer selects an output data strobe signal as a write clock signal of the asynchronous FIFO module; after the asynchronous FIFO module receives the data signal, a DARM system clock signal is used as a read clock signal of the FIFO module, and FIFO read data is output; and comparing the FIFO read data with target data, and when the comparison result is inconsistent, adjusting a control signal of the multiplexer until the comparison result of the FIFO read data and specific data is consistent.

A three-dimensional (3D) stacked memory package is described. The 3D stacked memory package includes a first plurality of stacked memory dies. The 3D stacked memory package also includes a first base die stacked on the first plurality of stacked memory dies. The 3D stacked memory package further includes a package substrate supporting the first plurality of stacked memory dies. The 3D stacked memory package also includes a first plurality of through silicon vias (TSVs) extending between the first plurality of stacked memory dies and a first compute block on the first base die. The 3D stacked memory package further includes a first set of wire-bonds coupled between the package substrate and a first physical IO interface (PHY) on the first base die.

The invention discloses an automatic wiring method for a gold-plated lead of a DRAM (Dynamic Random Access Memory) packaging substrate, and relates to the technical field of DRAM packaging substrate design. The method comprises the steps of structured data input, VBA intelligent coordinate calculation, network screening and duplicate removal, wiring instruction set generation, script automatic generation, automatic execution and graph generation. Basic data are input through a standardized Excel template, a VBA program automatically completes calculation of bonding wire angles and lead coordinates and duplicate network de-duplication, then the bonding wire angles and the lead coordinates are converted into Allegro scripts, and gold-plated leads are drawn in batches in Allegro software. According to the method, a traditional manual design mode is replaced, the wiring efficiency is greatly improved, the problem of lead omission or redundancy caused by human negligence is avoided, the design flexibility and the change response capability are enhanced, and the accuracy and reliability of gold-plated lead design are guaranteed.

The DRAM temperature monitoring self-refresh circuit and the DRAM provided by the embodiments of the present disclosure comprise: a self-refresh enabling module, which outputs a clock signal to a reference voltage generating module and a logic module upon receiving a self-refresh enabling signal; the reference voltage generating module determines a first clock sampling signal according to the received clock signal, and generates a reference voltage to a comparison module according to the first clock sampling signal; the comparison module outputs a comparison signal to the logic module according to the reference voltage and a diode voltage; the logic module generates a sampling signal to collect the first clock sampling signal of the reference voltage generating module at a first time according to the clock signal and the comparison signal when the comparison signal is at a high level, so as to generate a temperature identification signal according to the first clock sampling signal, and determine a chip refresh clock according to the temperature identification signal and the clock signal, and generates a reset signal to the reference voltage generating module at a second time, so as to reset the first clock sampling signal of the reference voltage generating module.

Disclosed herein are approaches for forming a dynamic random-access memory device (DRAM). One DRAM device may include plurality of pillars extending from a base layer, and a spacer layer formed along just a lower portion of each of the plurality of pillars. The DRAM further includes a body contact and a cap between the plurality of pillars, wherein the body contact is formed over the spacer layer, and a gate formed around the plurality of pillars. The DRAM further includes a bottom source / drain formed in the base layer and a top source / drain formed in each pillar of the plurality of pillars, wherein the top source / drain extends above the gate.

Method for operating a dynamic low-power double data rate 5 direct access memory, LPDDR5 DRAM, in a multi-rank memory system (10) which includes a plurality of memory ranks (RNK1 - RNKM), wherein the method includes the following steps: Receiving a write command intended for a first memory rank (RNK1) from the plurality of memory ranks (RNK1 - RNKM), wherein the write command corresponds to an LPDDR5 standard and is not intended for a second memory rank (RNK2) from the plurality of memory ranks (RNK1 - RNKM); Activating a receive buffer (720, BF1) in the first memory rank (RNK1); Disabling a transfer driver (710, DR1) in the first memory rank (RNK1); Disabling a receive buffer (720, BF2) and a transmit driver (710, DR2) in the second memory rank (RNK2); Receiving a data strobe signal pair (WCK_T, WCK_C); Activating (S200) on-die terminal, ODT, circuits (300) of the first memory rank (RNK1) and the second memory rank (RNK2) in response to the write command; Receiving data signals while the data strobe signal pair (WCK_T, WCK_C) is toggled during the activation of the ODT circuits (300) of the first memory rank (RNK1) and the second memory rank (RNK2); Receiving a read instruction intended for the first memory rank (RNK1), where the read instruction conforms to the LPDDR5 standard and is not intended for the second memory rank (RNK2); Enabling the transfer driver (710, DR1) in the first memory rank (RNK1); Disable the receive buffer (720, BF1) in the first memory rank (RNK1); Disable the receive buffer (720, BF2) and the transmit driver (710, DR2) in the second memory rank (RNK2); Disable (S300) the ODT circuit (300) of the first memory rank (RNK1) and enable the ODT circuit (300) of the second memory rank (RNK2) in response to the read command; and Sending data signals while the data strobe signal pair (WCK_T, WCK_C) is toggled during the disabling of the ODT circuit of the first memory rank (RNK1) and the enabling of the ODT circuit (300) of the second memory rank (RNK2).

The application discloses a stability test method, device, equipment and storage medium of a DRAM particle. The method comprises the following steps: restarting a test system for a preset number of times, executing a preset test strategy in a universal boot loader stage of each test system starting process, the preset test strategy comprising the following steps: enabling a CPU cache, and configuring the CPU to access the DRAM particle in a non-burst transmission mode; based on hardware configuration information of the DRAM particle, allocating at least two test areas in an address space of the DRAM particle; traversing each working frequency supported by the test system, testing the read-write stability of the DRAM particle in direct read-write under each working frequency based on the at least two test areas, and testing the read-write stability of the DRAM particle after the test system enters a sleep mode and wakes up under each working frequency. The application has the technical effect of providing sufficient test pressure by using the CPU cache and avoiding external interference after the system is completely started, and effectively improves the comprehensiveness and accuracy of the DRAM particle stability test.

A DRAM is provided, which includes a silicon substrate, buried word lines and active regions. The silicon substrate has a carrier surface. The buried word lines are buried in the silicon substrate. The active regions are located on the carrier surface. The buried word lines intersect the active regions. Each buried word line has a first width in one of the active regions and a second width outside the active regions, and the first width is greater than the second width. A manufacturing method of the DRAM is also provided. By the above configuration of the DRAM, word line disturbance and single cell failure can be reduced, and the density of the DRAM can be improved.

Methods and devices related to sharing data between computing devices are described. In an example, a method can include writing a first portion of data to a DRAM on a first computing device, receiving, via a radio of the first computing device, first signaling representing a request to share the first portion of data via a first processing resource of the first computing device with a second processing resource of a second computing device, determining at the first processing resource of the first computing device to share the first portion of data with the second processing resource of the second computing device based on at least one of: a command from a user or data representing user settings stored in non-volatile memory on the first computing device, and transmitting, via the radio of the first computing device, second signaling comprising the first portion of data to the second processing resource of the second computing device.

Methods and apparatus for mapping memory allocation to DRAM dies of a stacked memory modules are described herein. Memory address ranges in a module employing 3DS (three dimensional stacked) DRAMs (Dynamic Random Access Memories) comprising stacked DRAM dies are mapped to DRAM dies in the module based on a layer of the DRAM dies, where dies in different layers have different thermal dissipation characteristic. Chunks of the memory address range are allocated to software entities such as virtual machines (VMs) and / or applications based on a memory access rate of the VMs / applications and the thermal dissipation characteristics of the DRAM die layers, wherein VMs / applications with higher memory access rate are allocated memory on DRAM dies with higher thermal dissipation. In one aspect, memory ranks are associated with respective die layers. In response to detection of change in access rates, memory may be migrated between ranks. Interleaving at multiple levels is also supported.

The invention belongs to the field of GPGPU chip design, and particularly relates to a GPGPU thread block scheduling method and system based on data space locality, and the method comprises the steps: carrying out the statistics of Bank feature information of access data of all thread blocks, and classifying the thread blocks accessing the same Bank into the same Bank group according to the Bank feature information; preferentially distributing the thread blocks of the same Bank group to the same programmable multiprocessor until the resources of the programmable multiprocessor are saturated; setting a private row cache space for each Bank in each programmable multiprocessor; when the data in the private line cache space is updated, synchronously updating the corresponding data in the L1 cache, the L2 cache and the DRAM; counting the hit rate of the private line cache in real time, and closing the private line cache function when the hit rate is lower than a preset threshold value. High-delay external storage access is reduced, the data reuse rate is improved, and the execution efficiency is remarkably improved.

This invention relates to a dynamic memory management device and method for high-level synthesis. The device includes at least several search cache modules and several modification write-back modules. The search cache modules are connected to DRAM storage modules and BRAM cache modules, respectively. The modification write-back modules are also connected to DRAM storage modules and BRAM cache modules, respectively. The BRAM cache modules cache node information on the search path and temporarily store modification information for nodes. The search cache modules read node data from the DRAM storage modules and write it to the BRAM cache modules based on received operators and node addresses. The modification write-back modules read node data from the BRAM cache modules and write it back to the DRAM storage modules. Addressing the low execution efficiency of directly porting traditional operating systems to FPGAs, this invention leverages the large capacity of DRAM on FPGAs to achieve efficient dynamic memory allocation and reclamation, improving the ease of use and code reusability for high-level synthesis.

Memory module, computing device, and methods of reading and writing data to the memory module are disclosed. A memory module, comprises one or more dynamic random-access memories (DRAMs); and a processor configured to select a Central Processing Unit (CPU) or the processor to communicate with the one or more DRAMs via a memory interface.

The application discloses a hybrid memory-based NUMA-aware key-value storage system and an operating method, and belongs to the field of key-value storage. The system comprises a plurality of NUMA nodes; in the PM of each NUMA node, key-value pair data is written in the form of log items into a log file; a first storage area in the DRAM of each NUMA node constitutes a volatile index layer and is used for storing the address information of the log item where the key and the latest value are located; a second storage area in the DRAM of each NUMA node constitutes a RAF cache and is used for caching key-value pair data; the higher the access frequency and the higher the delay of the NUMA node initiating an access request to access the PM of the NUMA node where the key-value pair data is located, the greater the corresponding cache benefit; when the RAF cache is replaced, the entry with the smallest cache benefit is selected for replacement. The application can optimize the PM access performance across NUMA nodes and provide efficient key-value storage services.

A test and measurement instrument includes one or more test channels to connect to a memory device under test (DUT) and analyze signals generated by the DUT, and one or more processors configured to execute code to cause the DUT to generate strobe and data signals using a first clock setting of the DUT, determine whether the period of the strobe signal and data signals are within a tolerance specification, and perform at least one additional measurement of the DUT when the period of the strobe and data signals are within the tolerance specification. Methods are also described.

A memory controller for a dynamic random-access memory (DRAM) is disclosed. The memory controller includes control circuitry that is configured to transmit, via a command / address (CA) interface, a command to place the DRAM into a mode that causes the DRAM to perform a self-refresh operation. The memory controller is configured to receive address information recorded by the DRAM while operating in a test-during-self-refresh mode. The address information identifies memory cells internally read and evaluated for an error by the DRAM during the self-refresh operation.

The invention particularly relates to a layout conversion method for multi-level storage. According to the layout conversion method oriented to the multi-level storage, the storage capacity is from small to large, the access delay is from low to high, and the layout conversion method is divided into a register level, an SRAM level and a DRAM level; the method comprises the following steps of: firstly, determining a matrix multiplication task and a partitioning strategy, storing data in a DRAM (Dynamic Random Access Memory) in a Tile layout, then loading the data from an SRAM (Static Random Access Memory) into the SRAM in a Swizzle layout form, and finally loading the data from the SRAM into a specific register and completing calculation, so that a calculation unit can read the data from the register without waiting. According to the layout conversion method oriented to multi-level storage, continuous memory access reading is achieved by conducting layout conversion among different storage levels, the problem of plate conflict is solved, and meanwhile the DRAM bandwidth utilization rate and the access parallelism degree on an SRAM are improved through continuous memory access.

This invention relates to the field of embedded system firmware technology, and discloses a method, system, and related products for implementing adaptive firmware for multiple DRAM types in embedded SoCs. Addressing the problems of existing technologies where each DRAM requires its own independent firmware, leading to high development and maintenance costs, version inconsistencies, and weak supply chain adaptability, this invention leverages the differences in operating voltages of different DRAMs under the JEDEC standard. It uses an ADC to collect the DRAM interface voltage, automatically identifies the DRAM type, and calls the corresponding initialization code, enabling a single firmware set to adapt to multiple DRAMs. This solution significantly reduces firmware development and maintenance costs, simplifies version management, improves the system's adaptability to DRAM supply chain fluctuations, and enhances product manufacturing flexibility. It can be widely applied to various embedded SoC products.