644 results about "Dram" patented technology

Standard memory circuits are used for executing a sum-of-products function between data stored in the memory and data introduced into the memory. The sum-of-products function is executed in a manner substantially similar to a standard memory read operation. The memory circuits are standard or slightly modified SRAM and DRAM cells, or computing memory arrays (CAMs).

A semiconductor memory device may have a DRAM cell mode and a non-volatile memory cell mode without a capacitor, including multiple transistors arranged in an array and having floating bodies, word lines connected to gate electrodes of the transistors, bit lines at a first side of the gate electrodes connected to drains of the transistors, source lines at a second side of the gate electrodes, different from the first side, and connected to sources of the transistors on the semiconductor substrate, and charge storage regions between the gate electrodes and the floating bodies.

A one-transistor, floating-body (1T/FB) dynamic random access memory (DRAM) cell is provided that includes a field-effect transistor fabricated using a process compatible with a standard CMOS process. The field-effect transistor includes a source region and a drain region of a first conductivity type and a floating body region of a second conductivity type, opposite the first conductivity type, located between the source region and the drain region. A buried region of the first conductivity type is located under the source region, drain region and floating body region. The buried region helps to form a depletion region, which is located between the buried region and the source region, the drain region and the floating body region. The floating body region is thereby isolated by the depletion region. A bias voltage can be applied to the buried region, thereby controlling leakage currents in the 1T/FB DRAM cell.

A single transistor DRAM cell is formed in a SOI substrate so that the DRAM cells are formed in bodies that are electrically isolated from each other. Each cell has doped regions that act as source and drain contacts. Between the drain contact and the body is a region, which aids in impact ionization and thus electron/hole formation during programming that is the same conductivity type as the body but of a higher concentration than the body. Adjacent to the source contact and to the body is a region, which aids in diode current during erase, that is the same conductivity type as the source contact but of a lower concentration than the source contact.

A flash drive has increased endurance and longevity by reducing writes to flash. An Endurance Translation Layer (ETL) is created in a DRAM buffer and provides temporary storage to reduce flash wear. A Smart Storage Switch (SSS) controller assigns data-type bits when categorizing host accesses as paging files used by memory management, temporary files, File Allocation Table (FAT) and File Descriptor Block (FDB) entries, and user data files, using address ranges and file extensions read from FAT. Paging files and temporary files are never written to flash. Partial-page data is packed and sector mapped by sub-sector mapping tables that are pointed to by a unified mapping table that stores the data-type bits and pointers to data or tables in DRAM. Partial sectors are packed together to reduce DRAM usage and flash wear. A spare/swap area in DRAM reduces flash wear. Reference voltages are adjusted when error correction fails.

A monolithic 3-D dynamic memory structure includes independently addressable strings of dual-gate devices. In each dual-gate device charge is deliberately stored on one side of the dual-gate. Although the stored charge may leak away, the stored charge in a dual-gate device of the present invention need only be refreshed at much longer intervals than conventional DRAM cells.

A DRAM command scheduling algorithm is presented that is designed to alleviate various constraints imposed upon high performance, high datarate, short channel DDRx SDRAM memory systems. The algorithm amortizes the overhead costs of rank-switching time and schedules around the t_FAW bank activation constraint. A multi-rank DDRx memory system is also presented having at least two ranks of memory each having a number of banks and at least one memory controller configured for performing the hardware-implemented step of DRAM command scheduling for row access commands and column access commands. The step of command scheduling includes decoupling the row access commands from the column access commands; alternatively scheduling the decoupled row access commands to different ranks of memory; and group scheduling the decoupled column access commands to each bank of the number of banks of a given rank of the different ranks of memory.

A semiconductor memory device comprises select transistors formed on side surfaces of plural silicon columns defined by a grid-like trenches on a surface of a silicon substrate, each select transistor having a source and a drain on the top surface and the bottom of the silicon column. A capacitor is formed on the top surface of the silicon column to form a DRAM cell. The source/drain layers on the bottom of a greater number of memory cells are commonly connected, or the source/drain layers on the bottom of adjacent memory cells are commonly connected, to be brought out to the surface of the silicon substrate by a connection line to be connected to a constant voltage or a bit line.

A memory cell that has first and second fully depleted transfer devices each having a body region and first and second diffused electrodes. The cell has a differential storage capacitor having at least one node abutting and in electrical contact with one of the first and second diffused electrodes of each of the transfer devices. The storage capacitor has a primary capacitance and a plurality of inherent capacitances, wherein the primary capacitance has a capaictive value that is at least approximately five times greater than that of the plurality of inherent capacitances.

Structures and methods for memory cells having a volatile and a non-volatile component in a single memory cell are provided. The memory cell includes a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposes the channel region and separated therefrom by a gate oxide. A control gate opposes the floating gate. The control gate is separated from the floating gate by a low tunnel barrier intergate insulator. The memory cell is adapted to operate in a first and a second mode of operation. The first mode of operation is a dynamic mode of operation and the second mode of operation is a repressed memory mode of operation.

A Dynamic Random Access Memory (DRAM) performs read, write, and refresh operations. The DRAM includes a plurality of sub-arrays, each having a plurality of memory cells, each of which is coupled with a complementary bit line pair and a word line. The DRAM further includes a word line enable device for asserting a selected one of the word lines and a column select device for asserting a selected one of the bit line pairs. A timing circuit is provided for controlling the word line enable device, the column select device, and the read, write, and refresh operations in response to a word line timing pulse. The read, write, and refresh operation are performed in the same amount of time.

A contact structure in a semiconductor device including a dynamic random access memory (DRAM) and a method of forming the same are provided. The contact structure, which is formed in a peripheral circuit area or a logic circuit area of a semiconductor device including a DRAM having a cell array area with a plurality of DRAM cells and the peripheral or logic circuit area, includes a lower interconnection formed of the same material as a capacitor upper electrode of each of the plurality of DRAM cells; an interlayer dielectric layer formed on the lower interconnection and having a contact hole exposing a predetermined portion of the lower interconnection; and an upper interconnection formed on the interlayer dielectric layer and electrically connected to the lower interconnection through the contact hole. The lower portion of the lower interconnection has a larger area than the bottom of the contact hole and extends downward so that the lower interconnection has a T-shape in a cross-section view. By forming the lower interconnection under a shallow contact hole to have a T-shape extending downward when forming contact holes having a large difference in depth, the lower interconnection can be prevented from being pierced when the contact holes are formed. Consequently, stable and uniform contact resistance can be obtained.

A vertical one-transistor, floating-body DRAM cell is fabricated by forming an isolation region in a semiconductor substrate, thereby defining a semiconductor island in the substrate. A buried source region is formed in the substrate, wherein the top/bottom interfaces of the buried source region are located above/below the bottom of the isolation region, respectively. A recessed region is etched into the isolation region, thereby exposing sidewalls of the semiconductor island, which extend below the top interface of the buried source region. A gate dielectric is formed over the exposed sidewalls, and a gate electrode is formed in the recessed region, over the gate dielectric. A drain region is formed at the upper surface of the semiconductor island region, thereby forming a floating body region between the drain region and the buried source region. Dielectric spacers are formed adjacent to the gate electrode, thereby covering exposed edges of the gate dielectric.

Power consumption of a mobile communication device is reduced by disabling refreshing of unused portions of DRAM. DRAM includes multiple separately refreshable memory refresh ranges (MRRs). A memory refresh manager (MRM) within the device's operating system identifies ranges of virtual memory that will not be used during subsequent sleep mode operation. The MRM remaps virtual to physical memory space to conglomerate the physical memory pages (associated with virtual memory that will not be used) in certain MRRs such that the contents of entire MRRs need not be maintained in sleep mode. Information in any remapped physical page that needs to be maintained during sleep mode is copied so that it resides at the same virtual address after the remapping as before. Other software operates in virtual memory space and is not affected by the remapping. Refreshing of the certain MRRs is then disabled for sleep mode, thereby reducing power consumption.

A Programmable Logic Device (PLD) is provided with configuration memory cells displaying a superior soft error immunity by combating single event upsets (SEUs) as the configuration memory cells are regularly refreshed from non-volatile storage depending on the rate SEUs may occur. Circuitry on the PLD uses a programmable timer to set a refresh rate for the configuration memory cells. Because an SEU which erases the state of a small sized memory cell due to collisions with cosmic particles may take some time to cause a functional failure, periodic refreshing will prevent the functional failure. The configuration cells can be DRAM cells which occupy significantly less space than the SRAM cells. Refresh circuitry typically provided for DRAM cells is reduced by using the programming circuitry of the PLD. Data in the configuration cells of the PLD are reloaded from either external or internal soft-error immune non-volatile memory.

A video sub-system features reduced power consumption by integrating a video memory onto the same chip as the video memory controller. The video memory is preferably a small DRAM sufficiently large to store all pixel data for lower resolutions, but insufficient for higher resolutions. At higher resolutions, an external DRAM supplements the internal DRAM. The amount of external DRAM needed depends upon the resolution to be supported. The internal DRAM has a wide data bus and thus high bandwidth, since no external I/O pins are needed. The external DRAM is narrow to minimize pincount and power consumption. Since the external DRAM is slower and lower in bandwidth, pixel data from both internal and external DRAMs are interleaved together for each horizontal scan line. Thus the lower bandwidth of the external DRAM is masked by the high bandwidth of the wide internal DRAM. Either the internal or the external DRAM, or both, are automatically tested with a pseudo-random number generator that writes pseudo-random numbers to the DRAM while simultaneously supplying pixel data to the graphics data path for display. A checksum of the pixel data output from the graphics data path is generated for the first screen of pixels or frame, while on the second frame the pseudo-random number generator is disabled and the DRAM supplies the same pixel data that was written to it by the pseudo-random number generator during the first frame. The checksums for the first and second frames should match if the DRAM is free of faults.

A two-port dynamic random access memory (DRAM) cell consisting of two transistors and two trench capacitors (2T and 2C DRAM cell) connecting two one transistor and one capacitor DRAM cell (1T DRAM cell) is described. The mask data and cross-section of the 2T 2C DRAM and 1T DRAM cells are fully compatible to each other except for the diffusion connection that couples two storage nodes of the two 1T DRAM cells. This allows a one-port memory cell with 1T and 1C DRAM cell and a two-port memory cell with 2T and 2C DRAM cell to be fully integrated, forming a true system-on chip architecture. Alternatively, by halving the capacitor, the random access write cycle time is further reduced, while still maintaining the data retention time. The deep trench process time is also reduced by reducing by one-half the trench depth.

A ternary state content addressable memory (CAM) cell that includes two DRAM cells. In addition to a port for controlling and transmitting data to the CAM, another port is exclusively used for refreshing the DRAM cells. A refresh word line is coupled to the two DRAM cells for performing DRAW cell refresh. A refresh bit line is coupled to the first of the two DRAM cells for refreshing this first DRAM cell. A refresh bit line is coupled to the second of the two DRAM cells for refreshing this second DRAM cell. Problematic power consumption and voltage swing found in a conventional CAM are overcome in the CAM. A swing line (SL) is coupled to said first and second DRAM cells and a local match line (LML) of said CAM cell, said SL having an adjustable voltage level for changing voltage swing in said LML to regulate trade-off between power consumption and speed of said CAM cell.

A method for fabricating DRAM cells according to the present invention includes the steps of: forming a trench within a semiconductor substrate using a stacked layer as a mask, said stacked layer composed of a silicon oxide film and a silicon nitride film formed in an active region of said semiconductor substrate; forming a first insulation layer on a bottom and sides of said trench; depositing a first conductive layer on whole surface of said semiconductor substrate including said trench; etching back said conductive layer to be recessed from a top surface of said semiconductor substrate and forming bit lines of said first conductive layer on said bottom of said trench in a direction of column; filling a second insulation layer in said trench; removing said stacked layer and a part of said second insulation layer to expose said semiconductor substrate in said active region and planarizing said semiconductor substrate simultaneously; forming a gate insulation layer on said semiconductor substrate;forming a gate structure of a second conductive layer on said gate insulation layer; forming a spacer of an insulation layer on said sides of said gate structure of said second conductive layer; forming source and drain regions on both sides of said gate structure of said second conductive layer;forming a third insulation layer on said semiconductor substrate; connecting said bit lines to a first one of said source and drain regions with a plug of a third conductive layer filled in a contact hole inside said third insulation layer and said second insulation layer; forming a storage node electrode connected to a second one of said source and drain regions; andforming a plate electrode overlying a dielectric layer disposed said storage node electrode.Accordingly, the present invention has the buried bit lines in the trench, making it easy to secure a process margin in the subsequent process, maintaining a constant width of the bit lines to lower the resistance thereof. Furthermore, the bit lines disposed under the word lines has an advantage over patterning the node contact due to the low step height, with enhanced capacitance of the capacitor.