372 results about "Dram" patented technology

This invention pertains to a system optimized for reutilizing allocated underutilized or unused allocated DRAM, comprising a first host, a second host, and a resource composer, interconnected via CXL. Both hosts run packaged computing environments (PCEs), which may be containers or virtual machines, and are equipped to handle respective processes, P1 and P2. The resource composer is tasked with receiving data related to P1's memory usage from a kernel module on the first host, identifying underutilized DRAM mapped to P1, and subsequently remapping it to P2's address space on the second host. This process involves the use of CXL.mem commands, which are then translated into appropriate CXL.cache or CXL.io commands for DRAM access based on the mapping.

The invention provides a hierarchical memory and hierarchical storage method and system based on an NVM, and the method comprises the steps: S1, recognizing the access characteristics of memory pages, classifying the memory pages into persistent cold pages, memory access cold pages, persistent hot pages and memory access hot pages, and carrying out the initialization partitioning of the storage space of the NVM based on the classification; s2, dynamically adjusting the distribution of the memory pages between a dynamic random access memory (DRAM) and a non-volatile memory (NVM) by tracking the access heat and persistence heat of the memory pages; and S3, the persistent hot page is persisted to the NVM in the background. According to the method, a hierarchical memory system and a hierarchical storage system are combined, a new migration judgment standard is introduced, and the corresponding page is intelligently migrated to the NVM or the DRAM by predicting whether the page needs to be subjected to persistence operation frequently and predicting the access heat of the page, so that the overhead of the system in the persistence operation and access process is reduced.

The invention relates to the technical field of DRAM (Dynamic Random Access Memory) dynamic repair, in particular to a DRAM dynamic repair method based on unit damage trend identification. The method comprises the following steps: receiving a logic address request sent by a CPU (Central Processing Unit), sending a reading command to a DRAM (Dynamic Random Access Memory), and obtaining return data and ECC (Error Correction Code When a single-bit error is detected, the error is corrected according to ECC verification data, correct data is returned, meanwhile, the damage trend of a surrounding area is pre-judged based on physical correlation of DRAM unit damage, a DRAM address and the surrounding area are marked as isolation addresses, and the data are moved to an SRAM; establishing a repair mapping table in the SRAM, and writing the repair mapping table into the nonvolatile memory through the bus interface; reading the mapping table during cold start of the system, judging whether the address is an isolation address or not according to the mapping table in subsequent access, and if yes, accessing the SRAM to obtain data. According to the invention, a single-bit error is prevented from being evolved into a multi-bit error, and the system reliability is improved.

The invention discloses an IC (integrated circuit) chip packaging detection method for realizing system-in-package and 3D (three-dimensional) packaging, which relates to the technical field of chip packaging detection, and comprises the following steps: vertically stacking a plurality of DRAM (dynamic random access memory) core particles on a basic logic core particle with a micro-bump array on the surface through silicon through holes, and activating a self-detection circuit to obtain a suspicious area coordinate list; dividing regional risk levels through a targeted scanning scheduling algorithm, and generating a differentiated scanning parameter set; for each suspicious area, controlling an external X-ray source to collect multispectral projection data according to the differential scanning parameter set; performing three-dimensional reconstruction on the multiple groups of multispectral projection data by using an enhanced reconstruction model embedded with physical priori knowledge to obtain enhanced three-dimensional body data; and performing automatic defect identification on the enhanced three-dimensional body data, and outputting the identified defect as a detection result. The invention aims to solve the problems of difficulty in perspective imaging and insufficient resolution of internal defects of the high-density 3D stacked chip.

The invention relates to a three-dimensional stacking storage and calculation integrated artificial intelligence acceleration system and inference method, and the system comprises a three-dimensional stacking storage module which comprises a plurality of vertically stacked DRAM layers which carry out the communication through a high-density vertical interconnection structure; the calculation unit array is in direct communication coupling with at least one layer of the three-dimensional stacked storage module through a three-dimensional integration technology and is configured to execute at least partial reasoning calculation of a large language model or a multi-mode large language model; and the pre-stored key value cache management module is configured to pre-store key value caches generated by pre-filling and calculating predefined system cue words in one or more specified physical areas of the three-dimensional stack storage module, and the pre-stored key value caches are stored in one or more specified physical areas of the three-dimensional stack storage module. The computing unit array is further configured to access a pre-stored key value cache and combine it with data generated from dynamic user input when the inference computations are performed, thereby avoiding repeated pre-fill computations on system cues.

A memory system includes two or more memory controllers capable of accessing the same dynamic, random-access memory (DRAM), one controller having access to the DRAM or a subset of the DRAM at a time. Different subsets of the DRAM are supported with different refresh-control circuitry, including respective refresh-address counters. Whichever controller has access to a given subset of the DRAM issues refresh requests to the corresponding refresh-address counter. Counters are synchronized before control of a given subset of the DRAM is transferred between controllers to avoid a loss of stored data.

The invention belongs to the technical field of semiconductor testing, and particularly relates to an HBM-DRAM grouping testing system and method, and the system comprises a main testing controller and a plurality of testing execution units configured in the system. And the main test controller is in communication connection with the plurality of test execution units through a preset test coordination bus. By physically segmenting the test interface into a plurality of independent, low-needle-count probe card modules, challenges of designing and manufacturing a single, huge, ultra-high-needle-count probe card are fundamentally avoided. Therefore, the manufacturing cost, the calibration difficulty and the maintenance cost of each probe card module are greatly reduced, and the overall yield and the service life of the probe card are remarkably improved.

The invention relates to the technical field of DRAM (Dynamic Random Access Memory) repairing, in particular to a DRAM failure unit repairing method based on SOC (System On Chip) driving mapping adjustment. The method comprises the following steps: detecting a physical address of a failed CELL unit in a DRAM particle through test equipment, and generating repair mapping data; recording the repair mapping data on the surfaces of the DRAM particles in a two-dimensional code form and storing the repair mapping data in a nonvolatile memory; loading the repair mapping data to a driving program when the SOC is started; and synchronously modifying the address mapping relationship between the MMU and the IOMMU through a driving program, and redirecting the access to the invalid physical address to the standby physical address. By modifying MMU and IOMMU mapping on a driving layer at the same time, unified address remapping of access paths of CPU and DMA equipment is achieved, DRAM particles containing failure units can be used in a capacity reduction mode, PCBA cost is greatly reduced, hardware modification is not needed, and implementation is flexible.

The present disclosure provides a three-dimensional DRAM array structure including L layers, M rows, and N columns of DRAM cell structures, each DRAM cell structure including first and second gate transistors having a tubular channel, disposed in a vertical direction and electrically connected in parallel, and a storage capacitor of a tubular structure disposed between the first and second gate transistors in the vertical direction, an inner electrode of the second transistor is connected to the first source / drain of the first and second gate-all-around transistors, and an outer electrode is connected to a source line; the M * N bit lines respectively extend in a tubular structure jointly formed by the first and second gate-all-around transistors and the storage capacitor in the M-row and N-column DRAM unit structure along the vertical direction, and are respectively connected to second source / drain electrodes of the first and second gate-all-around transistors; the L * M first word lines and the L * M second word lines extend in the first horizontal direction and are connected to grid electrodes of the first fence transistors and the second fence transistors in the L layers of DRAM unit structures respectively, and the M rows of DRAM unit structures are divided into M / s row groups.

The invention discloses a data processing method and electronic equipment, relates to the technical field of computers, and aims to realize hot data preliminary screening through performance data, refine access features by compressing a heat map, dynamically update a heat score, and realize dynamic classification and hierarchical storage of data by comparing a target threshold with the heat score. According to the method and the device, the distribution of the data between the DRAM and the CXL memory is completed, and the technical effects of accurately identifying the hot data and optimizing the storage position are achieved on the premise of ensuring low overhead, so that the overall performance of the system is improved.

The present application relates to the field of accelerators, and discloses an accelerator architecture for near IO pipeline computing, and an AI acceleration system. A multi-channel direct access module comprises N DRAM controllers, and the N DRAM controllers are connected to DRAMs in a one-to-one correspondence; each DRAM controller is at least connected to k DMA controllers, and is connected to a corresponding core group cluster by means of the DMA controllers; a pipeline synchronization ring is connected to N core group clusters and comprises M cascaded forward transmission blocks and M cascaded backward transmission blocks, and the head-end forward transmission block and the tail-end forward transmission block are respectively connected to a data receiving module and a data transmitting module; the output of the tail-end forward transmission block is cascaded to the first backward transmission block; the ith forward transmission block and the (M-i)th backward transmission block correspond to each other in a front-rear direction, and are jointly connected to at least one computing core group. The accelerator of the architecture replaces a traditional multi-level cache structure, reduces the time delay caused multi-layer search, and accelerates the computing rate between the interior of the accelerator and the accelerator.

The invention belongs to the field of Transform model acceleration, and discloses a hybrid bonding 3D stacked accelerator and acceleration method oriented to Transform reasoning, the accelerator adopts a 3D stacked architecture, and comprises a DRAM storage bare chip and a logic bare chip, the DRAM storage bare chip comprises 16 DRAM storage blocks, the logic bare chip comprises 16 processing groups, each processing group corresponds to one DRAM storage block, and the processing groups correspond to the DRAM storage blocks. Each processing group is integrated with two attention processing units, and the DRAM storage blocks are connected with the processing groups through 32 copper-copper hybrid bonding vertical channels. According to the method, the problems of dense calculation and high memory bandwidth requirement in the reasoning process are solved, efficient model reasoning acceleration is realized, and the method is suitable for natural language processing, computer vision, video analysis and other application scenes depending on the Transform model.

A dynamic random access memory (DRAM) array has a first portion configured as a data array and a second portion configured as a reference array. The DRAM array includes read bit lines which include a first plurality of read bit lines in the data array and a second plurality of read bit lines in the reference array. Read circuitry includes a plurality of sensing circuits, each sensing circuit coupled to a corresponding read bit line of the first plurality of read bit lines and configured to receive a first reference voltage generated by a first read bit line of the second plurality of read bit lines and a second reference voltage generated by a second read bit line of the second plurality of bit lines. The plurality of sensing circuits is configured to provide a corresponding bit of an output read value.

An exemplary device and method for detecting and mitigating data-disturbance errors in a DRAM array, including Row-Press exploits or phenomenon as well as Rowhammer exploits or phenomenon. By mitigating both types of disturbance errors, the exemplary device and method can comprehensively protect DRAM from various vulnerabilities and enhancing its reliability, and doing so, with minimal hardware overhead addition. The exemplary device and method can be integrated with circuitries employed for Row-Press and Rowhammer detection and correction. The exemplary device and method can employ a counter as a proxy to detect when a Rowhammer threshold is met. In some embodiments, the Row-Press detection circuit can trigger an increment (whole or fractional) to the Rowhammer counter.

The invention relates to a storage processing method and device based on a capacitance-free DRAM (Dynamic Random Access Memory), and the method comprises the steps: preparing a corresponding writing transistor and a corresponding reading transistor through a preset oxide semiconductor and a silicon transistor; based on a preset heterogeneous integration strategy, vertically stacking the write transistor on the read transistor to establish a capacitance-free DRAM memory unit; the method comprises the following steps: establishing a heterogeneous integrated capacitance-free DRAM memory macro based on a pre-established storage unit peripheral circuit and a capacitance-free DRAM memory unit, and establishing a corresponding in-memory processing architecture according to the heterogeneous integrated capacitance-free DRAM memory macro and a pre-established convolution kernel logic circuit, so as to execute corresponding storage operation through the in-memory processing architecture. Therefore, the technical problems that in the prior art, a DRAM memory processing framework is high in process cost, incompatible in preparation process, high in circuit complexity, poor in memory processing speed and the like are solved.

The invention discloses a DRAM (dynamic random access memory) repairing method, an upper computer, a storage medium and a computer program product, and relates to the technical field of DRAM repairing, the DRAM repairing method comprises the following steps: inputting a test program to a main control chip to enable the main control chip to test DRAM particles based on the test program, and determining fault information of the DRAM particles according to a test result; wherein the test program runs in an SRAM (Static Random Access Memory) in the main control chip; generating a corresponding repair program according to the fault information, and verifying the validity of the repair program; and under the condition that the repair program is verified to be valid, repairing the DRAM particles according to the repair program. According to the method and the device, the DRAM can be repaired on the premise of not depending on normal work of the DRAM.

The invention discloses a flash memory and near memory acceleration system of an end-side large language model, and belongs to the technical field of calculation, reckoning or counting. According to the system, a 3D NAND flash memory chip with near memory computing capability is adopted, and model weights and key value caches are uniformly stored in the flash memory. Storage-intensive operations involved in the big language model inference decoding stage are all completed in a logic layer of a flash memory, and an NPU only executes non-linear operations such as normalization and activation and residual connection; in the pre-filling stage, the NPU obtains weight and key value cache data from the flash memory and is used for completing all calculations. Redundant read-write is reduced through a flash memory page-level key value cache mapping mechanism; and meanwhile, attention head group parallel data stream optimization is provided, so that the parallelism of a decoding stage is improved. A discrete framework and a compact framework are further provided, and optimal configuration is automatically selected in combination with a design space exploration strategy. According to the method, the requirement of edge end large language model reasoning on the DRAM can be omitted, delay is reduced, throughput is improved, and system cost and power consumption are remarkably reduced.

A method includes storing, by a microcontroller, cache data of the microcontroller into a dynamic random-access memory (DRAM) in response to the microcontroller receiving a power-off command. The method includes operating, by a DRAM controller, the DRAM in a standby state in response to the microcontroller storing the cache data into the DRAM. The method includes determining, by the DRAM controller and when the DRAM is operating in the standby state, a time characteristic associated with the DRAM, a charge characteristic associated with the DRAM, or a combination thereof. The method includes determining, by the DRAM controller, whether a suspend to storage condition is satisfied based on the time characteristic, the charge characteristic, or the combination thereof. The method includes storing, by the DRAM controller, the cache data of the DRAM into a read-only memory (ROM) in response to the suspend to storage condition being satisfied.

Overhang architectures for high bandwidth memory (HBM) multi-die assemblies and methods for making same. The overhang architecture places the DRAM (HBM) underneath the top IC die. The signal interconnects between the top IC die and the DRAM die are direct signal interconnects without lateral routing on a package substrate or on a motherboard.

A storage device provides thin provisioning by presenting more logical capacity than available physical capacity. The storage device uses a dynamic random-access memory (DRAM) having a size that is proportional to the available physical capacity of the storage device. The storage device includes a memory device with a physical capacity and the DRAM. A controller on the storage device creates segments including logical block address (LBA) sets in an LBA space. The LBA sets include an LBA from each segment that are linked to enable the LBAs in a LBA set to share a mapping space in the DRAM. The controller also creates an L2P table including a LBA set entry per LBA set, with each LBA set entry including sub-entries to store physical locations on the memory device that are associated with the LBAs in the LBA set. The controller also stores the L2P table in the DRAM.

A three-dimensional (3D) stacked memory package is described. The 3D stacked memory package includes a first plurality of stacked memory dies. The 3D stacked memory package also includes a first base die stacked on the first plurality of stacked memory dies. The 3D stacked memory package further includes a package substrate supporting the first plurality of stacked memory dies. The 3D stacked memory package also includes a first plurality of through silicon vias (TSVs) extending between the first plurality of stacked memory dies and a first compute block on the first base die. The 3D stacked memory package further includes a first set of wire-bonds coupled between the package substrate and a first physical IO interface (PHY) on the first base die.

The invention discloses an R-tree spatial index design method oriented to a DRAM-NVM hybrid storage architecture, relates to the technical field of computer data storage, and provides a write optimization spatial index HR-Tree under the DRAM-NVM hybrid architecture. The core design thought is that internal nodes are deployed on a DRAM, leaf nodes are placed on an NVM, and a targeted data read-write operation process is designed; in the aspect of an index structure and an operation mechanism, a minimum expansion strategy is adopted around a scene of less reading and more writing, a leaf node data structure and an in-situ updating algorithm on the NVM are designed in a targeted manner, and the write request processing efficiency can be improved on the premise of ensuring data consistency. And the multi-character data expansion and efficient fault recovery are provided, so that the actual requirements of the user are better met by allowing more flexible personalized configuration and shortening the service pause time. The method is suitable for the application fields of computer technology, database technology, data storage and the like.

A stacked system-on-chip (SoC) is described. The stacked SoC includes a first memory die comprising a dynamic random-access memory (DRAM). The stacked SoC also includes a compute logic die. The compute logic die comprises a static random-access memory (SRAM) having a first SRAM partition and a second SRAM partition. The first memory die is stacked on the compute logic die. The compute logic die includes a memory controller. The memory controller is coupled between the first SRAM partition and the second SRAM partition. Additionally, the memory controller is coupled to a DRAM bus of the first memory die.

The invention discloses a DRAM (Dynamic Random Access Memory) scheduling method and device and electronic equipment, and belongs to the technical field of terminals. The method comprises the steps that the CPU utilization rate of the electronic equipment and the frame rate redundancy of an application program in the electronic equipment are obtained, and the frame rate redundancy is determined based on the first actual rendering frame rate and the target rendering frame rate of the application program; and adjusting the running state of the DRAM in the electronic equipment according to the frame rate redundancy and the CPU utilization rate.

The present invention discloses a dynamic random access memory (DRAM) and a method for forming the same, wherein the DRAM comprises a substrate, a plurality of word line groups, a plurality of bit line structures, a plurality of capacitors, a plurality of capacitor contact windows, and a plurality of air gaps. The substrate has a plurality of active regions. The word line groups extend along the Y direction and are disposed in the substrate. The bit line structures extend along the X direction and are disposed on the substrate, crossing the plurality of word line groups. The capacitors are disposed at the two end points of the plurality of active regions, respectively. The capacitor contact windows are disposed between the capacitors and the active regions, respectively. The air gaps are disposed in a plurality of spaces enclosed by the bit line structures and the capacitor contact windows, respectively. A method for forming the DRAM is also provided.

The invention provides a DRAM (Dynamic Random Access Memory) data reading time sequence calibration method and device, and the method comprises the steps that in a DRAM initialization stage, a DRAM controller writes specific data into a fixed address, sends a reading instruction, and receives a fed-back data gating signal and a data signal; carrying out delay processing on the data strobe signal, delaying the data strobe signal into a plurality of data strobe signals with different delay values, and selectively outputting the data strobe signals by using a multiplexer; the asynchronous FIFO module is used for receiving a data signal, and the multiplexer selects an output data strobe signal as a write clock signal of the asynchronous FIFO module; after the asynchronous FIFO module receives the data signal, a DARM system clock signal is used as a read clock signal of the FIFO module, and FIFO read data is output; and comparing the FIFO read data with target data, and when the comparison result is inconsistent, adjusting a control signal of the multiplexer until the comparison result of the FIFO read data and specific data is consistent.

A three-dimensional (3D) stacked memory package is described. The 3D stacked memory package includes a first plurality of stacked memory dies. The 3D stacked memory package also includes a first base die stacked on the first plurality of stacked memory dies. The 3D stacked memory package further includes a package substrate supporting the first plurality of stacked memory dies. The 3D stacked memory package also includes a first plurality of through silicon vias (TSVs) extending between the first plurality of stacked memory dies and a first compute block on the first base die. The 3D stacked memory package further includes a first set of wire-bonds coupled between the package substrate and a first physical IO interface (PHY) on the first base die.

The invention discloses an automatic wiring method for a gold-plated lead of a DRAM (Dynamic Random Access Memory) packaging substrate, and relates to the technical field of DRAM packaging substrate design. The method comprises the steps of structured data input, VBA intelligent coordinate calculation, network screening and duplicate removal, wiring instruction set generation, script automatic generation, automatic execution and graph generation. Basic data are input through a standardized Excel template, a VBA program automatically completes calculation of bonding wire angles and lead coordinates and duplicate network de-duplication, then the bonding wire angles and the lead coordinates are converted into Allegro scripts, and gold-plated leads are drawn in batches in Allegro software. According to the method, a traditional manual design mode is replaced, the wiring efficiency is greatly improved, the problem of lead omission or redundancy caused by human negligence is avoided, the design flexibility and the change response capability are enhanced, and the accuracy and reliability of gold-plated lead design are guaranteed.

The DRAM temperature monitoring self-refresh circuit and the DRAM provided by the embodiments of the present disclosure comprise: a self-refresh enabling module, which outputs a clock signal to a reference voltage generating module and a logic module upon receiving a self-refresh enabling signal; the reference voltage generating module determines a first clock sampling signal according to the received clock signal, and generates a reference voltage to a comparison module according to the first clock sampling signal; the comparison module outputs a comparison signal to the logic module according to the reference voltage and a diode voltage; the logic module generates a sampling signal to collect the first clock sampling signal of the reference voltage generating module at a first time according to the clock signal and the comparison signal when the comparison signal is at a high level, so as to generate a temperature identification signal according to the first clock sampling signal, and determine a chip refresh clock according to the temperature identification signal and the clock signal, and generates a reset signal to the reference voltage generating module at a second time, so as to reset the first clock sampling signal of the reference voltage generating module.

Disclosed herein are approaches for forming a dynamic random-access memory device (DRAM). One DRAM device may include plurality of pillars extending from a base layer, and a spacer layer formed along just a lower portion of each of the plurality of pillars. The DRAM further includes a body contact and a cap between the plurality of pillars, wherein the body contact is formed over the spacer layer, and a gate formed around the plurality of pillars. The DRAM further includes a bottom source / drain formed in the base layer and a top source / drain formed in each pillar of the plurality of pillars, wherein the top source / drain extends above the gate.