514 results about "Dram" patented technology

This invention pertains to a system optimized for reutilizing allocated underutilized or unused allocated DRAM, comprising a first host, a second host, and a resource composer, interconnected via CXL. Both hosts run packaged computing environments (PCEs), which may be containers or virtual machines, and are equipped to handle respective processes, P1 and P2. The resource composer is tasked with receiving data related to P1's memory usage from a kernel module on the first host, identifying underutilized DRAM mapped to P1, and subsequently remapping it to P2's address space on the second host. This process involves the use of CXL.mem commands, which are then translated into appropriate CXL.cache or CXL.io commands for DRAM access based on the mapping.

The invention relates to an AI computing subsystem, end-side equipment and a control method of the end-side equipment, and the AI computing subsystem comprises at least one FLASH storage chip which is used for pre-storing weight parameters of at least one AI network model; the at least one DRAM storage chip is used for storing weight parameters and activation functions of the AI model; and the logic chip is connected with the FLASH storage chip and the DRAM storage chip, responds to an external instruction, reads data of the FLASH storage chip so as to write the data into the DRAM storage chip, and / or reads weight parameters and activation functions stored in the DRAM storage chip and executes a calculation task. The SoC system only needs to send parameters or start commands of the AI network, and the whole network runs in the AI computing subsystem; and the most complex part of the AI network part can be deployed in the AI computing subsystem, and the SoC system only needs to compute the simple operator of the part, so that the SoC system has larger space to complete other responsible tasks.

The invention relates to a ZNS SSD-based B + tree index construction method for dynamic placement of cold and hot data. A persistent memory PM, a dynamic random access memory DRAM and a ZNS SSD hard disk are included. The persistent memory PM and the dynamic random access memory DRAM are directly connected with a CPU memory bus and have the capability of being accessed by the CPU according to bytes; internal nodes of the B + tree are stored in a dynamic random access memory (DRAM), and the internal nodes only store index information used for positioning leaf nodes; the pseudo leaf nodes of the B + tree are stored in a persistent memory PM, and only the key index information of the leaf nodes is stored in the pseudo leaf nodes; leaf nodes really storing the key value pairs in the B + tree are divided into hot leaf nodes and cold leaf nodes according to the data access frequency, the hot leaf nodes are stored in a persistent memory PM, and the cold leaf nodes are stored in a ZNS SSD. According to the method, the leaf nodes are quickly positioned by using the DRAM, so that the query time is shortened; hot leaf nodes are stored in the PM, and the real-time service read-write requirement is met; and hot data is stored in a high-speed DRAM and PM, so that the random read-write delay is reduced, and the performance is excellent in scenes such as big data analysis and the like.

Disclosed are various approaches for bit-serial computing embedded in the DRAM subarray, leveraging the massive parallelism of DRAM row operations. The present disclosure discloses digital techniques that can outperform analog charge-sharing techniques. Digital techniques can use more area but support a wider range of computing primitives, and allow a sequence of logic operations to be performed at higher clock speeds, be-tween slower subarray row reads / writes. The present disclosure describes a range of bit-serial architectures, and evaluate raw performance as well as area and energy efficiency. Results show that the digital architecture demonstrates 20× speedup over CPU, 5× over GPU, and 1.7× over SIMDRAM, an analog architecture.

This specification describes memory controllers with adaptive precharge scheduling. In one aspect, a memory controller includes a refresh scheduler configured to send refresh commands to dynamic random-access memory (DRAM) banks of a DRAM memory system that includes DRAM banks arranged in a set of DRAM bank groups each comprising one or more DRAM banks. The memory controller includes an adaptive precharge scheduler configured to determine a priority score for each DRAM bank group based on a set of parameters, select, based on the priority score for each DRAM bank group, a particular DRAM bank group to close so that each DRAM bank in the DRAM bank group can be refreshed by the refresh scheduler, and send the precharge command to at least one DRAM bank of the particular DRAM group.

A DRAM memory controller is provided that identifies a marker command directed to a given row in a DRAM. If a threshold probability is satisfied in response to an identification of the marker command, the DRAM memory controller commands the DRAM to refresh a neighboring row in the DRAM. The neighboring row may be a neighboring of the given row or of a recently-closed row.

A DRAM packages comprises stacked array dies including at least a first array die and a stacked over at least the first array die, data terminals, via which the DRAM package receives or outputs data signals, first data interconnects between respective ones of the data terminals and the first array die, and second data interconnects distinct from the first data interconnects and between respective ones of the data terminals and the second array die. The DRAM package further comprises drivers configured to drive first data signals to the first array die via the first data interconnects and second data signals to the second array die via the second data interconnects. A first data signal is driven by one or more drivers having a first driver size, and a second data signal is driven by one or more drivers having a second driver size different from the first driver size.

The invention provides a hierarchical memory and hierarchical storage method and system based on an NVM, and the method comprises the steps: S1, recognizing the access characteristics of memory pages, classifying the memory pages into persistent cold pages, memory access cold pages, persistent hot pages and memory access hot pages, and carrying out the initialization partitioning of the storage space of the NVM based on the classification; s2, dynamically adjusting the distribution of the memory pages between a dynamic random access memory (DRAM) and a non-volatile memory (NVM) by tracking the access heat and persistence heat of the memory pages; and S3, the persistent hot page is persisted to the NVM in the background. According to the method, a hierarchical memory system and a hierarchical storage system are combined, a new migration judgment standard is introduced, and the corresponding page is intelligently migrated to the NVM or the DRAM by predicting whether the page needs to be subjected to persistence operation frequently and predicting the access heat of the page, so that the overhead of the system in the persistence operation and access process is reduced.

Splitting an address translation cache (ATC) into two portions can reduce costs and maintain efficient retrieval of data. One portion can be disposed in a first location while a second portion can be disposed in a second location distinct from the first location. The first location can be in the controller. The second location can be in a host memory buffer (HMB) or in a memory device separate from the controller. To obtain translated addresses, untranslated addresses can be searched in the first portion and the corresponding translated addresses can be retrieved from the second portion. When invalidating untranslated addresses, the untranslated addresses of the first portion can be deleted without a need to delete corresponding translated addresses in the second portion. To improve ATC storage capacity, grouping of untranslated addresses is possible using most significant bytes (MSBs).

The invention relates to the technical field of DRAM (Dynamic Random Access Memory) dynamic repair, in particular to a DRAM dynamic repair method based on unit damage trend identification. The method comprises the following steps: receiving a logic address request sent by a CPU (Central Processing Unit), sending a reading command to a DRAM (Dynamic Random Access Memory), and obtaining return data and ECC (Error Correction Code When a single-bit error is detected, the error is corrected according to ECC verification data, correct data is returned, meanwhile, the damage trend of a surrounding area is pre-judged based on physical correlation of DRAM unit damage, a DRAM address and the surrounding area are marked as isolation addresses, and the data are moved to an SRAM; establishing a repair mapping table in the SRAM, and writing the repair mapping table into the nonvolatile memory through the bus interface; reading the mapping table during cold start of the system, judging whether the address is an isolation address or not according to the mapping table in subsequent access, and if yes, accessing the SRAM to obtain data. According to the invention, a single-bit error is prevented from being evolved into a multi-bit error, and the system reliability is improved.

The invention discloses an IC (integrated circuit) chip packaging detection method for realizing system-in-package and 3D (three-dimensional) packaging, which relates to the technical field of chip packaging detection, and comprises the following steps: vertically stacking a plurality of DRAM (dynamic random access memory) core particles on a basic logic core particle with a micro-bump array on the surface through silicon through holes, and activating a self-detection circuit to obtain a suspicious area coordinate list; dividing regional risk levels through a targeted scanning scheduling algorithm, and generating a differentiated scanning parameter set; for each suspicious area, controlling an external X-ray source to collect multispectral projection data according to the differential scanning parameter set; performing three-dimensional reconstruction on the multiple groups of multispectral projection data by using an enhanced reconstruction model embedded with physical priori knowledge to obtain enhanced three-dimensional body data; and performing automatic defect identification on the enhanced three-dimensional body data, and outputting the identified defect as a detection result. The invention aims to solve the problems of difficulty in perspective imaging and insufficient resolution of internal defects of the high-density 3D stacked chip.

The invention relates to a three-dimensional stacking storage and calculation integrated artificial intelligence acceleration system and inference method, and the system comprises a three-dimensional stacking storage module which comprises a plurality of vertically stacked DRAM layers which carry out the communication through a high-density vertical interconnection structure; the calculation unit array is in direct communication coupling with at least one layer of the three-dimensional stacked storage module through a three-dimensional integration technology and is configured to execute at least partial reasoning calculation of a large language model or a multi-mode large language model; and the pre-stored key value cache management module is configured to pre-store key value caches generated by pre-filling and calculating predefined system cue words in one or more specified physical areas of the three-dimensional stack storage module, and the pre-stored key value caches are stored in one or more specified physical areas of the three-dimensional stack storage module. The computing unit array is further configured to access a pre-stored key value cache and combine it with data generated from dynamic user input when the inference computations are performed, thereby avoiding repeated pre-fill computations on system cues.

A memory system includes two or more memory controllers capable of accessing the same dynamic, random-access memory (DRAM), one controller having access to the DRAM or a subset of the DRAM at a time. Different subsets of the DRAM are supported with different refresh-control circuitry, including respective refresh-address counters. Whichever controller has access to a given subset of the DRAM issues refresh requests to the corresponding refresh-address counter. Counters are synchronized before control of a given subset of the DRAM is transferred between controllers to avoid a loss of stored data.

Described is a device having three-dimensional (3D) integration of a DRAM die and processor ASIC. Such an integrated device achieves much higher memory bandwidth and low memory access power consumption than prior art devices while still retaining the high capacity and low cost of DRAMs. The devices and techniques described herein can result in much higher computational throughput, higher power efficiency, and lower cost per throughput than conventional processors while still providing the high memory capacity necessary to be able to work on large problems.

A DRAM is provided including a block with a 3D array of memory cells. The block includes a set of planes stacked along a first axis, including a subset of stacked planes. Each plane of the subset includes a 2D array of memory cells organized in rows and columns. The block has multiple sub-blocks arranged along the second axis with each sub-block containing one column of memory cells of each plane. The DRAM has a plurality of bit lines extending along the first axis in one of the sub-blocks and connected to one memory cell in each plane and includes a plurality of global bit lines connected to the bit lines in each sub-block. Bit line selector transistors of the DRAM connect bit lines to global bit lines and bit line pre-charge transistors of the DRAM connect bit lines to charging lines to charge the bit line.

The invention belongs to the technical field of semiconductor testing, and particularly relates to an HBM-DRAM grouping testing system and method, and the system comprises a main testing controller and a plurality of testing execution units configured in the system. And the main test controller is in communication connection with the plurality of test execution units through a preset test coordination bus. By physically segmenting the test interface into a plurality of independent, low-needle-count probe card modules, challenges of designing and manufacturing a single, huge, ultra-high-needle-count probe card are fundamentally avoided. Therefore, the manufacturing cost, the calibration difficulty and the maintenance cost of each probe card module are greatly reduced, and the overall yield and the service life of the probe card are remarkably improved.

The invention relates to the technical field of DRAM (Dynamic Random Access Memory) repairing, in particular to a DRAM failure unit repairing method based on SOC (System On Chip) driving mapping adjustment. The method comprises the following steps: detecting a physical address of a failed CELL unit in a DRAM particle through test equipment, and generating repair mapping data; recording the repair mapping data on the surfaces of the DRAM particles in a two-dimensional code form and storing the repair mapping data in a nonvolatile memory; loading the repair mapping data to a driving program when the SOC is started; and synchronously modifying the address mapping relationship between the MMU and the IOMMU through a driving program, and redirecting the access to the invalid physical address to the standby physical address. By modifying MMU and IOMMU mapping on a driving layer at the same time, unified address remapping of access paths of CPU and DMA equipment is achieved, DRAM particles containing failure units can be used in a capacity reduction mode, PCBA cost is greatly reduced, hardware modification is not needed, and implementation is flexible.

A data processing system includes a dynamic random access memory (DRAM), a prefetcher, and a refresh controller. The DRAM includes a plurality of DRAM cells, each with a capacitive storage element. The prefetcher is configured to prefetch information from the DRAM into a prefetch buffer in accordance with a prefetch pattern of addresses in the DRAM. The refresh controller includes a dynamic refresh control circuit configured to detect prefetch patterns of the prefetcher, and, in response to a detected prefetch pattern, refresh locations of the DRAM in accordance with a refresh pattern of addresses which is based on the prefetch pattern of addresses.

The present disclosure provides a three-dimensional DRAM array structure including L layers, M rows, and N columns of DRAM cell structures, each DRAM cell structure including first and second gate transistors having a tubular channel, disposed in a vertical direction and electrically connected in parallel, and a storage capacitor of a tubular structure disposed between the first and second gate transistors in the vertical direction, an inner electrode of the second transistor is connected to the first source / drain of the first and second gate-all-around transistors, and an outer electrode is connected to a source line; the M * N bit lines respectively extend in a tubular structure jointly formed by the first and second gate-all-around transistors and the storage capacitor in the M-row and N-column DRAM unit structure along the vertical direction, and are respectively connected to second source / drain electrodes of the first and second gate-all-around transistors; the L * M first word lines and the L * M second word lines extend in the first horizontal direction and are connected to grid electrodes of the first fence transistors and the second fence transistors in the L layers of DRAM unit structures respectively, and the M rows of DRAM unit structures are divided into M / s row groups.

The invention discloses a data processing method and electronic equipment, relates to the technical field of computers, and aims to realize hot data preliminary screening through performance data, refine access features by compressing a heat map, dynamically update a heat score, and realize dynamic classification and hierarchical storage of data by comparing a target threshold with the heat score. According to the method and the device, the distribution of the data between the DRAM and the CXL memory is completed, and the technical effects of accurately identifying the hot data and optimizing the storage position are achieved on the premise of ensuring low overhead, so that the overall performance of the system is improved.

The present application relates to the field of accelerators, and discloses an accelerator architecture for near IO pipeline computing, and an AI acceleration system. A multi-channel direct access module comprises N DRAM controllers, and the N DRAM controllers are connected to DRAMs in a one-to-one correspondence; each DRAM controller is at least connected to k DMA controllers, and is connected to a corresponding core group cluster by means of the DMA controllers; a pipeline synchronization ring is connected to N core group clusters and comprises M cascaded forward transmission blocks and M cascaded backward transmission blocks, and the head-end forward transmission block and the tail-end forward transmission block are respectively connected to a data receiving module and a data transmitting module; the output of the tail-end forward transmission block is cascaded to the first backward transmission block; the ith forward transmission block and the (M-i)th backward transmission block correspond to each other in a front-rear direction, and are jointly connected to at least one computing core group. The accelerator of the architecture replaces a traditional multi-level cache structure, reduces the time delay caused multi-layer search, and accelerates the computing rate between the interior of the accelerator and the accelerator.

The invention discloses a vertically-stacked 2T0C DRAM (Dynamic Random Access Memory) unit based on an oxide semiconductor ring gate transistor and a preparation method of the vertically-stacked 2T0C DRAM unit. According to the 2T0C DRAM unit, a first metal interconnection layer, a read transistor layer, a second metal interconnection layer, an isolation layer, a write transistor layer and a third metal interconnection layer are sequentially stacked on a substrate from bottom to top, a read transistor and a write transistor are oxide semiconductor transistors of a vertical ring gate structure, and the two transistors are vertically stacked. Compared with a planar transistor, the DRAM unit has more excellent electrical performance, the working voltage and the characteristic size of the DRAM unit are effectively reduced, and the integration density is improved. By adopting the ring gate structure, the gate control capability can be effectively improved, the same charging current as that of a planar transistor can be realized under a relatively low power supply voltage, and the charge leakage in a holding state is reduced, so that the DRAM gives consideration to both ultra-fast writing and ultra-long data holding time. And meanwhile, the vertically stacked structure reduces the area overhead of the DRAM unit and reduces the wiring difficulty.

The invention belongs to the field of Transform model acceleration, and discloses a hybrid bonding 3D stacked accelerator and acceleration method oriented to Transform reasoning, the accelerator adopts a 3D stacked architecture, and comprises a DRAM storage bare chip and a logic bare chip, the DRAM storage bare chip comprises 16 DRAM storage blocks, the logic bare chip comprises 16 processing groups, each processing group corresponds to one DRAM storage block, and the processing groups correspond to the DRAM storage blocks. Each processing group is integrated with two attention processing units, and the DRAM storage blocks are connected with the processing groups through 32 copper-copper hybrid bonding vertical channels. According to the method, the problems of dense calculation and high memory bandwidth requirement in the reasoning process are solved, efficient model reasoning acceleration is realized, and the method is suitable for natural language processing, computer vision, video analysis and other application scenes depending on the Transform model.

A memory device has a relatively wide, multi-pad data port for sending and receiving bursts of read and write data, respectively, to and from a requesting host. The host can fractionalize the multi-pad data port into narrower bidirectional ports to simultaneously communicate read and write data. The memory device increases burst lengths in proportion to reductions in port width to maintain access granularity. The width fractions of the narrower data ports can be controlled by the host responsive to e.g. a ratio of read to write transactions.

According to one embodiment, a memory module includes: a memory die including a dynamic random access memory (DRAM) banks, each including: an array of DRAM cells arranged in pages; a row buffer to store values of one of the pages; an input / output (IO) module; and an in-memory compute (IMC) module including: an arithmetic logic unit (ALU) to receive operands from the row buffer or the IO module and to compute an output based on the operands and one of a plurality of ALU operations; and a result register to store the output of the ALU; and a controller to: receive, from a host processor, operands and an instruction; determine, based on the instruction, a data layout; supply the operands to the DRAM banks in accordance with the data layout; and control an IMC module to perform one of the ALU operations on the operands in accordance with the instruction.SPL

In an embodiment, a memory system may include at least two types of DRAM, which differ in at least one characteristic. For example, one DRAM type may be a high density DRAM, while another DRAM type may have lower density but may also have lower latency and higher bandwidth than the first DRAM type. DRAM of the first type may be on one or more first integrated circuits and DRAM of the second type may be on one or more second integrated circuits. In an embodiment, the first and second integrated circuits may be coupled together in a stack. The second integrated circuit may include a physical layer circuit to couple to other circuitry (e.g., an integrated circuit having a memory controller, such as a system on a chip (SOC)), and the physical layer circuit may be shared by the DRAM in the first integrated circuits.

A dynamic random access memory (DRAM) array has a first portion configured as a data array and a second portion configured as a reference array. The DRAM array includes read bit lines which include a first plurality of read bit lines in the data array and a second plurality of read bit lines in the reference array. Read circuitry includes a plurality of sensing circuits, each sensing circuit coupled to a corresponding read bit line of the first plurality of read bit lines and configured to receive a first reference voltage generated by a first read bit line of the second plurality of read bit lines and a second reference voltage generated by a second read bit line of the second plurality of bit lines. The plurality of sensing circuits is configured to provide a corresponding bit of an output read value.

An exemplary device and method for detecting and mitigating data-disturbance errors in a DRAM array, including Row-Press exploits or phenomenon as well as Rowhammer exploits or phenomenon. By mitigating both types of disturbance errors, the exemplary device and method can comprehensively protect DRAM from various vulnerabilities and enhancing its reliability, and doing so, with minimal hardware overhead addition. The exemplary device and method can be integrated with circuitries employed for Row-Press and Rowhammer detection and correction. The exemplary device and method can employ a counter as a proxy to detect when a Rowhammer threshold is met. In some embodiments, the Row-Press detection circuit can trigger an increment (whole or fractional) to the Rowhammer counter.

In a compute express link (CXL) memory controller system, a system and method to identify memory errors which may require soft package repair or hard package repair to rows of DRAM memory. When data is written to a row of DRAM, the data is immediately and automatically read back and scanned for bit errors. If bit errors are identified, steps are taken to determine if the memory location requires no repair, soft repair, or hard repair. The data is corrected and written back to a new memory location which is memory-mapped to the original location, thus effecting the soft- or hard-repair. The present system and method does not repair the entire row of memory, but only repairs the specific die(s) that exhibit memory error in the row.

The invention relates to a storage processing method and device based on a capacitance-free DRAM (Dynamic Random Access Memory), and the method comprises the steps: preparing a corresponding writing transistor and a corresponding reading transistor through a preset oxide semiconductor and a silicon transistor; based on a preset heterogeneous integration strategy, vertically stacking the write transistor on the read transistor to establish a capacitance-free DRAM memory unit; the method comprises the following steps: establishing a heterogeneous integrated capacitance-free DRAM memory macro based on a pre-established storage unit peripheral circuit and a capacitance-free DRAM memory unit, and establishing a corresponding in-memory processing architecture according to the heterogeneous integrated capacitance-free DRAM memory macro and a pre-established convolution kernel logic circuit, so as to execute corresponding storage operation through the in-memory processing architecture. Therefore, the technical problems that in the prior art, a DRAM memory processing framework is high in process cost, incompatible in preparation process, high in circuit complexity, poor in memory processing speed and the like are solved.