54 results about "Planar capacitor" patented technology

A method of fabricating a system includes fabricating a plurality of transistors and coupling a forming a bridge structure connected between a gate contact of a first transistor with a drain contact of a second transistor. The method further includes fabricating a multi-level memory structure including capacitors that comprise a ferroelectric material or a paraelectric material. The capacitors within a given level are coupled together by a plate electrode. The method further includes forming a signal electrode coupled with the plate electrode.

The invention relates to the field of intelligent sensing, and particularly provides a clothes humidity detection device and method. The device comprises a PCB, a first electrode plate, a second electrode plate and a third electrode plate are arranged on the PCB, and planar capacitors are formed between the first electrode plate and the second electrode plate and between the first electrode plate and the third electrode plate. The method comprises the following steps: S1, signal excitation; s2, receiving a signal; s3, amplifying the signal; s4, carrying out signal differential processing; s5, humidity information is output; the method is realized by using the device. The three electrode plates are arranged on the PCB to form two planar capacitors, the electric field distribution is wide, the surface and internal humidity change can be sensed, and the clothes drying degree can be accurately reflected. By means of differential amplification processing of detection signals of the second electrode plate and the third electrode plate, initial capacitance and noise interference are eliminated, and high-accuracy humidity detection is achieved under the complex humidity distribution condition.

A Floquet mode traveling wave parametric amplifier (TWPA) is disclosed. The Floquet mode TWPA comprises a plurality of stages, where each stage is made up of a nonlinear element and a shunt capacitor. The nonlinear elements may be Josephson junctions, or a combination of series and / or parallel Josephson junctions. The Floquet mode TWPA is designed such that the critical current of the nonlinear elements in each stage is not constant. In some embodiments, the ratio of the largest critical current to the smallest critical current in the Floquet mode TWPA is at least 2:1. In some embodiments, the nonlinear elements with the largest critical current are disposed at or near the input or output of the amplifier. In this way, reflections and backward amplification may be minimized. Further, the TWPA is formed using planar capacitors on a high resistivity substrate, or using low loss parallel plate capacitors.

A method of fabricating a system includes fabricating a plurality of transistors and coupling a forming a bridge structure connected between a gate contact of a first transistor with a drain contact of a second transistor. The method further includes fabricating a multi-level memory structure including capacitors that comprise a ferroelectric material or a paraelectric material. The capacitors within a given level are coupled together by a plate electrode. The method further includes forming a signal electrode coupled with the plate electrode.

The invention provides a semiconductor device, a forming method and a storage system, and relates to the technical field of semiconductors. The semiconductor device comprises a first semiconductor structure and a second semiconductor structure, the first semiconductor structure comprises a stacked structure and a transistor, the stacked structure comprises first conductive layers and second conductive layers which are alternately stacked in the first direction, the transistor is arranged on one side of the stacked structure, and the transistor is connected with one first conductive layer; and the first connecting structure penetrates through the stacking structure along the first direction and is connected with the second conductive layer. According to the technical scheme, the manufacturing process of the planar capacitor formed by alternately stacking the two conductive layers is simple and easy to implement, the common electrode led out through the first connecting structure does not occupy the effective area of the first conductive layer and the effective area of the second conductive layer, and the obtained planar capacitor has large capacitance capacity.

A flexible variable capacitor and its fabrication method are disclosed. The flexible variable capacitor comprises two highly conductive flexible electrode layers and an elastomeric dielectric insulating layer located between the two highly conductive flexible electrode layers. The highly conductive flexible electrode layers contain a first polymer elastomer and carbon nanomaterials, and the elastomeric dielectric insulating layer contains a second polymer elastomer and functional ceramic nanoparticles. The fabrication method of the flexible variable capacitor is as follows: first, an elastomeric composite film with different functions is prepared; then, the upper and lower electrode layers are pressed together with the intermediate elastomeric insulating layer to obtain a stretchable strip-shaped planar capacitor. Unlike existing technologies, this application uses independently developed highly conductive flexible electrodes to replace traditional silver-oil electrodes, significantly reducing the cost of the variable capacitor device and improving its integration and operability. The fabricated flexible variable capacitor features high dielectric constant, low dielectric loss, simple fabrication process, and sensitivity to deformation.

A device structure comprises a first conductive interconnect, an electrode structure on the first conductive interconnect, an etch stop layer laterally surrounding the electrode structure; a plurality of memory devices above the electrode structure, where individual ones of the plurality of memory devices comprise a dielectric layer comprising a perovskite material. The device structure further comprises a plate electrode coupled between the plurality of memory devices and the electrode structure, where the plate electrode is in direct contact with a respective lower most conductive layer of the individual ones of the plurality of memory devices. The device structure further includes an insulative hydrogen barrier layer on at least a sidewall of the individual ones of the plurality of memory devices; and a plurality of via electrodes, wherein individual ones of the plurality of via electrodes are on a respective one of the individual ones of the plurality of memory devices.

Techniques for forming one or more MIM trench capacitors over one or more planar MIM capacitors in an interconnect region above or below a device layer of an integrated circuit. The MIM trench capacitor(s) is in one or more interconnect layers of the interconnect region, and can have a relatively high height. The MIM trench capacitor includes a first electrode, a capacitor dielectric on the first electrode, and a second electrode on the capacitor dielectric, and runs along the outside surface of a plurality of dielectric fins, which increases the surface area of the capacitor within a relatively small plan footprint. A planar MIM capacitor is beneath the MIM trench capacitor within a same interconnect layer as the MIM trench capacitor. The planar MIM capacitor includes first and second planar electrodes separated by a capacitor dielectric, and may be electrically isolated from, or capacitively coupled to, the MIM trench capacitor.

Electronic component, which includes: a layered busbar structure (212) comprising at least two busbar layers (212A-C) separated by an insulating layer; a transistor (214) connected to the layered busbar structure (212) on a first side thereof; and a capacitor (100) which is mounted on the first side of the layered busbar structure (212) and is positioned further away from the layered busbar structure (212) than the transistor (214), wherein the capacitor (100) has respective planar terminals (102, 104) which are parallel to each other and perpendicular to the layered busbar structure (212), wherein each of the planar terminals (102, 104) comprises a rectangular element, one side of which is connected to the capacitor (100) and the opposite end is connected to a corresponding busbar layer (212A-C), wherein each of the planar terminals (102, 104) has several feeder lines (108, 110) at the opposite end of the rectangular element, the feeder lines (108, 110) connecting the respective planar terminal (102, 104) to the corresponding busbar layer.

A system for collection of static electricity deploys a plurality of planar capacitors connected in parallel and aligned to form a capacitor stack, which has two parallel and opposing major surfaces arranged for receiving a static electricity charge from the atmosphere. The system also includes electronic circuitry in communication with the capacitor stack. The electronic circuitry is configured to cause the static electricity charge to at least partially discharge thereinto so as to prepare the capacitor stack for receiving an additional static electricity charge from the atmosphere.

The invention relates to a capacitive ultrasonic sensor, which comprises a first planar electrode and a second planar electrode which are oppositely arranged, the first planar electrode and the second planar electrode are at least partially attached and are insulated to form a stable planar capacitor; wherein the first planar electrode is a conductive film. According to the ultrasonic sensor, the first planar electrode and the second planar electrode are used for replacing a piezoelectric ceramic piece to form a planar capacitor, and the technical defects caused by the piezoelectric ceramic piece production technology are avoided.

Embodiments of the present invention disclose an integrated passive device, a manufacturing method thereof, and a semiconductor device. By adopting a sandwich structure of a first flexible substrate + a glass substrate + a second flexible substrate to replace the single-layer glass substrate structure in the related art, the present invention can increase the device strength and compensate for the problem of reduced strength after punching and filling a conductive structure in the glass substrate. Moreover, by designing a three-dimensional inductor structure and a planar capacitor structure, the present invention can improve the quality factor (i.e., Q factor) of the inductor, thereby reducing losses and improving the reliability of the integrated passive device.

The invention relates to a robust device for measuring water available to plants in soils used for agriculture. In parallel to this, the device is also intended to measure the fertiliser content. The device comprises the following features: two planar capacitors (1a, b) and an electronic circuit (5) which is designed to evaluate changes in capacitance of the planar capacitors (1a, b). The circuit (5) is arranged in a stable protective shell. The planar capacitors (1a, b) are covered with a water-permeable protective body. The planar capacitors (1a, b) are protected from damage during a replacement of the protective body (6), by means of an anti-rotation device (11).

This invention discloses a MEMS capacitive pressure sensor structure and its manufacturing method, belonging to the field of pressure sensor technology. It employs a planar capacitor structure, where a doped layer is formed on a substrate to create the lower electrode of the capacitive pressure sensor. Multiple structural layers are deposited on this doped layer to form the upper electrode. A first insulating dielectric layer and a cavity are disposed between the upper and lower electrodes, from bottom to top. This invention features a simple structure and convenient fabrication. Furthermore, the entire fabrication process is performed on the front side of the substrate, a planar process, eliminating the need for front-back alignment and facilitating single-chip integration with CMOS technology.

The invention discloses a SiC SBD diode capable of reducing electric leakage and a preparation method, and relates to the technical field of semiconductors. In the SiC SBD diode, a Poly electrode and an N-drift layer are insulated by using an oxide layer to form a planar capacitor, and the two sides of the Poly electrode repel surrounding electrons during reverse blocking, so that a depletion region of the upper N-drift layer is expanded, the electric field intensity at a Schottky interface is reduced, the Schottky effect is weakened, and electric leakage is reduced. And meanwhile, the P-type masking layer extends into the N-drift layer by utilizing an etched groove and is connected with the positive electrode at an equal potential, and when the device is reversely blocked, an electric field peak value moves downwards from the surface and is far away from a Schottky interface, so that electric leakage is reduced.

The invention relates to a manufacturing method of a high-reliability polymer dielectric material. The manufacturing method comprises the following steps: providing an inorganic filler, a matrix material, a first auxiliary agent, a second auxiliary agent and a solvent; dissolving an inorganic filler and a first auxiliary agent in a solvent, and uniformly mixing to form a first mixed solution; dissolving a base material and a second auxiliary agent in a solvent, and uniformly mixing to form a second mixed solution; uniformly mixing the first mixed solution and the second mixed solution according to a weight ratio of 1: 1-60: 1 to form a polymer dielectric material; and carrying out negative pressure treatment on the polymer dielectric material to remove bubbles in the polymer dielectric material so as to form the polymer dielectric material with the reliability. The invention also relates to a planar capacitor material using the polymer dielectric material and a manufacturing method thereof.

To provide a chip part that allows capacitance to be set in a wider variety of ways.SOLUTION: A chip part A1 includes a substrate 1, a first capacitor structure 3A formed on the substrate 1, a second capacitor structure 3B formed on the substrate 1, and a first external electrode 2A and a second external electrode 2B. The first capacitor structure 3A and the second capacitor structure 3B are electrically connected in parallel to each other. The substrate 1 has a substrate main surface 11 that is perpendicular to a first direction. The second capacitor structure 3B is a planer capacitor along a substrate main surface 11. The second capacitor structure 3B includes a plurality of capacitor elements 300B electrically connected in parallel to each other and a plurality of fuse parts 429B respectively arranged between the plurality of capacitor elements 300B and the second external electrode 2B.SELECTED DRAWING: Figure 3

The utility model relates to an ultrasonic sensor, which comprises a first planar electrode and a second planar electrode which are oppositely arranged, the first planar electrode and the second planar electrode are at least partially attached and are insulated from each other to form a stable planar capacitor; wherein the first planar electrode comprises an insulating film and a first conductive layer which is arranged on one side, facing the second planar electrode, of the insulating film; the second planar electrode comprises a conductive substrate; an insulating layer is arranged between the first conductive layer and the conductive substrate. According to the ultrasonic sensor, the first planar electrode and the second planar electrode are used for replacing a piezoelectric ceramic piece to form a planar capacitor, and the technical defects caused by the piezoelectric ceramic piece production technology are avoided.

The invention discloses a planar capacitor and a preparation method thereof, and relates to the technical field of capacitors. The capacitor assembly is located on the surface of the substrate and comprises a bottom electrode layer, a dielectric layer and a top electrode layer which are sequentially stacked on the surface of the substrate; a capping layer covering the top electrode layer; the interconnection structure comprises a first conductive column and a second conductive column, and the second conductive column penetrates through the covering layer and is in contact connection with the top electrode layer; the first conductive column penetrates through the covering layer, the top electrode layer and the dielectric layer and is in contact connection with the bottom electrode layer; on the plane where the top electrode layer is located, at least part of the covering layer is located between the first conductive column and the top electrode layer. According to the invention, the interconnection structure electrically connected with the electrode layer can be formed without forming a large-size step structure in the capacitor assembly, and the opposite area of the bottom electrode layer and the top electrode layer is increased, so that the capacitance density of the planar capacitor can be improved.

A sensor arrangement for sensing a filled state of an absorbent article having a liquid absorbing layer, the sensor arrangement comprising: a substrate; a plurality of planar capacitors, each planar capacitor comprising a set of at least two corresponding capacitor electrodes, the set of at least two corresponding capacitor electrodes being disposed on or in the substrate close to each other; and a plurality of conductor paths on or in the substrate connecting the capacitor electrodes towards the terminals of the readout circuit, where at least two of the planar capacitors are connected in parallel.

The invention relates to an ultrasonic sensor. The ultrasonic sensor comprises a first planar electrode and a second planar electrode which are oppositely arranged, the first planar electrode and the second planar electrode are at least partially attached and are insulated from each other to form a stable planar capacitor; wherein the first planar electrode comprises an insulating film and a first conductive layer which is arranged on one side, facing the second planar electrode, of the insulating film; the second planar electrode comprises a conductive substrate; an insulating layer is arranged between the first conductive layer and the conductive substrate. According to the ultrasonic sensor, the first planar electrode and the second planar electrode are used for replacing a piezoelectric ceramic piece to form a planar capacitor, and the technical defects caused by the piezoelectric ceramic piece production technology are avoided.

The utility model discloses a polycrystalline silicon groove SiC diode with a P-type masking layer, and relates to the technical field of semiconductors. In the SiC SBD diode, a Poly electrode and an N-drift layer are insulated by using an oxide layer to form a planar capacitor, and the two sides of the Poly electrode repel surrounding electrons during reverse blocking, so that a depletion region of the upper N-drift layer is expanded, the electric field intensity at a Schottky interface is reduced, the Schottky effect is weakened, and electric leakage is reduced. And meanwhile, the P-type masking layer extends into the N-drift layer by utilizing an etched groove and is connected with the positive electrode at an equal potential, and when the device is reversely blocked, an electric field peak value moves downwards from the surface and is far away from a Schottky interface, so that electric leakage is reduced.

Embodiments disclosed herein include a capacitor apparatus. In an embodiment, the apparatus comprises a first metal layer and a first plate above the first metal layer, where the first plate is electrically conductive. In an embodiment, a second plate is above the first plate, where the second plate is electrically conductive, and a third plate is above the second plate, where the third plate is electrically conductive. In an embodiment, a second metal layer is above the third plate, and a first via is between the first metal layer and the second metal layer, where the first via contacts the first plate and the third plate. In an embodiment, a second via is between the first metal layer and the second metal layer, where the second via contacts the second plate, and a third via is between the first metal layer and the first plate.

Device for measuring the water content and fertilizer content of soils, wherein the device has the following features: - two planar capacitors (1a, b) formed on the top and bottom surfaces of a first plastic printed circuit board (2), each planar capacitor (1a, b) consisting of a copper layer with interlocking structures, and the printed circuit board (2) being covered on all sides with a water-impermeable plastic layer (3), - a second printed circuit board (4) comprising an electronic circuit (5) configured to evaluate capacitance changes of the planar capacitors (1a, b), wherein the first printed circuit board (2) is signal-contacted and mechanically connected to the second printed circuit board (4), - a porous protective body (6) that encloses the first circuit board (2), - an inner sleeve (7) in which the assembly of the first printed circuit board (2) and the second printed circuit board (4) is arranged, wherein the second printed circuit board (4) is encapsulated on all sides with a potting compound (8), - an outer tube (9) in which the inner sleeve (7) is arranged, wherein the outer tube (9) has a thread onto which - a plastic cap (10) with openings is screwed on, which fixes the protective body (6) and - at least 2 tapered and opposing ribs (11) arranged on the inner wall of the inner sleeve (7).

The invention relates to a robust device for measuring the water available to plants in agriculturally used soils. The device is also intended to measure the fertilizer content. The device comprises the following features: two planar capacitors (1a, b) and an electronic circuit (5) configured to evaluate changes in the capacitance of the planar capacitors (1a, b). The circuit (5) is housed in a robust protective casing. The planar capacitors (1a, b) are covered with a water-permeable protective body. An anti-rotation device (11) prevents damage to the planar capacitors (1a, b) when the protective body (6) is replaced.

The present invention discloses a metal capacitor. The metal capacitor comprises a first metal layer and a second metal layer arranged above a substrate. The first metal layer comprises a first electrode sheet and a second electrode sheet. The second metal layer comprises a third electrode sheet and a fourth electrode sheet. A first planar capacitor is formed between the first electrode sheet and the second electrode sheet; a second planar capacitor is formed between the third electrode sheet and the fourth electrode sheet. At least a portion of the fourth electrode sheet is located above the first electrode sheet, and a first longitudinal capacitor is formed between the first electrode sheet and the fourth electrode sheet. At least a portion of the third electrode sheet is located above the second electrode sheet, and a second longitudinal capacitor is formed between the second electrode sheet and the third electrode sheet.

The embodiment of the invention discloses a memory array and a preparation method thereof, a memory and electronic equipment, and relates to the technical field of semiconductors. The memory array comprises a laminated structure, the laminated structure is provided with a groove group, the groove group comprises grooves, and the grooves extend along a first direction and penetrate through the laminated structure. The laminated structure comprises a plurality of first dielectric layers and a plurality of first conductive layers which are alternately laminated along a third direction. The memory array also includes a plurality of second conductive layers and a memory medium layer within the trench. The plurality of second conductive layers are arranged at intervals at least along the first direction. The storage medium layers are located between the second conductive layers and the side walls of the grooves. The first direction, the second direction and the third direction are perpendicular to one another. Through the arrangement of the groove, the size of the storage unit can be miniaturized, the storage density of the storage array can be improved, the storage capacitor can be of a planar capacitor structure, the electrical property difference of different storage capacitors in the same storage unit can be reduced, and the remanent polarization intensity of the storage medium layer can be improved.

The invention provides a mixed ACIM and DCIM circuit based on a 1T-nC-1T FeRAM, and belongs to the technical field of novel storage and calculation. The circuit comprises a novel 1T-nC-1T FeRAM device structure, a plurality of ferroelectric capacitors connected in parallel form an nC structure, each ferroelectric capacitor adopts a planar capacitor structure or a three-dimensional cylindrical capacitor structure and forms the nC structure through planar parallel connection or three-dimensional vertical stacking, a top electrode of the nC structure is connected with source electrodes of two transistors to form the 1T-nC-1T structure, and a top electrode of the nC structure is connected with source electrodes of the two transistors to form the 1T-nC-1T structure. A bottom electrode of the nC structure is used as a plate line PL, a grid electrode and a drain electrode of the transistor are respectively used as a word line WL and a bit line BL, and the 1T-nC-1T structure forms a regular array structure in the horizontal direction and the vertical direction; the WL in the 1T-nC array is parallel to the PL, the BL in the 1T-nC array is perpendicular to the PL and is used for parallel computing of the ACIM, and the WL in the nC-1T array is perpendicular to the PL, the BL in the nC-1T array is perpendicular to the PL and is used for row-by-row computing of the DCIM; the method has the advantages of high calculation parallelism and high energy efficiency of the ACIM and high precision and high robustness of the DCIM, and the problem of write crosstalk of an nC structure is solved.

The invention discloses a preparation method of a deep trench capacitor structure based on RDL wiring, and the method comprises the following steps: S1, providing a deep trench capacitor structure which comprises at least two conductive layers with different potentials, and the upper surfaces of the conductive layers are covered by a first interlayer dielectric layer; s2, patterning the first interlayer dielectric layer to form via holes exposing different conductive layers; s3, a first redistribution layer is prepared on the first interlayer dielectric layer, the first redistribution layer comprises two electrode layers which are electrically isolated from each other, the two electrode layers are connected to conductive layers with different potentials respectively, patterns of the at least two electrode layers are alternately arranged on a plane in an interdigital shape or a spiral shape, and the patterns of the at least two electrode layers are arranged on the surface of the first interlayer dielectric layer; therefore, a planar capacitor structure connected in parallel with the deep groove capacitor is formed. According to the invention, the interdigital capacitor is connected in parallel on the basis of the MIM capacitor to form a composite capacitor structure, the advantage of high capacitance density of the DTC is maintained, the equivalent series inductance is reduced, and the working bandwidth of the capacitor is expanded.

The invention discloses a semiconductor structure and a forming method thereof. The method comprises the following steps: providing a substrate, and etching a first surface of the substrate to form a plurality of grooves; sequentially forming a lower pole plate, a dielectric layer and an upper pole plate of the trench capacitor in the trench; a first through hole conductive structure is formed above at least part of the grooves, and the first through hole conductive structure is electrically connected to the lower pole plate in the groove below the first through hole conductive structure and is electrically connected with the metal wire located on the second face of the substrate through the lower pole plate; the first through hole conductive structure and the second through hole conductive structure used for being connected with an upper electrode plate of the groove capacitor can be synchronously formed, and plane capacitors can be prepared in parallel while the groove capacitor is formed. According to the invention, through pre-forming and embedding the through hole conductive structure in the groove etching and capacitor preparation stage, the etching depth required by the subsequent top layer through hole can be obviously shortened, the high aspect ratio etching difficulty and the side wall damage risk are reduced, the metal filling is improved, and the interconnection alignment tolerance and yield are improved; and meanwhile, the method is compatible with the existing planar capacitor and rear-end interconnection process, and is beneficial to the reliability and the process stability of the device.