18 results about "Planar capacitor" patented technology

A method of fabricating a system includes fabricating a plurality of transistors and coupling a forming a bridge structure connected between a gate contact of a first transistor with a drain contact of a second transistor. The method further includes fabricating a multi-level memory structure including capacitors that comprise a ferroelectric material or a paraelectric material. The capacitors within a given level are coupled together by a plate electrode. The method further includes forming a signal electrode coupled with the plate electrode.

Techniques for forming one or more MIM trench capacitors over one or more planar MIM capacitors in an interconnect region above or below a device layer of an integrated circuit. The MIM trench capacitor(s) is in one or more interconnect layers of the interconnect region, and can have a relatively high height. The MIM trench capacitor includes a first electrode, a capacitor dielectric on the first electrode, and a second electrode on the capacitor dielectric, and runs along the outside surface of a plurality of dielectric fins, which increases the surface area of the capacitor within a relatively small plan footprint. A planar MIM capacitor is beneath the MIM trench capacitor within a same interconnect layer as the MIM trench capacitor. The planar MIM capacitor includes first and second planar electrodes separated by a capacitor dielectric, and may be electrically isolated from, or capacitively coupled to, the MIM trench capacitor.

Electronic component, which includes: a layered busbar structure (212) comprising at least two busbar layers (212A-C) separated by an insulating layer; a transistor (214) connected to the layered busbar structure (212) on a first side thereof; and a capacitor (100) which is mounted on the first side of the layered busbar structure (212) and is positioned further away from the layered busbar structure (212) than the transistor (214), wherein the capacitor (100) has respective planar terminals (102, 104) which are parallel to each other and perpendicular to the layered busbar structure (212), wherein each of the planar terminals (102, 104) comprises a rectangular element, one side of which is connected to the capacitor (100) and the opposite end is connected to a corresponding busbar layer (212A-C), wherein each of the planar terminals (102, 104) has several feeder lines (108, 110) at the opposite end of the rectangular element, the feeder lines (108, 110) connecting the respective planar terminal (102, 104) to the corresponding busbar layer.

This invention discloses a MEMS capacitive pressure sensor structure and its manufacturing method, belonging to the field of pressure sensor technology. It employs a planar capacitor structure, where a doped layer is formed on a substrate to create the lower electrode of the capacitive pressure sensor. Multiple structural layers are deposited on this doped layer to form the upper electrode. A first insulating dielectric layer and a cavity are disposed between the upper and lower electrodes, from bottom to top. This invention features a simple structure and convenient fabrication. Furthermore, the entire fabrication process is performed on the front side of the substrate, a planar process, eliminating the need for front-back alignment and facilitating single-chip integration with CMOS technology.

The invention discloses a planar capacitor and a preparation method thereof, and relates to the technical field of capacitors. The capacitor assembly is located on the surface of the substrate and comprises a bottom electrode layer, a dielectric layer and a top electrode layer which are sequentially stacked on the surface of the substrate; a capping layer covering the top electrode layer; the interconnection structure comprises a first conductive column and a second conductive column, and the second conductive column penetrates through the covering layer and is in contact connection with the top electrode layer; the first conductive column penetrates through the covering layer, the top electrode layer and the dielectric layer and is in contact connection with the bottom electrode layer; on the plane where the top electrode layer is located, at least part of the covering layer is located between the first conductive column and the top electrode layer. According to the invention, the interconnection structure electrically connected with the electrode layer can be formed without forming a large-size step structure in the capacitor assembly, and the opposite area of the bottom electrode layer and the top electrode layer is increased, so that the capacitance density of the planar capacitor can be improved.

The utility model discloses a polycrystalline silicon groove SiC diode with a P-type masking layer, and relates to the technical field of semiconductors. In the SiC SBD diode, a Poly electrode and an N-drift layer are insulated by using an oxide layer to form a planar capacitor, and the two sides of the Poly electrode repel surrounding electrons during reverse blocking, so that a depletion region of the upper N-drift layer is expanded, the electric field intensity at a Schottky interface is reduced, the Schottky effect is weakened, and electric leakage is reduced. And meanwhile, the P-type masking layer extends into the N-drift layer by utilizing an etched groove and is connected with the positive electrode at an equal potential, and when the device is reversely blocked, an electric field peak value moves downwards from the surface and is far away from a Schottky interface, so that electric leakage is reduced.

The invention provides a mixed ACIM and DCIM circuit based on a 1T-nC-1T FeRAM, and belongs to the technical field of novel storage and calculation. The circuit comprises a novel 1T-nC-1T FeRAM device structure, a plurality of ferroelectric capacitors connected in parallel form an nC structure, each ferroelectric capacitor adopts a planar capacitor structure or a three-dimensional cylindrical capacitor structure and forms the nC structure through planar parallel connection or three-dimensional vertical stacking, a top electrode of the nC structure is connected with source electrodes of two transistors to form the 1T-nC-1T structure, and a top electrode of the nC structure is connected with source electrodes of the two transistors to form the 1T-nC-1T structure. A bottom electrode of the nC structure is used as a plate line PL, a grid electrode and a drain electrode of the transistor are respectively used as a word line WL and a bit line BL, and the 1T-nC-1T structure forms a regular array structure in the horizontal direction and the vertical direction; the WL in the 1T-nC array is parallel to the PL, the BL in the 1T-nC array is perpendicular to the PL and is used for parallel computing of the ACIM, and the WL in the nC-1T array is perpendicular to the PL, the BL in the nC-1T array is perpendicular to the PL and is used for row-by-row computing of the DCIM; the method has the advantages of high calculation parallelism and high energy efficiency of the ACIM and high precision and high robustness of the DCIM, and the problem of write crosstalk of an nC structure is solved.

The invention discloses a preparation method of a deep trench capacitor structure based on RDL wiring, and the method comprises the following steps: S1, providing a deep trench capacitor structure which comprises at least two conductive layers with different potentials, and the upper surfaces of the conductive layers are covered by a first interlayer dielectric layer; s2, patterning the first interlayer dielectric layer to form via holes exposing different conductive layers; s3, a first redistribution layer is prepared on the first interlayer dielectric layer, the first redistribution layer comprises two electrode layers which are electrically isolated from each other, the two electrode layers are connected to conductive layers with different potentials respectively, patterns of the at least two electrode layers are alternately arranged on a plane in an interdigital shape or a spiral shape, and the patterns of the at least two electrode layers are arranged on the surface of the first interlayer dielectric layer; therefore, a planar capacitor structure connected in parallel with the deep groove capacitor is formed. According to the invention, the interdigital capacitor is connected in parallel on the basis of the MIM capacitor to form a composite capacitor structure, the advantage of high capacitance density of the DTC is maintained, the equivalent series inductance is reduced, and the working bandwidth of the capacitor is expanded.

The invention discloses a semiconductor structure and a forming method thereof. The method comprises the following steps: providing a substrate, and etching a first surface of the substrate to form a plurality of grooves; sequentially forming a lower pole plate, a dielectric layer and an upper pole plate of the trench capacitor in the trench; a first through hole conductive structure is formed above at least part of the grooves, and the first through hole conductive structure is electrically connected to the lower pole plate in the groove below the first through hole conductive structure and is electrically connected with the metal wire located on the second face of the substrate through the lower pole plate; the first through hole conductive structure and the second through hole conductive structure used for being connected with an upper electrode plate of the groove capacitor can be synchronously formed, and plane capacitors can be prepared in parallel while the groove capacitor is formed. According to the invention, through pre-forming and embedding the through hole conductive structure in the groove etching and capacitor preparation stage, the etching depth required by the subsequent top layer through hole can be obviously shortened, the high aspect ratio etching difficulty and the side wall damage risk are reduced, the metal filling is improved, and the interconnection alignment tolerance and yield are improved; and meanwhile, the method is compatible with the existing planar capacitor and rear-end interconnection process, and is beneficial to the reliability and the process stability of the device.

The invention provides a one-dimensional stress measurement device. The one-dimensional stress measurement device comprises a to-be-measured structural member and a circuit board, the to-be-measured structural member comprises at least one protruding metal strip, the circuit board comprises a metalized groove corresponding to the protruding metal strip and a stress detection circuit, and the protruding metal strip is perpendicular to the plane of the to-be-measured structural member; after the protruding metal strips are inserted into the metallized grooves corresponding to the protruding metal strips, planar capacitors corresponding to the protruding metal strips are formed, one end of each planar capacitor is connected with one end of the stress detection circuit, and the other end of each planar capacitor is grounded; the planar capacitor is used for generating a capacitance effect under the action of an external force, and the stress detection circuit is used for detecting a capacitance value of the planar capacitor and converting the capacitance value of the planar capacitor into frequency to obtain a stress measurement result corresponding to the planar capacitor. The stress measurement result is used for indicating the stress condition of the to-be-measured structural member in the direction of the rotating shaft. The installation process is simple, no additional part needs to be pasted, and the measurement result is accurate.

The invention discloses a power semiconductor structure, a preparation method thereof and electronic equipment, and relates to the technical field of semiconductors. The power semiconductor structure comprises a circuit board, a power chip and a planar capacitor. The circuit board comprises a plurality of conductive layers which are arranged in a stacked mode. The power chip is embedded in the circuit board. The planar capacitor is embedded in the circuit board and is stacked with the plurality of conductive layers; the planar capacitor is electrically connected with the power chip. The power semiconductor structure is relatively high in integration level and relatively small in parasitic inductance, so that the power semiconductor structure has relatively high power density.

A capacitor element including: a planar capacitor layer; and a sealing layer that includes a first insulation portion covering a first main surface of the capacitor layer and a second insulation portion covering a second main surface of the capacitor layer, the capacitor layer includes a plurality of through portions passing therethrough, the plurality of through portions include one or more first through portions and one or more second through portions, a width of an end portion of the first through portions on a first insulation portion side is larger than a width of an end portion of the first through portions on a second insulation portion side, and a width of an end portion of the second through portions on the first insulation portion side is smaller than a width of an end portion of the second through portions on the second insulation portion side.

This application provides a capacitor assembly for an array substrate, an array substrate, a manufacturing method thereon, and a display panel. The capacitor assembly includes: a first electrode layer and a second electrode layer spaced apart; at least a portion of the capacitor assembly has a rolled structure extending along a first direction, and the first electrode layer and the second electrode layer are respectively rolled up when projected onto a plane perpendicular to the first direction. By providing a capacitor assembly with a rolled structure, compared to a planar capacitor, the projected area of ​​the capacitor assembly on the array substrate can be reduced, improving the light transmittance of the array substrate and thus improving the display effect; furthermore, the rolled shape of the capacitor assembly can increase the area of ​​the first electrode layer and the second electrode layer, that is, further increase the capacitance of the capacitor assembly and improve the display effect of the array substrate.

The technology described herein is directed towards a planar-type capacitor with a modified design (relative to standard capacitors), in which an array of interconnects facilitates electrical surface current flow between the first conductor and the second conductor, determines the self-resonant frequency of the capacitor, and provides an improved quality factor to an extent. The array (or enlarged area) of conducting interconnects results in capacitors with larger self-resonant frequency, e.g., having a substantially stable capacitance over a range of high radio frequencies, including millimeter wave frequencies. The designs described herein further decouple the capacitor's quality factor from the self-resonant frequency, based on a design modification to the shape of the RF signal port that changes the capacitor's parasitic inductance, facilitating greater flexibility in radio frequency component tuning. The modified capacitor provides benefits in various circuits, e.g., in an impedance or a millimeter wave frequency phase shifter for antenna elements.

A sensor arrangement for sensing a filling state of an absorbent article with a liquid absorbent layer, the sensor arrangement comprising a substrate, a plurality of planar capacitors, each one comprising a set of at least two corresponding capacitor electrodes being arranged next to each other on or in the substrate, and a plurality of conductor paths on or in the substrate connecting the capacitor electrodes toward terminals of a readout circuit, wherein at least two of said planar capacitors are connected in parallel.

The utility model provides a planar capacitor material with uniform thickness, which comprises a first electrode plate and a second electrode plate which are oppositely arranged, and at least one dielectric layer connected between the first electrode plate and the second electrode plate, and the dielectric layer comprises a first dielectric film and a second dielectric film, the first dielectric film comprises a first thick area and a first thin area, the second dielectric film comprises a second thick area and a second thin area, the first thick area and the second thin area are covered together, the second thick area and the first thin area are covered together, and the first thin area and the second thin area are covered together. The sum of the thickness of the first thick area and the thickness of the second thin area is equal to the sum of the thickness of the second thick area and the thickness of the first thin area. The thickness of the first dielectric film and the thickness of the second dielectric film of the uniform-thickness planar capacitor material are complementary, so that the uniform thickness of each part of the dielectric layer is ensured.

IC devices implementing memory with one access transistor coupled to multiple capacitors are disclosed. An example IC device includes a transistor having a region, wherein the region is either a source region or a drain region. Such an IC device further includes first and second platelines, and first and second capacitors, wherein a first capacitor electrode of the first capacitor is coupled to the region, a first capacitor electrode of the second capacitor is coupled to the region, a second capacitor electrode of the first capacitor is coupled to the first plateline, a second capacitor electrode of the second capacitor is coupled to the second plateline, the first capacitor is a three-dimensional capacitor, and the second capacitor is a planar capacitor.

The technology described herein is directed towards a planar-type capacitor with a modified design (relative to standard capacitors), in which an array of interconnects facilitates electrical surface current flow between the first conductor and the second conductor, determines the self-resonant frequency of the capacitor, and provides an improved quality factor to an extent. The array (or enlarged area) of conducting interconnects results in capacitors with larger self-resonant frequency, e.g., having a substantially stable capacitance over a range of high radio frequencies, including millimeter wave frequencies. The designs described herein further decouple the capacitor's quality factor from the self-resonant frequency, based on a design modification to the shape of the RF signal port that changes the capacitor's parasitic inductance, facilitating greater flexibility in radio frequency component tuning. The modified capacitor provides benefits in various circuits, e.g., in an impedance or a millimeter wave frequency phase shifter for antenna elements.