1883 results about "Plate electrode" patented technology

Methods and apparatuses for plasma chemical vapor deposition (CVD). In particular, a plasma CVD apparatus having a cleaning function, has an improved shower plate with holes having a uniform cross-sectional area to yield a high cleaning rate. The shower plate may serve as an electrode, and may have an electrically conductive extension connected to a power source. The shower plate, through which both cleaning gases and reaction source gases flow, may include a hole machined surface area with a size different than conventionally used to ensure a good film thickness uniformity during a deposition process. The size of the hole machined surface area may vary based on the size of a substrate to be processed, or the size of the entire surface of the shower plate.

An inverted PCRAM cell is formed by plating the bottom electrode, made of copper for example, with a conductive material, such as silver. Chalcogenide material is disposed over the plated electrode and subjected to a conversion process so that ions from the plated material diffuse into the chalcogenide material.

A method includes forming a switching device which includes a vertical channel spaced apart from a semiconductor substrate, and forming a storage device which is positioned on opposed sides of the switching device. The storage device includes a cylindrically shaped storage node, a plate electrode coupled to the storage node, and a dielectric film which is formed between the storage node and plate electrode, the storage nodes being electrically connected to the switching device.

A capacitor with zirconium oxide and a method for fabricating the same are provided. The method includes: forming a storage node; forming a multi-layered dielectric structure on the storage node, the multi-layered dielectric structure including a zirconium oxide (ZrO₂) layer and an aluminum oxide (Al₂O₃) layer; and forming a plate electrode on the multi-layered dielectric structure.

A multicell assembly is constituted by alternately stacking two types of pre-assembled elements: a bipolar electrode holding subassembly and a membrane holding subassembly. The alternate stack of elements is piled over a bottom end element and the stack is terminated by placing over the last membrane holding element a top end electrode element. Each bipolar plate electrode holding element and each ion exchange membrane separator holding element includes a substantially similar rectangular frame piece, made of an electrically nonconductive and chemically resistant material, typically of molded plastic material, having on its upper (assembly) face grooves for receiving O-ring type gasket means, and having through holes and recesses in coordinated locations disposed along two opposite sides of the rectangular frame forming, upon completion of the assembling, ducts for the separate circulation of the negative electrolyte and of the positive electrolyte through all the negative electrolyte flow chambers and all positive electrolyte flow chambers, respectively, in cascade.

A sweep-type fingerprint sensor module includes a microprocessor and a sweep-type fingerprint sensor, which includes a substrate, and a sensing members array, a speed-detecting unit, and a processing circuit on the substrate. The array is composed of plural fingerprint sensing members. When the finger sweeps across the fingerprint sensor, the array sequentially acquires plural fingerprint fragment images from the finger with a sampling time interval. The speed-detecting unit is composed of first and second plate electrodes. The processing circuit processes and then outputs signals from the array and the speed-detecting unit. The microprocessor electrically connected to the processing circuit derives a sweeping speed of the finger by the time difference when the finger sweeps across the sensor surface and sequentially contacts the first and second plate electrodes, determines the sampling time interval and minimize the number of captured fragment images for re-construction of the initial complete fingerprint image.

Methods and devices for fabricating AlGaN/GaN normally-off high electron mobility transistors (HEMTs). A fluorine-based (electronegative ions-based) plasma treatment or low-energy ion implantation is used to modify the drain-side surface field distribution without the use of a field plate electrode. The off-state breakdown voltage can be improved and current collapse can be completely suppressed in LDD-HEMTs with no significant degradation in gains and cutoff frequencies.

An improved filter element for use in an electrostatic precipitation air cleaning device, the filter element including rod electrodes arranged through a stack of alternating fluted plastic sheets and plate electrodes. Successive plate electrodes are arranged to make contact with an alternating one or the other of the rod electrodes. The plate and rod electrodes may be composed of high impedance materials such as paper and plastic, respectively. An arrangement for removably inserting a filter element into an air cleaning device is provided. The arrangement also removably provides electrical connectivity between the filter element and the air cleaning device. The filter element can thus be readily removed and re-installed by a user.

A phase changeable memory device includes a lower interlayer dielectric layer on a semiconductor substrate. A plurality of first phase changeable data storage elements is disposed on the lower interlayer dielectric layer. A middle interlayer dielectric layer covers the first phase changeable data storage elements and the lower interlayer dielectric layer. A plurality of second phase changeable data storage elements is disposed on the middle interlayer dielectric layer. The first and second phase changeable data storage elements are arrayed in rows and columns such that respective first phase changeable data storage elements are disposed between respective adjacent second phase changeable data storage elements in the rows and columns. A plate electrode overlies the first and second phase changeable data storage elements and is electrically connected to the first and second phase changeable data storage elements. Related fabrication methods are also disclosed.

The invention relates to an experimental apparatus for acquiring large-area uniform discharge plasmas, which belongs to the technical field of plasmas. The experimental apparatus comprises a bipolar nanosecond pulse power supply, a reactor, multi-needle-to-plate electrodes, a gas distribution system, a spectral measurement system and a discharge measurement system, wherein the bipolar nanosecond pulse power supply drives dielectric barrier discharge of air and other gas mixtures among the multi-needle-to-plate electrodes in the reactor, and the gas mixtures are input to the reactor through the gas distribution system; the spectral measurement system collects photonic information of plasma discharge in real time and inputs the photonic information to a computer for spectral analysis; and the discharge measurement system collects discharge voltage and current of the high-voltage nanosecond pulse power supply in real time, and the discharge voltage and current are displayed through a digital oscilloscope. By virtue of the bipolar nanosecond narrow-pulse power supply, the large-area discharge plasmas are generated without a magnetic field; and the generated plasmas are uniform, diffusive, high in electron density, high in energy utilization ratio, low in energy consumption and easy to control in a discharge process.

A compound semiconductor device includes a group-III nitride semiconductor layer; an insulation film located on the group-III nitride semiconductor layer; a drain electrode located in a position which is a first distance away from an upper surface of the group-III nitride semiconductor layer; a source electrode located in a position which is the first distance away from the upper surface of the group-III nitride semiconductor layer; a gate electrode located between the drain electrode and the source electrode; and a field plate electrode located between the drain electrode and the gate electrode at a position which is a second distance away from the upper surface of the group-III nitride semiconductor layer, the second distance is shorter than the first distance.

A semiconductor device includes: a first semiconductor layer of non-doped Al_XGa_1-XN (0≦X<1); a second semiconductor layer of non-doped or n-type Al_YGa_1-YN (0<Y≦1, X<Y) on the first semiconductor layer; a first electrode on the second semiconductor layer; a second electrode on the second semiconductor layer that is separated from the first electrode and electrically connected to the second semiconductor layer; a first insulating film covering the first and second electrodes; a first field plate electrode electrically connected to the first electrode and covered by a second insulating film; and a second field plate electrode on the second insulating film, wherein a length of at least one of the first and second field plate electrodes in a first direction from the first electrode toward the second electrode changes periodically in a second direction intersecting the first direction.

An integrated circuit memory device includes a semiconductor substrate and a first electrically insulating layer that extends on the semiconductor substrate and has a first contact hole extending therethrough. An electrically conductive plug is provided in the first contact hole. A phase-change material layer pattern is provided as a non-volatile storage medium. The phase-change material layer pattern has a bottom surface that is electrically connected to the electrically conductive plug. A second electrically insulating layer is provided on the phase-change material layer pattern. The second electrically insulating layer has a second contact hole therein. This contact hole exposes a portion of an upper surface of the phase-change material layer pattern. To improve data writing efficiency, the area of the exposed portion of the upper surface of the phase-change material layer pattern is less than a maximum cross-sectional area of the electrically conductive plug. A plate electrode is also provided. This plate electrode is electrically connected to the phase-change material layer pattern. Barrier layers may also be provided directly on the plug and directly on the exposed portion of the upper surface.

The invention relates to a method for fabricating a capacitor of a semiconductor device including the steps of: forming storage nodes for being connected with predetermined portions of a semiconductor substrate; forming a surface nitride layer by performing a surface nitrification process for preventing formation of an oxide layer on the surface of the storage nodes that deteriorates dielectric characteristic of the layer; forming an alumina (Al2O3) layer as a dielectric layer on the surface nitride layer in a perovskite structure with superior electrical and mechanical strength; and forming a plate electrode on the dielectric layer, thereby forming a capacitor with capacitance high enough to achieve high integration of the semiconductor device.

Conductive lines constituting word lines of memory cells and conductive lines constituting memory cell plate electrodes are formed in the same interconnecting layer in a memory device including a plurality of memory cells each including a capacitor for storing data in an electrical charge form. By forming the capacitors of the memory cells into a planar capacitor configuration, a step due to the capacitors is removed. Thus. a dynamic semiconductor memory device can be formed through CMOS process, and a dynamic semiconductor memory device suitable for merging with logic is achieved. Data of 1 bit is stored by two memory cells, and data can be reliably stored even if the capacitance value of the memory cell is reduced due to the planar type capacitor.

A method for fabricating DRAM cells according to the present invention includes the steps of: forming a trench within a semiconductor substrate using a stacked layer as a mask, said stacked layer composed of a silicon oxide film and a silicon nitride film formed in an active region of said semiconductor substrate; forming a first insulation layer on a bottom and sides of said trench; depositing a first conductive layer on whole surface of said semiconductor substrate including said trench; etching back said conductive layer to be recessed from a top surface of said semiconductor substrate and forming bit lines of said first conductive layer on said bottom of said trench in a direction of column; filling a second insulation layer in said trench; removing said stacked layer and a part of said second insulation layer to expose said semiconductor substrate in said active region and planarizing said semiconductor substrate simultaneously; forming a gate insulation layer on said semiconductor substrate;forming a gate structure of a second conductive layer on said gate insulation layer; forming a spacer of an insulation layer on said sides of said gate structure of said second conductive layer; forming source and drain regions on both sides of said gate structure of said second conductive layer;forming a third insulation layer on said semiconductor substrate; connecting said bit lines to a first one of said source and drain regions with a plug of a third conductive layer filled in a contact hole inside said third insulation layer and said second insulation layer; forming a storage node electrode connected to a second one of said source and drain regions; andforming a plate electrode overlying a dielectric layer disposed said storage node electrode.Accordingly, the present invention has the buried bit lines in the trench, making it easy to secure a process margin in the subsequent process, maintaining a constant width of the bit lines to lower the resistance thereof. Furthermore, the bit lines disposed under the word lines has an advantage over patterning the node contact due to the low step height, with enhanced capacitance of the capacitor.

A balun circuit comprises a balun transformer having first and second windings, and first and second variable capacitors. The first variable capacitor has a first plate electrode coupled to the first terminal of the first winding, and a second plate electrode coupled to the second terminal of the first winding. The second variable capacitor has a first plate electrode coupled to the first terminal of the second winding, and a second plate electrode coupled to the second terminal of the second winding. The first variable capacitor is tunable between first and second capacitance values. The second variable capacitor is tunable between third and fourth capacitance values. Tuning the variable capacitors allows the balun circuit to be re-configurable to operate in both the first frequency band and the second frequency band.