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2767 results about "High electron" patented technology

Process for making and programming and operating a dual-bit multi-level ballistic MONOS memory

A fast low voltage ballistic program, ultra-short channel, ultra-high density, dual-bit multi-level flash memory is described with a two or three polysilicon split gate side wall process. The structure and operation of this invention is enabled by a twin MONOS cell structure having an ultra-short control gate channel of less than 40nm, with ballistic injection which provides high electron injection efficiency and very fast program at low program voltages of 3~5V. The cell structure is realized by (i) placing side wall control gates over a composite of Oxide-Nitride-Oxide (ONO) on both sides of the word gate, and (ii) forming the control gates and bit diffusion by self-alignment and sharing the control gates and bit diffusions between memory cells for high density. Key elements used in this process are: 1) Disposable side wall process to fabricate the ultra short channel and the side wall control gate with or without a step structure, and 2) Self-aligned definition of the control gate over the storage nitride and the bit line diffusion, which also runs in the same direction as the control gate. The features of fast program, low voltage, ultra-high density, dual-bit, multi-level MONOS NVRAM of the present invention include: 1) Electron memory storage in nitride regions within an ONO layer underlying the control gates, 2) high density dual-bit cell in which there are two nitride memory storage elements per cell, 3) high density dual-bit cell can store multi-levels in each of the nitride regions, 4) low current program controlled by the word gate and control gate, 5) fast, low voltage program by ballistic injection utilizing the controllable ultra-short channel MONOS, and 6) side wall control poly gates to program and read multi-levels while masking out memory storage state effects of the unselected adjacent nitride regions and memory cells. The ballistic MONOS memory cell is arranged in the following array: each memory cell contains two nitride regions for one word gate, and ½ a source diffusion and ½ a bit diffusion. Control gates can be defined separately or shared together over the same diffusion. Diffusions are shared between cells and run in parallel to the side wall control gates, and perpendicular to the word line.
Owner:HALO LSI INC

Manufacturing process for ultra slim electrooptic display device unit

To obtain a high intensity, high definition and sophisticated electrooptic display device unit such as transmissive type LCD, a semi-transmissive type LCD, a reflective type LCD, a surface emitter type organic EL, or an underside emitter type organic EL, etc. which has high electron and positive hole mobility and low leak electric current qualities.A porous semiconductor layer (low porous Si layer 11a / high porous Si layer 11b / low porous Si layer 11c), a monocrystalline Si layer12a, and the Si O2 layer 13a are formed on a monocrystalline Si substrate 10. The Si O2 layer 13a of the peripheral circuit area is removed, leaving the Si O2 layer 13a in the display area. The poly Si layer 14a is formed in the display area by semiconductor epitaxial growth, and a monocrystalline Si layer 12b is formed in the peripheral circuit area. Then, the display element section is formed in the poly Si layer 14 of the display area and the peripheral circuitry section is formed in the monocrystalline Si layer 12b of the peripheral circuit area. The assembly is divided into each ultra slim electrooptic display device unit after separation from the backing, and after the process of separating the Si substrate 10 from the porous Si layer 11b and by attaching the backing to the ultra slim electrooptic display element substrate after its separation. Each ultra slim electrooptic display device unit is divided after attaching the backing.
Owner:SONY CORP
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