22results about How to "Reduce dislocation density" patented technology

The invention relates to the technical field of semiconductor light emitting diodes, and discloses a composite patterned substrate and a preparation method thereof. The preparation method comprises the following steps: preparing a SiO2 film layer on a substrate; coining glue is prepared on the SiO2 film layer; transferring the pattern of the soft template to the SiO2 film layer by using a nanoimprint technology; performing etching treatment on the SiO2 film layer to form a graphic structure with a preset morphology, and etching to remove part of the substrate material to form a pit to obtain a patterned substrate; preparing an AlN layer on the substrate, filling the pit with the AlN layer, and covering the surface of the graphic structure; carrying out photoetching treatment and etching treatment on the AlN layer, so that the AlN layer is filled in the pit and covers the side surface of a part of the pattern structure; and carrying out annealing treatment, and removing the residual photoresist to obtain the composite patterned substrate. By implementing the preparation method provided by the invention, the obtained composite patterned substrate can improve the crystal quality of the epitaxial layer, thereby improving the internal quantum efficiency and final brightness of the chip.

The invention provides a method for heteroepitaxial growth of a gallium arsenide material on silicon by introducing laser surface treatment. The method comprises the following steps: growing a gallium arsenide low-temperature layer with a low crystallization degree on a silicon substrate, and crystallizing the surface layer of the gallium arsenide low-temperature layer by adopting a laser surface treatment mode; growing a gallium arsenide medium-temperature layer on the gallium arsenide low-temperature layer after the surface layer crystallization treatment, and purifying the surface layer crystalline state of the gallium arsenide medium-temperature layer by adopting a laser surface layer treatment mode; and growing a gallium arsenide high-temperature layer on the gallium arsenide medium-temperature layer after the surface layer crystalline state purification treatment. Under the condition that the crystallization degree of the whole gallium arsenide epitaxial layer is reserved, the crystallization degree of the local part, namely the upper surface of the epitaxial layer, is improved, the inhibition effect on dislocation is enhanced, and the optimization of the crystal quality of the whole epitaxial structure is realized. The dislocation penetrating to the surface of the whole epitaxial structure during heteroepitaxial growth of the gallium arsenide material on the silicon substrate is remarkably reduced, and a brand new way is opened up for preparing semiconductor photoelectric devices.

This invention discloses an epitaxial wafer for a deep ultraviolet (UV) light-emitting diode (LED) and its fabrication method, relating to the field of semiconductor optoelectronic devices. The UV LED epitaxial wafer includes a substrate and a buffer layer, an N-type AlGaN layer, an active layer, an electron blocking layer, and a P-type AlGaN layer sequentially grown on the substrate. The active layer has a periodic structure, with each period comprising a sequentially stacked quantum well layer and a quantum barrier layer, and the number of periods in the active layer is ≥2. The quantum barrier layer comprises a sequentially stacked AlInGaN layer and a P-AlInGaN layer. Implementing this invention can effectively improve the luminous efficiency of deep ultraviolet LEDs.

The utility model discloses a light emitting diode epitaxial wafer and a light emitting diode. The light emitting diode epitaxial wafer comprises a substrate, and a buffer layer, a U-GaN layer, an N-GaN layer, an insertion layer, a stress release layer, a multi-quantum well layer, an electron blocking layer and a P-GaN layer which are stacked on the substrate in sequence. Wherein the insertion layer at least comprises a Si3N4 layer. The light-emitting efficiency of the light-emitting diode provided by the utility model is obviously improved.

The utility model relates to the technical field of gallium oxide crystal growth, and discloses a crucible structure for growing a gallium oxide single crystal by a VB method, which comprises a crucible shell, a seed crystal cavity, a diameter-expanding cavity, a diameter-reducing cavity, a shoulder-expanding cavity and an equal-diameter cavity, the seed crystal cavity, the diameter-expanding cavity, the diameter-reducing cavity, the shoulder-expanding cavity and the equal-diameter cavity are arranged in the crucible shell, the seed crystal cavity is arranged at one end of the crucible shell, and the diameter-reducing cavity is arranged at the other end of the crucible shell. One end of the seed crystal cavity is closed, the other end of the seed crystal cavity is connected with the diameter-expanding cavity, the diameter-expanding cavity is connected with the diameter-reducing cavity, the diameter-reducing cavity is connected with the shoulder-expanding cavity, the shoulder-expanding cavity is connected with the equal-diameter cavity, and the other end of the equal-diameter cavity is open. Through reasonable design of a gallium oxide growth technology, the crucible shell, the seed crystal cavity, the diameter-expanding cavity, the diameter-reducing cavity, the shoulder-expanding cavity and the equal-diameter cavity are adopted, so that gallium oxide crystals can be separated from the crucible wall during growth and cooling, dislocation proliferation and twin crystal structures are not easy to appear, the crystal dislocation density is reduced, and the performance of a semiconductor chip is improved. The crucible structure can be used for preparing cylindrical gallium oxide single crystals with low dislocation density.

This invention provides a light-emitting diode epitaxial wafer and its fabrication method. The light-emitting diode epitaxial wafer includes a substrate, and a buffer layer, an undoped GaN layer, an N-type GaN layer, a multiple quantum well layer, an electron blocking layer, and a P-type GaN layer sequentially deposited on the substrate. The buffer layer includes a nitrided graphene buffer layer, an h-BN buffer layer, and a B-type GaN layer sequentially deposited on the substrate. x Al 1‑x N buffer layer, AlN buffer layer, wherein, the B x Al 1‑x The boron content in the N-buffer layer gradually decreases along the growth direction of the epitaxial layer. This invention achieves this by sequentially arranging a graphene nitride buffer layer, an h-BN buffer layer, and a boron buffer layer between the substrate and the epitaxial structure. x Al 1‑x N-buffer layers and AlN-buffer layers reduce lattice mismatch between structures, lower defect density, and improve the overall quality of LED epitaxial wafers.

This invention discloses a germanium photodetector and semiconductor device. The germanium photodetector includes: a silicon substrate; a first germanium thin film layer deposited on the silicon substrate; the first germanium thin film layer having multiple penetrating dislocations extending through its thickness; multiple pits corresponding one-to-one with the multiple penetrating dislocations formed on the surface of the first germanium thin film layer, and the inner surface of each pit being covered with an amorphous material layer; and a second germanium thin film layer deposited on the surface of the first germanium thin film layer and on the amorphous material layer within each pit, filling each pit. The amorphous material layer effectively blocks the extension of dislocations, reduces dislocation density, and ensures the photoelectric conversion efficiency of the device. Furthermore, by integrating the epitaxial chamber, deposition chamber, and pre-cleaning chamber into the same semiconductor device through a transfer chamber to produce the germanium photodetector, the contact path of external contaminants is reduced, the process flow is simplified, production efficiency is improved, and space and cost are optimized.

The invention provides a preparation method of a composite patterned substrate, the composite patterned substrate and an LED chip, and the method comprises the steps: forming a plurality of holes in the surface of a sapphire substrate, and carrying out the gluing, exposure and development processing, and obtaining a preset pattern; depositing a SiOF layer on the substrate; removing the preset pattern below the SiOF layer through heat treatment to form a cavity; transferring a pattern on the substrate through a nanoimprint technology; and performing inductively coupled plasma etching to form a composite pattern structure. A cavity structure is formed in a sapphire substrate through laser drilling and heat treatment, the light extraction efficiency of an LED is improved by combining with a composite pattern constructed by a nanoimprint technology and utilizing a multi-interface light scattering effect, the propagation direction of light rays can be guided by combining a patterned structure with a cavity, light emitting angle distribution is optimized, and light emitting is more uniform or the directivity is more concentrated; epitaxial growth stress is released through the cavity, dislocation density is reduced, epitaxial layer cracks are effectively inhibited, and crystal integrity is improved.

This invention discloses a rapid annealing apparatus and method for micro / nano-scale metal samples. A metal indenter and a micro / nano-scale metal sample are prepared separately. The micro / nano-scale metal sample is placed at the fixed end of an electromechanical sample rod, while the metal indenter is mounted on the movable end, with the two ends facing each other without contact. Under a transmission electron microscope, the metal indenter is aligned and brought closer to the sample by a piezoelectric ceramic drive. After the indenter and the micro / nano-scale metal sample reach critical contact, several pulsed currents are applied. Then, by controlling the displacement of the piezoelectric ceramic, the cyclic movement of the metal indenter is achieved, thereby applying a constant strain amplitude of pressure-pressure cyclic loading to the micro / nano-scale metal sample. Then, pulsed currents are applied again, and this process is repeated multiple times, thus achieving rapid annealing of the micro / nano-scale metal sample using electromechanical coupling. The micro / nano-scale metal sample annealing method of this invention allows for in-situ observation at the micro / nano scale, with controllable parameters, high success rate, high efficiency, and good stability.

This application discloses a GaN-based micro-LED epitaxial structure, device, and fabrication method. The GaN-based micro-LED epitaxial structure includes, along the growth direction, a substrate, a buffer layer, an N-type doped GaN electron injection layer, an active region, and an Al2O3 layer. y Ga 1‑y The substrate consists of an N-type electron blocking layer and a P-type doped GaN hole injection layer; the substrate is selected from a (111) crystal plane single-crystal silicon substrate, a c-axis single-crystal sapphire substrate, a c-axis single-crystal silicon carbide substrate, or a c-axis self-supporting single-crystal gallium nitride substrate; the active region includes an InGaN-based light-emitting structure, which is at least one of an InGaN / GaN alternating multi-quantum-well structure, a GaN / InGaN / GaN single-quantum-well structure, and an InGaN quantum dot structure. This application shortens the carrier radiative recombination lifetime, weakens the quantum-confined Stark effect, and improves the radiative recombination rate by employing a thin quantum well or quantum dot active region structure, thereby enhancing the device's modulation bandwidth and photoelectric efficiency, meeting the performance requirements of light sources for applications such as data center optical interconnects, co-packaged optics, and high-speed visible light communication.

The application discloses a kind of high-strength plastic β titanium alloy strip and whole-process preparation method, the β titanium alloy strip is composed of the following mass percentage components: Cr 7.7%~8.3%, Mo 4.9%~5.5%, V 4.9%~5.5%, Al 2.7%~3.3%, Fe≤0.20%, C≤0.03%, N≤0.02%, H≤0.010%, O≤0.10%, and the rest is Ti;The preparation method comprises: one, forging;Two, hot rolling;Three, cold rolling;Four, heat treatment.The β titanium alloy strip and whole-process preparation method of the application are overall planning from component design to final heat treatment whole-process procedure, improve production efficiency, shorten preparation time, and the β titanium alloy strip solid solution state microstructure is equiaxed β fine grain structure, strength-plasticity matching is high, horizontal longitudinal organization performance is uniform, with excellent comprehensive mechanical properties, applicable to metal processing field.

This invention discloses a method for fabricating an LED epitaxial structure, wherein a stress relief layer is grown on an N-type semiconductor layer; the stress relief layer comprises an InGaN layer, a GaN layer, and an Al layer grown sequentially according to a first preset cycle. Y Ga1 Y N layer and B X Ga1 X N layers; growing Al Y Ga1 Y In the N-layer stage, the reaction chamber temperature is set to 700-900℃, the reaction chamber pressure to 100-500 mbar, and 25-1000 sccm of TMAl and 25-1000 sccm of TEGa are introduced into the reaction chamber to form Al. Y Ga1 Y N layers; during the growth of B X Ga1 X In the N-layer stage, the reaction chamber temperature is set to 700-950℃, the reaction chamber pressure to 100-500 mbar, and 25-1000 sccm of TEB and 25-1000 sccm of TEGa are introduced into the reaction chamber to form B. X Ga1 X N layers. This invention can improve the crystal quality of the subsequent multi-quantum-well active region, enabling the LED epitaxial structure to have better luminous efficiency and device reliability.

A semiconductor device includes a semiconductor film including a Schottky junction region and an ohmic junction region; a Schottky electrode disposed on the Schottky junction region of the semiconductor film; and an ohmic electrode disposed on the ohmic junction region, the semiconductor device characterized in that a dislocation density of the Schottky junction region of the semiconductor film is smaller than a dislocation density of the ohmic junction region of the semiconductor film.

The application belongs to the technical field of high-temperature alloy processing, and particularly relates to a nickel-based high-temperature alloy ultra-thin foil and a preparation method and application thereof. According to the application, the cold rolling deformation of each pass is limited to 10% to 30%, a 1050 DEG C to 1100 DEG C stress relief annealing cycle rolling mechanism is matched when the cumulative deformation reaches 65% to 70%, and a 1170 DEG C to 1230 DEG C solid solution treatment process is coupled to the 0.02 mm to 0.03 mm ultra-thin intermediate blank, so that the problems of strip breakage, poor plate shape precision, low thickness uniformity, large internal stress, insufficient room temperature and high-temperature tensile strength in the prior art can be solved, and thus the nickel-based ultra-thin foil with high mechanical properties can be stably prepared.

The application relates to the field of semiconductor photoelectric devices, and particularly discloses a hydrolysis-resistant blue-green LED epitaxial wafer, a preparation method thereof and an LED. The hydrolysis-resistant blue-green LED epitaxial wafer comprises a substrate and a buffer layer, a composite layer, an N-GaN layer, a multi-quantum well layer, an electron blocking layer and a P-GaN layer arranged on the substrate in sequence; the composite layer comprises a first three-dimensional GaN layer, a second three-dimensional GaN layer, an InGaN layer, a superlattice layer, a third three-dimensional GaN layer and a two-dimensional GaN layer which are stacked on the buffer layer in sequence; and the superlattice layer comprises AlN layers and GaN layers which are alternately stacked. By implementing the application, the hydrolysis resistance of the blue-green LED can be improved.

The application discloses a kind of tellurium zinc cadmium polycrystal synthesis device and method thereof, specifically related to crystal preparation technical field, including installation base, the four corners of the upper surface of the installation base are all fixedly connected with support column, and the bottom of four support columns is fixedly connected with the four corners of the lower surface of installation top plate respectively, the inner wall of installation top plate is fixedly connected with the outer surface of fixed frame.The application is provided with heat preservation water tank, heating furnace, annular flow guide pipe and vacuum cover, the liquid in the heat preservation water tank is injected into the annular flow guide pipe by the water pump arranged in the heat preservation water tank, at the same time, the heat absorbed by the liquid is used to assist the temperature rise of the vacuum cover, so that the resources required for improving the temperature inside the vacuum cover are reduced, the consumption of resources during use of the synthesis device is effectively reduced, the cost of producing tellurium zinc cadmium is reduced, and the processing quality of tellurium zinc cadmium is guaranteed by the way of auxiliary temperature rise and temperature drop.

A crystal annealing apparatus and method are disclosed. The apparatus includes an annealing mechanism comprising a heating component forming an annealing chamber; a heat-preserving mechanism installed inside the annealing chamber, also having a heat-preserving chamber; a crucible body installed within the heat-preserving chamber; and a silicon carbide powder buffer filling the inner cavity of the crucible body, with multiple crystal accommodating spaces within it. The method involves filling the inner cavity of the crucible body with a silicon carbide powder buffer, and arranging multiple crystals spaced apart within the buffer; placing the crystal annealing apparatus carrying the crucible body in a crystal growth furnace; and annealing the crystal using a temperature gradient heating and staged differential rate cooling process to reduce internal thermal stress in the crystal. Simultaneously, the thermal stability and uniform thermal conductivity of silicon carbide powder buffer the thermal stress generated by temperature changes in the crystal. This invention effectively optimizes crystal stress, improves crystal quality, and effectively solves the technical problems of crystal cracking, stress superposition, high dislocation density, and insufficient purity.

The application provides a light-emitting epitaxial structure, a light-emitting diode chip and a display device, and relates to the technical field of semiconductor light-emitting devices. The light-emitting epitaxial structure comprises a substrate, an N-type confinement layer, an active layer, a P-type confinement layer and a P-type GaP window layer which are sequentially arranged in sequence; a layer of AlGaP improvement layer is inserted in the P-type GaP window layer; or at least two layers of AlGaP improvement layer are inserted in the P-type GaP window layer, and the at least two layers of AlGaP improvement layer are arranged at intervals in the direction from the substrate to the P-type GaP window layer. The insertion of the at least one layer of AlGaP improvement layer in the P-type GaP window layer can reduce the stress of the P-type GaP window layer caused by lattice mismatch, reduce the dislocation density in the P-type GaP window layer, improve the crystal quality of the P-type GaP window layer, improve the growth quality of the light-emitting epitaxial structure, and improve the performance of the light-emitting diode chip.

The application provides a 135ksi grade hydrogen sulfide corrosion resistant drilling steel and a production method, a produced steel pipe, a steel pipe heat treatment method and application thereof. The composition is as follows: Cr: 0.90-1.20%, Ni: 0.60-0.75%, Mo: 0.80-1.00%, Al: 0.020-0.050%, V: 0.15-0.25%, C: 0.22-0.27%, Si: 0.15-0.30%, Mn: 0.60-0.75%, P≤0.010%, S≤0.0015%, and the rest is Fe and other inevitable impurities. Compared with the prior art, the application is matched with a reasonable composition system, a pure steel refining control technology and a high uniformity heat treatment process, so that the material has good strength and toughness and excellent hydrogen sulfide corrosion resistance, and the produced steel pipe can be used in a 10,000m deep well.

The invention provides an epitaxial wafer growth method, an epitaxial wafer, a semiconductor device and a preparation method thereof, and the epitaxial wafer growth method comprises the steps: providing a substrate, and growing a first epitaxial layer on one side of the substrate; a mask layer is grown on the side, away from the substrate, of the first epitaxial layer, and the mask layer comprises window areas and mask areas which are distributed alternately; growing a second epitaxial layer at the mask layer window on one side, far away from the first epitaxial layer, of the mask layer; wherein the chamfer angle of the area corresponding to the mask area in the second epitaxial layer is different from the chamfer angle of the area corresponding to the window area in the second epitaxial layer. The method is used for solving the problem that the performance of a semiconductor device prepared by an epitaxial wafer subsequently is influenced because the control of the epitaxial wafer prepared by a conventional growth method in the prior art on the dislocation density is limited by a single chamfer angle.

The invention relates to the technical field of crystal growth, in particular to a crystal growth method adopting a high-pressure inert atmosphere edge-defined film-fed crystal growth method, which comprises the following steps of: melting a crystal raw material and a doping agent under 6-10MPa inert gas, growing a crystal by a Czochralski method, and adopting staged dynamic pressure regulation during growth, the method comprises the following steps: sequentially carrying out neck (6-8 MPa), shouldering (linearly reducing to 4-6 MPa), equal-diameter (constant 4-6 MPa) and ending (reducing to 3-4 MPa) stages, adopting a double-layer structure, adopting a high-density solid body as the inner layer, enabling the aperture to be 102-108% of the target diameter, and arranging a spiral micro-channel on the side wall; the outer layer is a porous material, the porosity is 15-25%, annealing is carried out after growth, and pressure relief is carried out in stages: when the pressure is greater than 1 MPa, the pressure is released at 0.2-0.3 MPa / min, and when the pressure is less than 1 MPa, the pressure is slowly reduced to normal pressure at 0.05-0.15 MPa / min, so that the wastage rate of volatile components can be controlled below 0.5%.

The invention belongs to the technical field of crystal material preparation, and particularly relates to a method for growing sapphire crystals by a wide seed crystal edge-defined film-fed crystal growth method, which comprises the following steps of: firstly, preparing an Al2O3-based raw material through multi-step sintering, carrying out acid etching microstructuring treatment on R / M surface seed crystals, arranging an array type feeding seam mold above a crucible during charging, and carrying out vacuum replacement for three times, so as to obtain a sapphire crystal; a gradient temperature field is established through three-area independent temperature control, seeding is performed after melt is immersed into a mold, the growth process comprises seeding, shouldering and equal-diameter growth, wide diameter expansion and equal-diameter growth of crystals are realized by accurately controlling the pulling rate, the crucible rising speed and the three-section power of a middle heating area, and the crystals are automatically separated from the mold; and high-temperature, medium-temperature and low-temperature three-stage gradient annealing is carried out under argon protection to release stress and stabilize the structure, so that the transverse temperature gradient can be accurately controlled below 5 DEG C / cm, the problem of large temperature difference between the edge and the center during wide seed crystal growth is solved, and the stability of the solid-liquid interface shape and the uniformity of crystal growth are ensured.