145results about How to "Reduce dislocation density" patented technology

The invention relates to a hot-rolled wire rod for a 1960MPa-grade bridge cable and a manufacturing method of the hot-rolled wire rod, after a C-Si-Mn-Cr hypereutectoid component is rolled and spun into a wire rod, the wire rod is subjected to online molten salt strong isothermal treatment, so that the wire rod firstly passes through front-section molten salt and is cooled at a cooling speed of more than or equal to 36 DEG C / s, and enters a sorbite phase region from an austenite state to promote transformation of part of austenite to sorbite; the method comprises the following steps: carrying out high-temperature heat treatment on a steel wire rod, then carrying out rear-section molten salt heating isothermal treatment to promote pearlite phase change and isothermal tempering, and finally carrying out roller way slow cooling to prepare a mixed structure with a microscopic structure mainly comprising tempered sorbite and tempered pearlite and the balance of ferrite and quasi-spheroidized carbide, so that a component system can be simplified, the structure of the steel wire rod is regulated to be uniform, and the service life of the steel wire rod is prolonged. The tensile strength is 1360-1410 MPa, the percentage reduction of area is 45%-50%, the requirement for the strength grade of a 1960 MPa bridge cable is met, and meanwhile the risks of wire breakage and unqualified torsion of manufactured wires are reduced.

The invention belongs to the technical field of crystal growth, and provides a low-resistivity silicon carbide single crystal growth method and system and a single crystal, silicon carbide powder is uniformly paved at the bottom of a graphite crucible, metal carbide material particles are uniformly paved on the surface of the silicon carbide powder, and silicon carbide seed crystals are adhered to the top of the graphite crucible; the graphite crucible is sealed, and the interior of the graphite crucible is vacuumized; heating the graphite crucible subjected to vacuumizing treatment, filling carrier gas into the graphite crucible, then slowly replacing the carrier gas with doped source gas, slowly increasing the growth pressure to a set pressure, and growing a buffer layer; after the growth of the buffer layer is completed, changing the growth condition to grow the heavily doped silicon carbide single crystal; and after the growth of the crystal is completed, cooling the graphite crucible subjected to vacuumizing treatment, so that the crystal is naturally cooled, and the low-resistivity silicon carbide single crystal is obtained. The doping concentration of the silicon carbide single crystal can be improved, and the resistivity of the silicon carbide material can be reduced.

The invention discloses a light-emitting diode epitaxial wafer and a preparation method thereof, and relates to the field of semiconductor photoelectric devices. The light-emitting diode epitaxial wafer sequentially comprises a substrate, a buffer layer, an N-type GaN layer, a multi-quantum well layer, an electron blocking layer and a P-type GaN layer. The buffer layer sequentially comprises a first AlN layer, a second AlN layer, a third AlN layer, a first superlattice layer, a first AlGaN layer, a second superlattice layer and a first GaN layer; the first superlattice layer comprises a fourth AlN layer and a second AlGaN layer which are alternately stacked, and the second superlattice layer comprises a third AlGaN layer and a second GaN layer which are alternately stacked; a first V-shaped pit extending to the second superlattice layer is formed in the third AlN layer, a second V-shaped pit is formed in the first superlattice layer, and the second V-shaped pit is filled and leveled up by the first AlGaN layer; the second superlattice layer forms a third V-shaped pit, and the first V-shaped pit and the third V-shaped pit are filled and leveled up by the first GaN layer. By implementing the invention, the luminous efficiency can be improved.

The invention discloses a preparation device and method for growing a large-size silicon carbide single crystal. A raw material gas phase in a high-temperature area is transmitted to the surface of a seed crystal in a low-temperature area for crystal growth by using a physical gas phase transmission method; the device comprises a furnace chamber, a movable sectional type heating system, a thermal insulation material, a graphite crucible, porous graphite, a seed crystal unit, a crystal growth induction forming device and an electric field device. The method comprises the following steps: installing a seed crystal unit in a crucible filled with silicon carbide powder, placing the crucible in a heater, and carrying out a crystal growth stage to prepare the silicon carbide single crystal. The whole growth process of the crystal is in a constant temperature state, thermal stress caused by the temperature difference between the growth end and the seed crystal end and the temperature difference between the crystal edge and the crystal center in the top end seed crystal method crystal growth process is avoided, the dislocation defect of the crystal is reduced, and finally the high-quality silicon carbide single crystal is obtained. And the production cost is reduced.

The invention discloses a 125KSi-grade high-strength corrosion-resistant seamless steel tube and a production method thereof, and belongs to the technical field of seamless steel tubes, the 125KSi-grade high-strength corrosion-resistant seamless steel tube comprises the following main chemical components in percentage by weight: 0.20-0.25% of C, 0.17-0.37% of Si, 0.30-0.40% of Mn, 2.00-4.00% of Cr, 0.20-0.30% of W, 0.10-0.20% of V, 0.010-0.030% of Nb, 50-0.70% of Mo, 0.0005-0.0015% of B, 0.020-0.040% of Al, 0.015-0.025% of Ti, 0.0010-0.0020% of Ca and 0.0003-0.0005% of Mg. The seamless steel tube is excellent in mechanical property and good in corrosion resistance, and can be The seamless steel pipe is a 125KSi-grade high-strength corrosion-resistant seamless

The invention discloses a silicon substrate gallium nitride wafer containing a large mismatch stress regulation and control structure and a preparation method and application thereof, and relates to the technical field of semiconductor materials. The silicon substrate gallium nitride wafer containing the large mismatch stress regulation and control structure is formed by stacking a silicon substrate, an aluminum nitride amorphous film barrier layer, an ultrathin porous aluminum oxide weak bonding decoupling layer, an aluminum nitride single crystal film nucleating layer template layer and a gallium nitride single crystal film quality improvement layer in sequence. According to the invention, by regulating and controlling the pore size and pore density in the ultrathin porous alumina weak bonding and decoupling layer, the weak bonding and decoupling effect of the aluminum nitride single crystal film nucleating layer template layer on the ultrathin porous alumina weak bonding and decoupling layer is regulated and controlled; and therefore, large mismatch stress regulation and control of the silicon substrate gallium nitride material are realized, and the crack-free thickness, the material crystallization quality and the material preparation efficiency are improved. The silicon substrate gallium nitride wafer containing the large mismatch stress regulation and control structure can be applied to development and production of gallium nitride-based power electronic devices, microwave radio frequency devices and optoelectronic devices.

The invention discloses a method for lateral epitaxial growth of a gallium nitride layer and a gallium nitride structure, and the method comprises the following steps: providing a substrate structure which comprises a substrate and a graphene layer which are stacked; etching the graphene layer to form a first window and a first graphene mask structure which are arranged at an interval; the bottom of the first window is in contact with the upper surface of the substrate, and an oxide mask structure is arranged at the bottom; etching the first graphene mask structure to form a second window to obtain a second graphene mask structure; the bottom of the second window is in contact with the upper surface of the substrate, and the second window is located around the second graphene mask structure; and growing a gallium nitride layer on the substrate at the boundary of the second graphene mask structure in a nucleation manner. According to the invention, GaN is subjected to nucleation growth in the nano-scale second window, dislocation of the substrate is blocked by the oxide mask structure and the second graphene mask structure, and a large amount of dislocation is prevented from extending to the gallium nitride layer, so that the dislocation density is greatly reduced.

The invention discloses a silicon substrate gallium nitride semiconductor wafer and a preparation method and application thereof, and relates to the technical field of semiconductor materials. The silicon substrate gallium nitride semiconductor wafer is composed of a silicon single crystal substrate, a silicon carbide single crystal thin film barrier layer, an ultrathin porous titanium nitride weak bonding decoupling layer, an aluminum nitride single crystal thin film nucleating layer template layer and a gallium nitride single crystal thin film quality improving layer which are stacked in sequence. According to the invention, the pore size and the pore density in the ultrathin porous titanium nitride weak bonding decoupling layer are regulated and controlled, so that the weak bonding decoupling effect of the aluminum nitride single crystal film nucleating layer template layer on the ultrathin porous titanium nitride weak bonding decoupling layer is regulated and controlled; therefore, large mismatch stress regulation and control and crack-free thickness improvement of the silicon substrate gallium nitride material are realized, and material crystallization quality and preparation efficiency are improved. The silicon substrate gallium nitride semiconductor wafer can be applied to development and production of gallium nitride-based power electronic devices, microwave radio frequency devices and optoelectronic devices.

The invention relates to a 4-inch low-dislocation indium antimonide lt; 211gt, 211gt; the invention discloses a preparation method of directional single crystals and belongs to the technical field of photoelectric materials. According to the method, a Czochralski method is adopted to grow the single crystal, a resistance furnace is arranged on the periphery of an induction coil of a heating device, and by accurately controlling heating conditions, designing a proper temperature field in a growth chamber and further combining growth conditions such as the state of a solid-liquid interface, the pulling speed, the rotating speed and particularly the shoulder expanding angle in the crystal growth process, the single crystal is obtained. The longitudinal temperature gradient in the crystal growth process is reduced, and the dislocation density of the large-size indium antimonide single crystal with the diameter of 4 inches can be obviously reduced, so that indium antimonide is enabled to be lt; 211gt, 211gt; the dislocation density of the directional single crystal is less than 100 / cm < 2 >.

The invention discloses a method for realizing low-temperature strengthening and toughening of TRIP high-entropy alloy, which comprises the following steps: S1, low-temperature pre-stretching: carrying out low-temperature pre-stretching on the TRIP high-entropy alloy until the TRIP high-entropy alloy is stretched to a Luders strip deformation end point or a stretching stress-strain curve stress platform end point, and then unloading; and S2, heat treatment is conducted, specifically, heat preservation treatment of the TRIP high-entropy alloy is conducted between the room temperature and the melting point temperature, and then rapid cooling is conducted through a cooling medium. According to the method for achieving low-temperature strengthening and toughening of the TRIP high-entropy alloy, low-temperature pre-stretching and heat treatment are adopted, the high-entropy alloy with two phase structures and two grain size characteristics is prepared, the low-temperature yield strength can be remarkably improved through a fine grain structure, residual dislocation and back stress caused by deformation of the two grain sizes, and the low-temperature strengthening and toughening of the TRIP high-entropy alloy can be achieved. And the deformation coordination between different grain sizes and phase structures can also ensure that the low-temperature plasticity is not reduced, so that the TRIP high-entropy alloy has high strength and high plasticity in a low-temperature environment, and the TRIP high-entropy alloy shows excellent low-temperature mechanical properties.

The present invention provides a preparation method of a 7 series aluminum alloy plate, which relates to the technical field of aluminum alloys, and comprises the following steps: step 1) homogenizing heat treatment of the 7 series aluminum alloy ingot, preheating after cooling, and then performing multiple rolling processes to obtain a rolled plate; wherein the preheating temperature is higher than the recrystallization temperature of the 7 series aluminum alloy ingot and lower than the solution temperature of the 7 series aluminum alloy ingot; the pressing amount of each rolling process is 30%-40%; step 2) solution treatment of the rolled plate, and then double-stage aging treatment to obtain a 7 series aluminum alloy plate. By adopting a large reduction rolling process in the temperature range above recrystallization, the plane rheology of the rolling process is induced to change to a three-dimensional shear rheology, the plane rheology ratio along the rolling direction is reduced, the transverse plasticity of the plate is improved, and the anisotropy of the plate is improved.

The invention belongs to the technical field of nitride material preparation, and provides a substrate pretreatment and single crystal film preparation method for growing aluminum nitride. According to the method, nitrogen is used as a nitrogen source, aluminum particles are used as an aluminum source, and a metal nitridation vapor phase epitaxy (MNVPE) device is used on a sapphire substrate. Wherein a sunken structure is formed on the sapphire substrate through a pretreatment method, and then the growth of the aluminum nitride single crystal film is carried out in three steps. According to the pretreatment and preparation method for the aluminum nitride single crystal film, on one hand, steam generated by heating aluminum has an etching effect on sapphire, nucleation and crystal column closure of aluminum nitride are facilitated, and on the other hand, annihilation of dislocation and stress release can be promoted through three-step growth, so that the yield of the aluminum nitride single crystal film is improved. Therefore, the crystal quality of the aluminum nitride film prepared by the metal nitriding vapor phase epitaxy method is improved.

The invention relates to the technical field of LED epitaxial wafers, and discloses a GaN-based LED epitaxial wafer and a preparation method thereof, and the GaN-based LED epitaxial wafer comprises a substrate, a buffer layer, an N-type semiconductor layer, a stress release layer, a multi-quantum well light-emitting layer, an electron blocking layer, and a P-type semiconductor layer. Wherein the N-type semiconductor layer sequentially comprises a first porous low-temperature GaN layer, a second porous AlGaN / GaN superlattice layer, a third high-temperature GaN layer, a fourth porous AlGaN / GaN superlattice layer and a fifth high-temperature GaN layer. By adopting the invention, the generation of defects in the growth process of the epitaxial material can be reduced, the dislocation density of the material is reduced, and the quality of the epitaxial wafer material is remarkably improved, so that the radiation recombination efficiency in the active region of the light-emitting diode is improved, and meanwhile, the proportion of the photon escape body material in the active region can be remarkably improved.

The invention relates to the technical field of semiconductor light emitting diodes, and discloses a composite patterned substrate and a preparation method thereof. The preparation method comprises the following steps: preparing a SiO2 film layer on a substrate; coining glue is prepared on the SiO2 film layer; transferring the pattern of the soft template to the SiO2 film layer by using a nanoimprint technology; performing etching treatment on the SiO2 film layer to form a graphic structure with a preset morphology, and etching to remove part of the substrate material to form a pit to obtain a patterned substrate; preparing an AlN layer on the substrate, filling the pit with the AlN layer, and covering the surface of the graphic structure; carrying out photoetching treatment and etching treatment on the AlN layer, so that the AlN layer is filled in the pit and covers the side surface of a part of the pattern structure; and carrying out annealing treatment, and removing the residual photoresist to obtain the composite patterned substrate. By implementing the preparation method provided by the invention, the obtained composite patterned substrate can improve the crystal quality of the epitaxial layer, thereby improving the internal quantum efficiency and final brightness of the chip.

The invention relates to an LED epitaxial wafer, a growth method of a graphene layer and an LED chip, and belongs to the technical field of LEDs. The LED epitaxial wafer comprises a substrate, and a graphene layer, a buffer layer, an undoped GaN layer, an n-type GaN layer, a stress release layer, a multi-quantum well layer, an electron barrier layer and a p-type GaN layer which are sequentially epitaxially grown on the substrate, wherein the thickness of the single graphene layer is 0.5-1.5 nm, and the number of the graphene layers is at least two. According to the LED epitaxial wafer provided by the invention, the defect density in the GaN template layer is reduced through deposition of the graphene interlayer. Therefore, the recombination efficiency of electrons and holes is improved, so that the luminous efficiency of the LED is enhanced. Due to the existence of the graphene layer, the compressive strain of the chip is reduced, the influence of a polarization field is reduced, and the emission wavelength of electroluminescence (EL) is more stable.

The utility model discloses a seed crystal assembly, which relates to the field of casting monocrystalline silicon ingots, is suitable for casting monocrystalline silicon ingots, and comprises a seed crystal layer, a seed crystal layer and a crystal layer, the seed crystal layer comprises a plurality of seed crystals which are laid at the bottom of the crucible; a splicing seam is formed between every two adjacent seed crystals; a cushion block layer; the cushion block layer comprises a plurality of cushion blocks, and the plurality of cushion blocks are distributed on the seed crystal layer at intervals and cannot cover any splicing seam; a cover layer; the covering layer comprises a single or a plurality of silicon blocks; and the covering layer is arranged on the cushion block layer and partially or completely covers the seed crystal layer. According to the utility model, the three layers of seed crystal components are adopted, so that gaps exist in splicing seams; and the pressure of the splicing seam is reduced, so that the generation of a dislocation source is reduced, the dislocation density in the silicon ingot is reduced, and the weight of the monocrystalline silicon ingot is improved.

The invention provides a method for heteroepitaxial growth of a gallium arsenide material on silicon by introducing laser surface treatment. The method comprises the following steps: growing a gallium arsenide low-temperature layer with a low crystallization degree on a silicon substrate, and crystallizing the surface layer of the gallium arsenide low-temperature layer by adopting a laser surface treatment mode; growing a gallium arsenide medium-temperature layer on the gallium arsenide low-temperature layer after the surface layer crystallization treatment, and purifying the surface layer crystalline state of the gallium arsenide medium-temperature layer by adopting a laser surface layer treatment mode; and growing a gallium arsenide high-temperature layer on the gallium arsenide medium-temperature layer after the surface layer crystalline state purification treatment. Under the condition that the crystallization degree of the whole gallium arsenide epitaxial layer is reserved, the crystallization degree of the local part, namely the upper surface of the epitaxial layer, is improved, the inhibition effect on dislocation is enhanced, and the optimization of the crystal quality of the whole epitaxial structure is realized. The dislocation penetrating to the surface of the whole epitaxial structure during heteroepitaxial growth of the gallium arsenide material on the silicon substrate is remarkably reduced, and a brand new way is opened up for preparing semiconductor photoelectric devices.

This invention discloses an epitaxial wafer for a deep ultraviolet (UV) light-emitting diode (LED) and its fabrication method, relating to the field of semiconductor optoelectronic devices. The UV LED epitaxial wafer includes a substrate and a buffer layer, an N-type AlGaN layer, an active layer, an electron blocking layer, and a P-type AlGaN layer sequentially grown on the substrate. The active layer has a periodic structure, with each period comprising a sequentially stacked quantum well layer and a quantum barrier layer, and the number of periods in the active layer is ≥2. The quantum barrier layer comprises a sequentially stacked AlInGaN layer and a P-AlInGaN layer. Implementing this invention can effectively improve the luminous efficiency of deep ultraviolet LEDs.

The utility model discloses a light emitting diode epitaxial wafer and a light emitting diode. The light emitting diode epitaxial wafer comprises a substrate, and a buffer layer, a U-GaN layer, an N-GaN layer, an insertion layer, a stress release layer, a multi-quantum well layer, an electron blocking layer and a P-GaN layer which are stacked on the substrate in sequence. Wherein the insertion layer at least comprises a Si3N4 layer. The light-emitting efficiency of the light-emitting diode provided by the utility model is obviously improved.

The invention discloses a yellowing-resistant flame-retardant plastic and a preparation method thereof, and relates to the technical field of polypropylene particle preparation. Potassium ethylene trifluoroborate and allyl hydrazine hydrochloride participate in propylene polymerization to prepare modified polypropylene, fluorine and boron elements are introduced, growth and reproduction of bacteria are inhibited, the antibacterial effect is achieved, meanwhile, potassium ions adsorb moisture in air, the antistatic effect is achieved, chloride ions are assisted, and the antibacterial performance is enhanced; then, the modified polypropylene particles are bombarded through silicon, tungsten and yttrium mixed plasma current, an amorphous silicon film is formed on the surface through in-situ growth, and the surface hardness and the overall mechanical strength of polypropylene are remarkably improved; by doping the tungsten element, the friction coefficient is reduced, the wear is reduced, the wear resistance and the mechanical property of the plastic are improved, the yttrium element is matched, grains are refined, the mechanical strength and the flexibility of the material are improved, and on the basis, the tungsten element and the yttrium element form a conductive network on the surface, so that generated electrostatic charges are quickly leaked, and the antistatic effect is achieved.

The utility model relates to the technical field of gallium oxide crystal growth, and discloses a crucible structure for growing a gallium oxide single crystal by a VB method, which comprises a crucible shell, a seed crystal cavity, a diameter-expanding cavity, a diameter-reducing cavity, a shoulder-expanding cavity and an equal-diameter cavity, the seed crystal cavity, the diameter-expanding cavity, the diameter-reducing cavity, the shoulder-expanding cavity and the equal-diameter cavity are arranged in the crucible shell, the seed crystal cavity is arranged at one end of the crucible shell, and the diameter-reducing cavity is arranged at the other end of the crucible shell. One end of the seed crystal cavity is closed, the other end of the seed crystal cavity is connected with the diameter-expanding cavity, the diameter-expanding cavity is connected with the diameter-reducing cavity, the diameter-reducing cavity is connected with the shoulder-expanding cavity, the shoulder-expanding cavity is connected with the equal-diameter cavity, and the other end of the equal-diameter cavity is open. Through reasonable design of a gallium oxide growth technology, the crucible shell, the seed crystal cavity, the diameter-expanding cavity, the diameter-reducing cavity, the shoulder-expanding cavity and the equal-diameter cavity are adopted, so that gallium oxide crystals can be separated from the crucible wall during growth and cooling, dislocation proliferation and twin crystal structures are not easy to appear, the crystal dislocation density is reduced, and the performance of a semiconductor chip is improved. The crucible structure can be used for preparing cylindrical gallium oxide single crystals with low dislocation density.

This invention provides a light-emitting diode epitaxial wafer and its fabrication method. The light-emitting diode epitaxial wafer includes a substrate, and a buffer layer, an undoped GaN layer, an N-type GaN layer, a multiple quantum well layer, an electron blocking layer, and a P-type GaN layer sequentially deposited on the substrate. The buffer layer includes a nitrided graphene buffer layer, an h-BN buffer layer, and a B-type GaN layer sequentially deposited on the substrate. x Al 1‑x N buffer layer, AlN buffer layer, wherein, the B x Al 1‑x The boron content in the N-buffer layer gradually decreases along the growth direction of the epitaxial layer. This invention achieves this by sequentially arranging a graphene nitride buffer layer, an h-BN buffer layer, and a boron buffer layer between the substrate and the epitaxial structure. x Al 1‑x N-buffer layers and AlN-buffer layers reduce lattice mismatch between structures, lower defect density, and improve the overall quality of LED epitaxial wafers.

This invention discloses a germanium photodetector and semiconductor device. The germanium photodetector includes: a silicon substrate; a first germanium thin film layer deposited on the silicon substrate; the first germanium thin film layer having multiple penetrating dislocations extending through its thickness; multiple pits corresponding one-to-one with the multiple penetrating dislocations formed on the surface of the first germanium thin film layer, and the inner surface of each pit being covered with an amorphous material layer; and a second germanium thin film layer deposited on the surface of the first germanium thin film layer and on the amorphous material layer within each pit, filling each pit. The amorphous material layer effectively blocks the extension of dislocations, reduces dislocation density, and ensures the photoelectric conversion efficiency of the device. Furthermore, by integrating the epitaxial chamber, deposition chamber, and pre-cleaning chamber into the same semiconductor device through a transfer chamber to produce the germanium photodetector, the contact path of external contaminants is reduced, the process flow is simplified, production efficiency is improved, and space and cost are optimized.

The invention provides a preparation method of a composite patterned substrate, the composite patterned substrate and an LED chip, and the method comprises the steps: forming a plurality of holes in the surface of a sapphire substrate, and carrying out the gluing, exposure and development processing, and obtaining a preset pattern; depositing a SiOF layer on the substrate; removing the preset pattern below the SiOF layer through heat treatment to form a cavity; transferring a pattern on the substrate through a nanoimprint technology; and performing inductively coupled plasma etching to form a composite pattern structure. A cavity structure is formed in a sapphire substrate through laser drilling and heat treatment, the light extraction efficiency of an LED is improved by combining with a composite pattern constructed by a nanoimprint technology and utilizing a multi-interface light scattering effect, the propagation direction of light rays can be guided by combining a patterned structure with a cavity, light emitting angle distribution is optimized, and light emitting is more uniform or the directivity is more concentrated; epitaxial growth stress is released through the cavity, dislocation density is reduced, epitaxial layer cracks are effectively inhibited, and crystal integrity is improved.

The present invention relates to a gallium oxide film and a preparation method thereof and an ultraviolet detection device. The preparation method comprises: growing a gallium oxide buffer layer on a substrate; forming a gallium vacancy gallium oxide layer on a surface of the gallium oxide buffer layer away from the substrate; growing a gallium oxide layer on a surface of the gallium vacancy gallium oxide layer away from the substrate; obtaining the gallium oxide film; and in the process of forming the gallium vacancy gallium oxide layer, intermittently introducing an oxygen source and performing an annealing treatment. The preparation method of the present invention obtains a gallium vacancy gallium oxide layer rich in gallium vacancies by intermittently introducing an oxygen source, thereby reducing the dislocation density of the gallium oxide film. When applied to an ultraviolet detection device, the performance and reliability of the device are improved.

The invention provides a crucible for growing indium phosphide crystals, which comprises a carrier crucible and a diamond coating layer / coating body, the diamond coating layer / coating body is arranged on the inner surface of the carrier crucible, the material of the carrier crucible is any one of graphite, quartz, silicon carbide or boron nitride, and the diamond coating layer / coating body is arranged on the inner surface of the carrier crucible. The thickness d of the diamond coating layer or the diamond coating layer arranged on the surface of the diamond coating body is not less than 0.5 [mu] m and not more than 100 [mu] m, placing an indium phosphide polycrystal material in the crucible, then placing the crucible in a high-pressure reaction kettle, setting process parameters, and carrying out single crystal growth, the problems that in the prior art, indium phosphide crystals obtained through growth are large in internal stress and many in dislocation, and crystal lattices are prone to distortion are solved.

The invention discloses a low-dislocation and low-stress P-type silicon carbide crystal and a silicon carbide substrate, and belongs to the technical field of silicon carbide material preparation. A plurality of silicon carbide substrates are prepared in areas, which are more than 1mm away from a seed crystal face, of the P-type silicon carbide crystal, the number of BPD in any square area with the size of 1cm * 1cm in the 2 / 3 radius range on any silicon carbide substrate is not more than 500 / cm < 2 >, and the average value of BPD density in the 2 / 3 radius range is not more than 100 / cm < 2 >. The overall dislocation of the P-type silicon carbide crystal is lower than that of the existing P-type silicon carbide crystal, and the quality of the silicon carbide substrate prepared close to the surface of the silicon carbide crystal is the same as that of the silicon carbide substrate prepared by other silicon carbide crystals at the height, so that the silicon carbide crystal has no residual liquid drop influence and is good in overall axial uniformity.

The invention provides an epitaxial layer structure of a doped InSb film and a preparation process thereof, based on an MOCVD (Metal Organic Chemical Vapor Deposition) process, an InSb: Te layer and an InSb layer are periodically and alternately grown to form a doped InSb functional layer of a Hall element, the band gap of an InSb material can be increased, and the temperature coefficient of the Hall element of the InSb film is reduced; furthermore, according to the epitaxial layer structure and the preparation process provided by the invention, uniform doping can be realized, excessive Te doping can be avoided, and the defect density and the surface state density of the doped InSb functional layer can be reduced, so that the sensitivity of the InSb Hall element is improved, and the background noise of the Hall element is reduced. Besides, according to the epitaxial layer structure of the doped InSb film and the preparation process thereof provided by the invention, the growth processes, materials, thicknesses and the like of the buffer layer and the gradient layer are further improved, lattice mismatch between the substrate and the InSb film is slowed down, the dislocation density of the InSb film caused by mismatch is reduced, the InSb film with higher mobility can be grown, and the yield of the InSb film is improved. And therefore, higher sensitivity can be obtained on the Hall element.

This invention discloses a rapid annealing apparatus and method for micro / nano-scale metal samples. A metal indenter and a micro / nano-scale metal sample are prepared separately. The micro / nano-scale metal sample is placed at the fixed end of an electromechanical sample rod, while the metal indenter is mounted on the movable end, with the two ends facing each other without contact. Under a transmission electron microscope, the metal indenter is aligned and brought closer to the sample by a piezoelectric ceramic drive. After the indenter and the micro / nano-scale metal sample reach critical contact, several pulsed currents are applied. Then, by controlling the displacement of the piezoelectric ceramic, the cyclic movement of the metal indenter is achieved, thereby applying a constant strain amplitude of pressure-pressure cyclic loading to the micro / nano-scale metal sample. Then, pulsed currents are applied again, and this process is repeated multiple times, thus achieving rapid annealing of the micro / nano-scale metal sample using electromechanical coupling. The micro / nano-scale metal sample annealing method of this invention allows for in-situ observation at the micro / nano scale, with controllable parameters, high success rate, high efficiency, and good stability.

The application provides a GaN-based light-emitting diode epitaxial structure and a preparation method thereof, wherein a Zn source is introduced as a surface activator during the growth of a P-type AlGaN electron blocking layer, a P-type AlGaN electron blocking layer structure with a gradient distribution of Zn concentration along the direction of the P-type AlGaN electron blocking layer is constructed, and specifically, through the core role of the Zn surface activator and the innovative design of the gradient distribution of the Zn concentration, the valence band Ev is smoothly and non-peaked along the whole process, and the hole injection is smooth along the whole process under the premise of ensuring that the conduction band Ec is smoothly and non-peaked and the strong electron blocking capability is not lost.