488 results about "Conduction type" patented technology

The embodiment of the invention provides a solar cell and a preparation method thereof, and a photovoltaic module. In the embodiment of the invention, a first internal expansion layer with the same conduction type as a first doping layer and / or a second internal expansion layer with the same conduction type as a second doping layer are / is arranged in an interval region used for forming an isolation region on the back surface of a silicon substrate; and the first internal expansion layer and the second internal expansion layer are electrically connected, so that the field passivation effect can be realized, the recombination of minority carriers in the isolation region can be effectively reduced, reverse conduction can be realized when the battery piece is shielded, the breakdown can be avoided, and the hot spot prevention effect can be effectively realized.

The invention discloses a response time conduction type testing device and method for a radio frequency channel protection device. The response time conduction type testing device comprises a transient field intensity generating device, an isolator, a directional coupler, a first attenuator, a second attenuator, a third attenuator, a first power meter, a second power meter, a high-speed oscilloscope, a vector network analyzer and a radio frequency channel protection device to be tested. According to the method, the response performance of the protection device under the influence of the transient strong field can be comprehensively, safely and accurately evaluated, the amplitude limiting function of the protection device can still be effectively exerted under the action of the transient strong field with an extremely narrow rising edge, and then subsequent devices, circuits and equipment are prevented from being damaged.

The invention relates to the technical field of semiconductors, in particular to a semiconductor structure and a preparation method thereof. The preparation method comprises the steps that a substrate is provided, the substrate comprises an SGT device region and a BCD device region which are transversely arranged, and the conduction types of the SGT device region and the BCD device region are different; forming a plurality of deep grooves in the SGT device region and the BCD device region; gate material filling is carried out on the multiple deep grooves, a first voltage-withstanding gate structure and at least one gate filling structure of the SGT device area and a second voltage-withstanding gate structure of the BCD device area are formed, and the first voltage-withstanding gate structure is close to the BCD device area; forming a shield gate structure based on the at least one gate filling structure; and forming a plurality of shallow trench isolation structures arranged at intervals in the BCD device region, wherein the shallow trench isolation structures are located between the first voltage-withstanding gate structure and the second voltage-withstanding gate structure. According to the invention, the process cost of SGT and BCD device integration can be reduced, and the device connection is simplified.

The invention provides a back contact battery, which comprises a semiconductor substrate, a first doping layer and a second doping layer, the main body part of the first doping layer and the main body part of the second doping layer are alternately distributed on one side of the backlight surface of the semiconductor substrate, and the conduction types of the first doping layer and the second doping layer are opposite; wherein a conductive connection structure is arranged between a part of the first doped layer and a part of the second doped layer, and wherein a single conductive connection structure comprises at least two side butt joint surfaces. The invention also provides a photovoltaic module. According to the back contact battery, the electric leakage channel contact area of the single conductive connection structure can be increased, and the effect of improving the hot spot effect is better.

According to the back contact battery and the preparation method thereof provided by the invention, doping elements penetrate through the third doping region between the first doping region and the second doping region through high-temperature diffusion to form an electric leakage channel, so that a new back surface structure of the back contact battery is provided. The third doped region is formed by mixing the doping elements of the first doped region and the doping elements of the second doped region, doping of the two impurities is completed at a high temperature in one step, so that an electric leakage channel of an overlapping region is not generated, and the overlapping region of the two doped semiconductor layers with opposite conduction types in the thickness direction of the semiconductor substrate is removed, so that the conductivity of the semiconductor substrate is improved. Therefore, electric leakage loss of the back contact battery in a forward voltage area can be controlled, current in the electric leakage channel is introduced to the grid line of the first electrode or the second electrode through the electric leakage channel or the connecting electrode, the hot spot risk of the back contact battery is reduced, the safety performance of the back contact battery is effectively improved, and the service life of the back contact battery is prolonged. And the back contact battery has relatively high working performance.

The invention provides a metal oxide semiconductor electrostatic protection device. The metal oxide semiconductor electrostatic protection device comprises a substrate; a well region of a first conductivity type disposed in the substrate; the source electrode region is formed in the well region of the first conduction type, the source electrode region comprises a first heavily doped region, and the first heavily doped region is of a second conduction type; a drain region; a gate structure; the body contact region comprises a third heavily doped region, and the third heavily doped region is of the first conduction type; wherein the drain region comprises a plurality of second heavily doped regions, the plurality of second heavily doped regions are of a second conduction type, and the plurality of second heavily doped regions are arranged at positions adjacent to the gate structure; the fourth heavily doped region is of the second conduction type, and the fourth heavily doped region is not arranged close to the gate structure; and a lightly doped drain region of the second conductivity type disposed below the plurality of second heavily doped regions and the fourth heavily doped regions. By changing the structure of the drain electrode heavily doped region, the ESD current distribution is improved, and the ESD endurance capability of the device is improved.

The invention relates to a back contact battery and a photovoltaic module. Comprising a substrate, the substrate is provided with a first surface and a second surface which are oppositely arranged, the first surface comprises a first area and a second area, the first area comprises an overlapping area, and the overlapping area is adjacent to the second area; the first doped semiconductor layer is arranged in the first region; the second doped semiconductor layer is arranged in the second region and the overlapping region, and the conduction type of the second doped semiconductor layer is opposite to that of the first doped semiconductor layer; the conductive layer is arranged on one side, deviating from the substrate, of the first doped semiconductor layer and the second doped semiconductor layer; the conductive layer is provided with a first isolation groove, the first isolation groove is arranged in the first region and comprises a first groove part and a second groove part along the arrangement direction of the first region and the second region, the first groove part penetrates to the surface of the side, away from the substrate, of the first doped semiconductor layer, and the second groove part is located in the overlapping region; and the second groove part penetrates to the surface of one side, deviating from the first doped semiconductor layer, of the second doped semiconductor layer.

The invention discloses a back contact battery and a photovoltaic module, and relates to the technical field of photovoltaics. The back contact cell comprises a silicon substrate which comprises a first surface and a second surface which are oppositely arranged, and a side surface which connects the first surface and the second surface; the first interface passivation layer, the first doped silicon layer, the intrinsic silicon layer, the second doped silicon layer and the transparent conducting layer are sequentially arranged on the side face in the direction away from the side face. On the side surface of the silicon substrate, the first doped silicon layer is in direct contact with the intrinsic silicon layer; wherein the conduction types of the first doped silicon layer and the second doped silicon layer are opposite. On the side face of the silicon substrate, the first doped silicon layer can be electrically connected with the second doped silicon layer with the conduction type opposite to that of the first doped silicon layer through the intrinsic silicon layer, so that a diode structure with low reverse breakdown voltage is formed on the side face of the silicon substrate, and the hot spot risk of the back contact battery is reduced.

A power semiconductor device includes a semiconductor layer structure including a drift region of a first conductivity type and a gate trench extending into the drift region. The gate trench includes sidewalls and a bottom surface between the sidewalls. And a bottom shielding structure of a second conduction type is arranged below the bottom surface of the gate trench. First and second support shielding structures of a second conductivity type extend into the drift region on opposite sides of the gate trench and are spaced apart from sidewalls of the gate trench. A material composition of the bottom shielding structure, a distance extending into the drift region relative to a surface of the semiconductor layer structure, and / or a dopant concentration may be different from those of the first and second support shielding structures. Related devices and methods of manufacture are also discussed.

The invention relates to the technical field of photovoltaic cells, and discloses a back contact solar cell and a preparation method thereof. The preparation method comprises the following steps: providing a substrate layer of a first conductive type having a first surface and a second surface opposite to each other; a first groove is formed in the first surface, and a bulge is formed beside the first groove; performing doping treatment on the inner wall surface of the first groove to form a first doping layer; the first doped layer is of a second conductive type; forming a passivation layer on the surface of the first doping layer; a second groove isolated from the first groove is formed in the protrusion; forming a first tunneling oxide layer on the second groove; forming a second doping layer of the first conduction type in the second groove and on the first tunneling oxide layer; a first electrode and a second electrode are formed, the first electrode penetrates through the passivation layer to be connected with the first doping layer, and the second electrode is connected with the second doping layer. The first groove and the second groove which are relatively isolated are formed by grooving at different positions of the substrate layer, so that efficient current collection is facilitated, short circuit is prevented, and the photoelectric conversion efficiency and the power generation efficiency are improved.

The embodiment of the invention provides a back contact cell and a preparation method thereof, and a photovoltaic module, and relates to the field of solar cells, the back contact cell comprises a silicon substrate, the back surface of the silicon substrate comprises a first region, a second region and a spacer region, the first region comprises a first sub-region and a second sub-region, and the spacer region comprises a second sub-region and a third sub-region; the spacer region comprises a first spacer sub-region adjacent to the first region and a second spacer sub-region adjacent to the second region; the first carrier collection layer has a first conduction type, is arranged on the back surface of the silicon substrate and is positioned in the first region and the first spacer region; the amorphous semiconductor layer is arranged on the first carrier collection layer and is positioned in the second sub-region and the first spacer sub-region; the second carrier collection layer has an opposite second conduction type, is arranged on the back surface of the silicon substrate, is positioned in the second region, the spacer region and the second sub-region, and is positioned on the amorphous semiconductor layer in the second sub-region and the first spacer region; and the first electrode is arranged in the first sub-region and is positioned on one side, far away from the silicon substrate, of the first carrier collection layer. The back contact battery has excellent electrical properties.

The invention discloses a super-junction MOSFET device and a preparation method thereof, and belongs to the technical field of semiconductors, and the super-junction MOSFET device comprises a first conduction type substrate and a first conduction type epitaxial layer located on the first conduction type substrate; a cellular region and a terminal region of the device are arranged in the first conductive type epitaxial layer; a plurality of second conductive type columns are longitudinally distributed in a cellular region and a terminal region in the first conductive type epitaxial layer; wherein the plurality of second conductive type columns distributed in the terminal area comprise a plurality of size types, and the second conductive type columns of different size types are alternately arranged. The structural design relieves the strength of a terminal electric field of the device in a reverse withstand voltage state, so that the electric field strength of a terminal region is lower than that of a cellular region, breakdown occurs in the cellular region, the situation that holes are injected into a silicon and silicon dioxide interface, and consequently charges on an oxide layer interface are increased is avoided, the reliability of the device is improved, and the performance of the device is improved. And meanwhile, the avalanche breakdown capability of the device is improved.

The embodiment of the invention provides a semiconductor structure, a manufacturing method thereof and a memory device. The semiconductor structure comprises a substrate; the well region is located in the substrate; the threshold voltage doped region is positioned above the well region; the lightly doped regions are located on the two sides of the threshold voltage doped region; the source electrode region and the drain electrode region are located on the two sides of the lightly doped region respectively; the halo ring region is located between the source region and the threshold voltage doped region and between the drain region and the threshold voltage doped region; the gate structure is located on the surface of the threshold voltage doped region; wherein the conduction type of the threshold voltage doped region is different from that of the well region, the doping concentration of the lightly doped region is 8 * 10 < 19 >-9 * 10 < 19 > / cm < 3 >, and the doping concentration of the halo region is 5 * 10 < 18 >-6 * 10 < 18 > / cm < 3 >.

The invention discloses a deep trench isolation structure and a manufacturing process method thereof, an injection layer of a second conduction type is arranged on a substrate of a first conduction type, and a deep trap of the second conduction type is arranged on the injection layer; the surface layer of the deep well is provided with a shallow trench isolation structure, and the outer side of the shallow trench isolation structure is provided with a well region of a second conductive type; a deep trench is formed in the shallow trench isolation structure through etching; filling materials which are filled in sections are arranged in the deep grooves; wherein the lower part in the deep trench is filled with a silicon oxide material, and the upper part in the deep trench is filled with a polycrystalline silicon material; filling in the deep trench is divided into two sections of composite filling made of different materials, the portion located on the lower portion of the deep trench is made of silicon oxide, the portion located on the upper middle portion of the deep trench is made of polycrystalline silicon, the structure is further optimized, the bottom of DTI polycrystalline silicon is shortened to the position below an injection layer, the bottom of the DTI polycrystalline silicon can pull up a high peak electric field in a depletion region, and therefore the reliability of the deep trench is improved. And the breakdown voltage of the device is improved.

The invention relates to a solar cell, a preparation method thereof and a photovoltaic module. The solar cell comprises a semiconductor substrate which is provided with a first surface and a second surface which are opposite to each other, the first surface is provided with a first doped region and a second doped region which are arranged in a staggered mode, the second doped region comprises a contact region and isolation regions located on the two sides of the contact region, and the isolation regions are connected with the first doped region; the first doped layer is positioned in the first doped region; the first isolation layer is located in the isolation region; the second doping layer at least covers the contact region and one side, deviating from the semiconductor substrate, of the first isolation layer; the conduction type of the second doping layer is opposite to that of the first doping layer; and a first electrode and a second electrode, the first electrode being in electrical contact with the first doped layer, and the second electrode being in electrical contact with the second doped layer located in the contact region. The isolation effect can be improved.

The invention provides a solar cell and a preparation method thereof. The preparation method of the solar cell comprises the following steps: providing a silicon substrate with first doping atoms of a first conductive type; a first tunneling oxide layer and an intrinsic polycrystalline silicon layer are formed on the back face of a silicon substrate, second doping atoms with the conduction type opposite to that of the first doping atoms are diffused into the silicon substrate at a first temperature, and a first doping layer of a second conduction type is formed on the side, close to the back face, of the silicon substrate, converting the intrinsic polycrystalline silicon layer into a first doped polycrystalline silicon layer of a second conductive type; removing the first doped polycrystalline silicon layer; and growing an intrinsic amorphous silicon layer on one side, opposite to the silicon substrate, of the first tunneling oxide layer, and diffusing second doping atoms into the silicon substrate at a second temperature, the first temperature being higher than the second temperature. According to the preparation method of the solar cell, the passivation performance and the contact performance of the solar cell can be considered at the same time, and the cell conversion efficiency is improved.

The invention relates to the technical field of semiconductors, in particular to a SiC power device heat dissipation type ceramic packaging structure which comprises a substrate, a silicon carbide device and a ceramic package, a plurality of heat conduction plates are fixedly arranged on the left inner wall and the right inner wall of the ceramic package, and wavy heat conduction pieces are fixedly arranged on the end faces, away from the ceramic package, of the heat conduction plates. The lower surface of the convex surface part of the wavy heat-conducting fin abuts against the upper surface of the silicon carbide device, the lower surface of the concave surface part of the wavy heat-conducting fin is fixedly provided with a plurality of I-shaped heat-conducting fins which are arranged in parallel at equal intervals left and right, the bottom ends of the I-shaped heat-conducting fins are fixedly provided with S-shaped heat-conducting fins, and the bottom ends of the S-shaped heat-conducting fins are fixedly provided with L-shaped heat-conducting fins. The silicon carbide device can be clamped together with the substrate through the heat conduction type elastic sheet structure composed of the heat conduction plate, the wave-shaped heat conduction sheet, the I-shaped heat conduction sheet, the S-shaped heat conduction sheet and the L-shaped heat conduction sheet, and the heat conduction type elastic sheet is connected with the ceramic package to construct an efficient heat conduction heat dissipation channel.

The invention provides a manufacturing method of a semiconductor structure, which is applied to the technical field of semiconductors. According to the invention, before the second conductive layer is formed, the ion implantation process is carried out on the substrate, so that the first ion implantation region is formed in the substrate below the deep trench, and the second ion implantation region is synchronously formed in the substrate at two sides of the deep trench, thereby saving an ion implantation process. The conduction type of the first ion implantation region (located between the control gate and the drain electrode) is opposite to that of the substrate, so that carriers can be mutually depleted, and the purpose of increasing a depletion region and the breakdown voltage is achieved; and then a second conductive layer is formed and deposited in the deep trench, and a control gate in a special shape is formed by combining a first conductive layer on the side wall of the deep trench, so that the purposes of reducing the overlapping area between the control gate and a drain electrode, reducing the gate-drain capacitance of the power semiconductor device, reducing the switching loss and finally improving the switching speed are achieved.

The invention provides a back contact battery, which comprises a semiconductor substrate, a first doping layer and a second doping layer, the main body part of the first doping layer and the main body part of the second doping layer are alternately distributed on one side of the backlight surface of the semiconductor substrate, and the conduction types of the first doping layer and the second doping layer are opposite; a spacer region is arranged between the main body part of the first doping layer and the main body part of the second doping layer; wherein the first doping layer further comprises an extension part of the first doping layer, the extension part of the first doping layer at least extends across part of the spacer region and extends below the second doping layer, and the extension part of the first doping layer is electrically connected with the second doping layer. The invention also provides a photovoltaic module. According to the back contact battery, the relative position of the second electrode and the laminated structure does not need to be considered, and the alignment problem does not need to be considered.

The invention discloses a solar cell and a photovoltaic module, which are used for realizing light trapping, electric leakage prevention, minority carrier lifetime prolonging and cell efficiency improving. Comprising a silicon substrate, a first doped semiconductor layer, a second doped semiconductor layer and a passivation layer, the silicon substrate has a first surface, a second surface and a side surface. The first surface has a pyramid structure, and the side surface comprises a first region, a second region and a third region which are sequentially distributed; the first region is adjacent to the first surface and the third region is adjacent to the second surface. The second region is recessed towards the silicon substrate by a distance of 2-10 [mu] m relative to the first region; the first area is provided with a first pyramid structure, the second area is provided with a second pyramid structure, and the third area is provided with a third pyramid structure and / or a first texture structure; the first doped semiconductor layer and the second doped semiconductor layer with opposite conduction types are respectively arranged on the first surface and the second surface; the passivation layer is arranged on the first surface, the second surface and the side surface.

The invention provides a pixel driving circuit, an array substrate and a display device. According to the embodiment of the invention, the first transistor, the pixel electrode and the second transistor are sequentially connected in series, and the first transistor and the second transistor have opposite conduction types, so that a semiconductor layer in the first transistor and a semiconductor layer in the second transistor can form a Peltier pair; the pixel electrode can serve as a hot end or a cold end of a Peltier module, charge and discharge of the pixel electrode are achieved by selectively conducting the first transistor or the second transistor, and the pixel electrode can be charged or discharged by changing the direction of current flowing through the first transistor and the second transistor. The pixel electrode is used for heating or radiating liquid crystal so as to improve the display effect of the liquid crystal panel in a high-temperature or low-temperature environment.

The invention provides a trench type field effect transistor and a manufacturing method thereof, and the trench type field effect transistor is provided with a gate trench structure and a source trench structure at one side, deviating from a substrate, of a second conductive type drift region, and the source trench structure is introduced below a source metal layer. A high electric field peak value exists at the bottoms of the gate trench structure and the source trench structure at the same time, and an avalanche breakdown current generated at the bottom of the source trench structure directly flows to the first conduction type ohmic contact region along the source trench, so that the avalanche breakdown current can be reduced without changing the channel density and the voltage endurance capability of the field effect transistor. And the current proportion of the first conduction type body region below the second conduction type source region is reduced, so that the avalanche energy of the field effect transistor is improved.

The invention provides a super-junction MOSFET structure and a preparation method thereof, and relates to the technical field of semiconductor devices. Comprising a first conductive type epitaxial layer formed on a first conductive type substrate layer; the second conduction type doped columns are formed in the middle area of the first conduction type epitaxial layer, the second conduction type doped columns comprise second preset conduction type doped columns and a plurality of second target conduction type doped columns located on the two sides of the lower surfaces of the second preset conduction type doped columns, and the second target conduction type doped columns are arranged at intervals; the second conduction type body region is formed on the second preset conduction type doped column; the plurality of first conductive type source regions are formed in the second conductive type body region and are arranged at intervals; gate oxide layers are formed in edge regions on two sides of the first conductive type epitaxial layer; the polycrystalline silicon layer is formed on the gate oxide layer; and sequentially forming a plurality of interlayer dielectric layers and metal layers on the polycrystalline silicon layer. And the failure risk caused by starting of an in-vivo parasitic NPN triode is reduced.

The invention discloses a semiconductor test structure and a test method thereof. According to the invention, the P-type well regions and the N-type well regions which are alternately distributed are formed in the active region, and the S-shaped active region metal silicide strips serving as S-shaped test structures are formed on the surface of the active region; the two ends of the snakelike active region metal silicide strip are located above the well regions of different conduction types respectively, so that the snakelike active region metal silicide strip covers the surfaces of the PN junctions which are connected in series; through the snakelike test structure, the square resistance of the snakelike active region metal silicide strip can be accurately measured, whether electric leakage exists in the substrate or not is detected, and whether continuity of the snakelike active region metal silicide strip is abnormal or not and whether bridging exists or not is detected. Furthermore, a cross comb-shaped test structure used for measuring the breakdown voltage of the metal silicide layer of the active region to judge whether the isolation between the active regions meets the requirement is formed in the region where the snake-shaped test structure is located, so that the comprehensiveness of the test structure can be improved, and the test area of a test pattern in a chip is saved; the area utilization rate is effectively improved.

The invention relates to the field of batteries, particularly provides a solar battery and a preparation method of the solar battery, and aims to solve the problem of serious minority carrier lifetime attenuation of the solar battery with a transparent conductive passivation layer under low injection concentration. To this end, the solar cell of the present invention comprises a first layer having a first conductivity type, a second layer having a second conductivity type, and a transparent conductive passivation layer; the second layer is arranged on the first surface of the first layer and has a second conduction type opposite to the first conduction type, so that a PN junction is formed between the first layer and the second layer; the transparent conductive passivation layer is arranged on a second surface, opposite to the first surface, of the first layer, and the transparent conductive passivation layer has a doping concentration capable of promoting majority carriers in the first layer to flow to the second surface. When the doping concentration is appropriate, the motion direction of the majority carriers can be influenced, so that the bending direction and degree of the energy band can promote the majority carriers to flow to the second surface of the first layer, and the service life of the minority carriers is prolonged.

The embodiment of the invention discloses a semiconductor device, a manufacturing method, a power module, a power conversion circuit and a vehicle. The semiconductor device comprises a semiconductor body which comprises a first surface and a second surface which are oppositely arranged; the semiconductor body further comprises a well region, a first region and a channel layer, the first region is in contact with the channel layer, the first region is of a first conductive type and located on the first surface, and the well region is of a second conductive type and located on the side, away from the first surface, of the first region; a gate trench extending from the first surface into the semiconductor body; the channel layer is arranged to be of a first conduction type and is located between the well region and the side wall of the gate trench; a gate structure; a drain electrode; and a source electrode. According to the technical scheme, the depletion type semiconductor device is formed, negative voltage needs to be applied between the grid electrode and the source electrode to cut off the channel when the depletion type semiconductor device is in the conducting state and the cut-off state in the normal state, response can be made faster, current circulation can be controlled, the conducting loss is small, and the depletion type semiconductor device is more suitable for a high-frequency circuit and a switching circuit.

The invention discloses a semiconductor laser and a preparation method thereof, which can be used in the field of semiconductor device preparation, and the method comprises the steps: firstly, providing a first conductive type substrate; then, epitaxially growing a buffer layer of a first conduction type, a lower optical waveguide limiting layer, a quantum well active light-emitting layer, an upper optical waveguide limiting layer, a corrosion barrier layer, a current injection layer and an intrinsic ohmic contact layer on the substrate in sequence to obtain a multi-layer epitaxial layer; then, etching the multi-layer epitaxial layer to the corrosion barrier layer based on a preset pattern to form a ridge-shaped table which starts from the intrinsic ohmic contact layer and is deeply cut off to the corrosion barrier layer; and finally, performing particle doping in a region corresponding to the ridge-shaped table, and converting one sides, close to the corrosion barrier layer, of the intrinsic ohmic contact layer, the current injection layer, the corrosion barrier layer and the upper optical waveguide limiting layer into a second conduction type. Therefore, current limitation can be realized without performing multiple epitaxy like a traditional buried heterojunction, and the production cost and the process difficulty are greatly reduced.

The invention discloses a back contact battery, a manufacturing method thereof and a photovoltaic module, relates to the technical field of photovoltaic, and aims to improve the double-sided rate of the back contact battery and improve the conversion efficiency of the back contact battery. The back contact cell includes a semiconductor substrate, a doped semiconductor portion, and a spacer region. The doped semiconductor portion includes a first doped semiconductor portion and a second doped semiconductor portion. The first doped semiconductor part and the second doped semiconductor part are opposite in conduction type and are arranged on the first face of the semiconductor substrate at intervals in the first direction, and the first direction is parallel to the first face. The spacer region is a region, which is not correspondingly provided with the first doped semiconductor part and the second doped semiconductor part, in the first surface of the semiconductor substrate. Wherein the surfaces of the spacer regions are suede surfaces. In the first direction, the first doped semiconductor part and / or the second doped semiconductor part comprises a first doped region and a second doped region located on at least one side of the first doped region, and the doping forms of the first doped region and the second doped region are different.

The present invention provides an integrated structure composite conduction type solid oxide cell and a preparation method thereof, and belongs to the technical field of solid oxide fuel cells, the integrated structure composite conduction type solid oxide cell comprises: an integrated skeleton, the integrated skeleton comprises an electrolyte layer and porous layers on two sides, the integrated skeleton is composed of a proton conductor material and an oxygen ion conductor material, the molar ratio of the proton conductor material to the oxygen ion conductor material is 1: (0.8-1.2), and the proton / oxygen ion composite material is prepared by mixing and sintering the proton conductor material with the average particle size of 50-60 nm and the oxygen ion conductor material with the average particle size of 0.1-0.2 [mu] m; the catalyst layer is positioned on the pore wall of the porous layer. According to the invention, by limiting the proportion and the particle size of the proton conductor material and the oxygen ion conductor material, more conduction type paths are prepared, and the output power of the solid oxide battery is improved.

The embodiment of the invention discloses a solar cell, a cell string, a cell module and a photovoltaic system. The solar cell comprises a substrate and a plurality of doping units arranged on a first surface of the substrate, wherein the plurality of doping units are sequentially arranged along a first direction; each doping unit in the plurality of doping units comprises a first doping layer and a second doping layer which are sequentially arranged along a first direction; the conduction types of the first doping layer and the second doping layer are different; in the thickness direction of the solar cell, the first doping layer comprises a first surface and a second surface which are oppositely arranged, and the first surface is farther away from the substrate than the second surface; the plurality of doping units comprise a first doping unit, and a first surface of a first doping layer in the first doping unit comprises a first part and a second part which are arranged along a first direction; the doping concentration of the first portion of the first doped layer is smaller than the doping concentration of the second portion of the first doped layer. According to the technical scheme, the power loss is effectively reduced, and the conversion efficiency of the battery is improved.