224 results about "Conduction type" patented technology

According to the back contact battery and the preparation method thereof provided by the invention, doping elements penetrate through the third doping region between the first doping region and the second doping region through high-temperature diffusion to form an electric leakage channel, so that a new back surface structure of the back contact battery is provided. The third doped region is formed by mixing the doping elements of the first doped region and the doping elements of the second doped region, doping of the two impurities is completed at a high temperature in one step, so that an electric leakage channel of an overlapping region is not generated, and the overlapping region of the two doped semiconductor layers with opposite conduction types in the thickness direction of the semiconductor substrate is removed, so that the conductivity of the semiconductor substrate is improved. Therefore, electric leakage loss of the back contact battery in a forward voltage area can be controlled, current in the electric leakage channel is introduced to the grid line of the first electrode or the second electrode through the electric leakage channel or the connecting electrode, the hot spot risk of the back contact battery is reduced, the safety performance of the back contact battery is effectively improved, and the service life of the back contact battery is prolonged. And the back contact battery has relatively high working performance.

The embodiment of the invention provides a back contact cell and a preparation method thereof, and a photovoltaic module, and relates to the field of solar cells, the back contact cell comprises a silicon substrate, the back surface of the silicon substrate comprises a first region, a second region and a spacer region, the first region comprises a first sub-region and a second sub-region, and the spacer region comprises a second sub-region and a third sub-region; the spacer region comprises a first spacer sub-region adjacent to the first region and a second spacer sub-region adjacent to the second region; the first carrier collection layer has a first conduction type, is arranged on the back surface of the silicon substrate and is positioned in the first region and the first spacer region; the amorphous semiconductor layer is arranged on the first carrier collection layer and is positioned in the second sub-region and the first spacer sub-region; the second carrier collection layer has an opposite second conduction type, is arranged on the back surface of the silicon substrate, is positioned in the second region, the spacer region and the second sub-region, and is positioned on the amorphous semiconductor layer in the second sub-region and the first spacer region; and the first electrode is arranged in the first sub-region and is positioned on one side, far away from the silicon substrate, of the first carrier collection layer. The back contact battery has excellent electrical properties.

The invention discloses a semiconductor laser and a preparation method thereof, which can be used in the field of semiconductor device preparation, and the method comprises the steps: firstly, providing a first conductive type substrate; then, epitaxially growing a buffer layer of a first conduction type, a lower optical waveguide limiting layer, a quantum well active light-emitting layer, an upper optical waveguide limiting layer, a corrosion barrier layer, a current injection layer and an intrinsic ohmic contact layer on the substrate in sequence to obtain a multi-layer epitaxial layer; then, etching the multi-layer epitaxial layer to the corrosion barrier layer based on a preset pattern to form a ridge-shaped table which starts from the intrinsic ohmic contact layer and is deeply cut off to the corrosion barrier layer; and finally, performing particle doping in a region corresponding to the ridge-shaped table, and converting one sides, close to the corrosion barrier layer, of the intrinsic ohmic contact layer, the current injection layer, the corrosion barrier layer and the upper optical waveguide limiting layer into a second conduction type. Therefore, current limitation can be realized without performing multiple epitaxy like a traditional buried heterojunction, and the production cost and the process difficulty are greatly reduced.

The embodiment of the invention discloses a solar cell, a cell string, a cell module and a photovoltaic system. The solar cell comprises a substrate and a plurality of doping units arranged on a first surface of the substrate, wherein the plurality of doping units are sequentially arranged along a first direction; each doping unit in the plurality of doping units comprises a first doping layer and a second doping layer which are sequentially arranged along a first direction; the conduction types of the first doping layer and the second doping layer are different; in the thickness direction of the solar cell, the first doping layer comprises a first surface and a second surface which are oppositely arranged, and the first surface is farther away from the substrate than the second surface; the plurality of doping units comprise a first doping unit, and a first surface of a first doping layer in the first doping unit comprises a first part and a second part which are arranged along a first direction; the doping concentration of the first portion of the first doped layer is smaller than the doping concentration of the second portion of the first doped layer. According to the technical scheme, the power loss is effectively reduced, and the conversion efficiency of the battery is improved.

A gate structure is formed on a substrate at the junction of a well region and a drift region, the gate structure on the drift region is doped to form a first doped region and a second doped region which are adjacent to each other, the first doped region is doped with first type ions, and the second doped region is doped with second type ions; the conduction types of the second type ions and the first type ions are different, so that the first doped region and the second doped region form a reverse biased PN junction, an electric field caused by the interconnection structure can be balanced and dispersed in the direction from the drain electrode to the source electrode, and the high voltage of the interconnection structure can be effectively isolated; besides, the first doped region and the second doped region form a reverse-biased PN junction to disperse the high potential difference between the first doped region and the second doped region, so that the electric field intensity and the potential peak value on the surface of the device are effectively reduced, the segmented voltage division effect is beneficial to optimization of electric field distribution on the surface of the device, electric field concentration is reduced, and the performance of the device is improved. Therefore, the breakdown voltage of the semiconductor structure is improved.

The invention discloses a heat conduction type heat dissipation cable, and relates to the technical field of heat dissipation cables, the heat conduction type heat dissipation cable comprises a central capillary main pipe, a plurality of conductor strands are arranged on the outer side of the central capillary main pipe, a heat dissipation ring is arranged on the other side of each conductor strand, and a plurality of first heat dissipation holes are integrally formed in the heat dissipation ring; according to the invention, heat generated by the conductor strands is quickly transmitted through the heat conducting column, and the magnetic conductive sheet and the magnetocaloric material sheet are matched to generate magnetocaloric effect by utilizing magnetic field intensity fluctuation caused by current change: when the current is increased, heat is released to strengthen evaporation of a working medium, and when the current is reduced, heat is absorbed to directly cool, so that a self-adaptive heat adjusting mechanism is formed; heat can be quickly transferred through evaporation-condensation of low-boiling-point fluid through phase change circulation of the central capillary main pipe and the branch capillary pipes, and multi-path heat dissipation of the heat dissipation ring and the fins is combined, so that the heat dissipation efficiency under different current loads is improved, and the problem of local overheating is effectively avoided.

The invention discloses a solar cell and a photovoltaic module, which are used for realizing light trapping, electric leakage prevention, minority carrier lifetime prolonging and cell efficiency improving. Comprising a silicon substrate, a first doped semiconductor layer, a second doped semiconductor layer and a passivation layer, the silicon substrate has a first surface, a second surface and a side surface. The first surface has a pyramid structure, and the side surface comprises a first region and a second region which are sequentially distributed; the first region is adjacent to the first surface and the second region is adjacent to the first region. The second region is recessed into the silicon substrate by a first distance relative to the first region; the first doped semiconductor layer and the second doped semiconductor layer with opposite conduction types are respectively arranged on the first surface and the second surface; the passivation layer is arranged on the first surface, the second surface and the side surface; the second surface comprises groove regions and doped regions which are alternately arranged, and the groove regions are recessed towards the silicon substrate by a second distance relative to the doped regions; the second doped semiconductor layer is located in the doped region, and the passivation layer is located in the trench region and the doped region; wherein the first distance is greater than or equal to the second distance.

The invention discloses a back contact solar cell, a photovoltaic module and a photovoltaic system, and relates to the technical field of solar cells. The back contact solar cell comprises a first region, a second region and an isolation region which are arranged on the backlight surface of a silicon substrate, the first region and the second region are covered with a first doping layer and a second doping layer respectively, and the first doping layer and the silicon substrate are opposite in conduction type; the edges of the first region and the isolation region are provided with extension parts extending to the upper part of the isolation region; a first suede structure is arranged on the first side wall, close to the first area, of the isolation area, and a second suede structure is arranged at the bottom of the isolation area; the first suede structure is formed by protruding the first side wall of the isolation area in the first direction, the second suede structure is formed by protruding the bottom of the isolation area in the second direction, and the first direction is perpendicular to the second direction. According to the invention, the leakage current between the first doped layer and the second doped layer can be reduced, and the recombination of current carriers on the surface of the isolation region is avoided, thereby reducing the parallel resistance.

The invention relates to a back contact battery, a manufacturing method thereof and a photovoltaic module. The back contact battery comprises a substrate which comprises a first surface and a second surface which are oppositely arranged, and a side surface which is connected with the first surface and the second surface; the first surface is provided with first regions and second regions which are alternately arranged, and the conduction types of the first regions and the second regions are different; the first region comprises a tunneling layer, a first semiconductor doping layer and a first transparent conducting layer which are sequentially arranged away from the substrate; the second region comprises an amorphous silicon layer, a second semiconductor doping layer and a second transparent conducting layer which are sequentially arranged in the direction away from the substrate; the side surface comprises a first passivation layer and a second passivation layer which are sequentially arranged away from the substrate, and the first passivation layer is connected with the first semiconductor doping layer and makes contact with the first semiconductor doping layer. The carrier recombination of the side surface is effectively improved, the passivation effect of the side surface is improved, the open-circuit voltage, the filling factor and the photoelectric conversion efficiency of the back contact battery are further improved, and the power generation performance of the back contact battery is improved.

The invention relates to the technical field of semiconductor devices, and discloses a wide bandgap power semiconductor device and a preparation method thereof. The method comprises: providing a substrate layer of a first conductivity type; forming a first doped region which is deep into the substrate layer and comprises a plurality of doped layers which are sequentially nested from outside to inside, wherein the doping concentrations of the plurality of doped layers are sequentially increased from outside to inside; forming a second doped region in the doped layer on the innermost side of the first doped region; forming an isolation layer on the first surface; forming a control electrode on the isolation layer; forming a first electrode on the first surface; a second electrode is formed on the second surface of the substrate layer. According to the invention, the first doped region which is located between the substrate layer and the second doped region and has the doping concentration gradually increased from outside to inside is formed through a mode of multiple times of ion implantation, so that transverse electric field constraint is constructed, transverse depletion of a channel region and a short channel effect under the condition of large voltage are inhibited, the channel width is reduced, and the performance of the device is improved. And the device performance and reliability are improved.

The invention relates to a back-illuminated image sensor and a preparation method thereof. The back-illuminated image sensor comprises a substrate, and photodiodes and target isolation laminations which are located on a first surface of the substrate, are alternately arranged along a first direction parallel to the first surface and extend towards the substrate, the substrate internally comprises a plurality of trench isolation structures which extend into the substrate through the first surface and are arranged at intervals in the first direction; the trench isolation structures are located right below the target isolation laminations which are arranged in a one-to-one manner; the photodiode comprises a first photosensitive area and a second photosensitive area which are stacked in the second direction away from the substrate. The second photosensitive area is formed in the first photosensitive area through solid phase diffusion; the first photosensitive area comprises at least three photosensitive layers made of different materials; the conductive type of the target isolation lamination layer is opposite to that of the first photosensitive area, and the side wall of the target isolation lamination layer is zigzag. The number of Quantum <-> can be increased through the Photo diodes of different layer structures.

The invention provides a solar cell and a preparation method thereof. The solar cell comprises a silicon substrate, the silicon substrate comprises a first main surface and a second main surface which are opposite, and the first main surface comprises a first area; the first silicon oxide layer is arranged in the first region; the first doped polycrystalline silicon layer is arranged on the first silicon oxide layer; the second silicon dioxide layer is arranged on the first doped polycrystalline silicon layer; the second doped polycrystalline silicon layer is arranged on the second silicon dioxide layer; the first doped polycrystalline silicon layer and the second doped polycrystalline silicon layer are the same in conduction type, and the thickness of the second silicon oxide layer is larger than that of the first silicon oxide layer. According to the solar cell, the preparation process difficulty can be reduced, the controllability of the thickness of the second silicon dioxide layer is improved, the stability of the electrical property of the solar cell with the structure is ensured, and the production efficiency is improved.

To provide a heat transfer gas sensor system and a sensing method having high accuracy and sensitivity.SOLUTION: A heat transfer gas sensor system includes a measurement unit, a control unit, and a calculation unit. The measurement unit includes a sensor unit capable of measuring a resistance value and a heater unit capable of heating the sensor unit. The control unit has a heater control circuit capable of controlling heating and non-heating of the heater unit, and a timing control circuit capable of controlling timing of a control signal of heating and non-heating of the heater unit and an output signal from the sensor unit. The calculation unit acquires a first output signal from the sensor unit when the heater unit is not heating, and corrects a second output signal from the sensor unit when the heater unit is heating, using the first output signal.SELECTED DRAWING: Figure 1

The present disclosure relates to a trench-type DMOS device and manufacturing method therefor. The trench-type DMOS device includes an expansion gate layer disposed on an inner surface of a gate insulation layer, and the expansion gate layer includes a first expansion gate region with a second conduction type, a second expansion gate region with a first conduction type, and a third expansion gate region, which improves a contradiction relationship between voltage resistance and specific on-resistance of the trench-type DMOS device. Therefore, the trench-type DMOS device has both high voltage resistance and low specific on-resistance. The trench-type DMOS device has a longitudinal voltage resistance structure, which reduces device area and further decreases device on-resistance. At the same time, a source region and a drain region in the trench-type DMOS device may be led out on its front surface, which is compatible with CMOS.

The invention discloses a back contact heterojunction solar cell and a preparation method thereof. The back contact heterojunction solar cell comprises a silicon substrate, wherein a first main surface of the silicon substrate is provided with a first functional region, an isolation region for blocking the first functional region and a second functional region, and a second functional region; the first carrier collection layer is arranged on the first functional area; an insulating layer covering the first carrier collection layer; the second carrier collection layer is arranged on the second functional area and the insulating layer corresponding to the first functional area; a conductive layer disposed on the second carrier collection layer; the conduction types of the first carrier collection layer and the second carrier collection layer are opposite; conductive holes are formed in the second carrier collection layer and the insulating layer corresponding to the first functional area; and the conductive layer corresponding to the first functional area extends to the conductive hole and is in contact with the first carrier collection layer. And the performance of the back contact heterojunction solar cell is effectively improved.

The utility model belongs to the technical field of heating cables, and provides a temperature-sensing heat-conducting high-power insulating heating cable, which comprises three phases of power lines arranged in parallel; the insulating layer is arranged on the outer side of the three-phase power line; the inner protective metal layer is arranged on the outer side of the insulating layer; the temperature sensing test line is arranged on the outer side of the metal layer; the heat conduction wire is arranged on the outer side of the metal layer, and the heat conduction wire and the temperature sensing test wire are arranged in the circumferential direction of the outer wall of the inner protection metal layer; and the corrosion-resistant outer metal sleeve is arranged on the outer side of the temperature sensing test wire and the heat conduction wire. According to the utility model, the temperature sensing test line and the three-phase power line jointly form the temperature sensing heat conduction type high-power insulation heating cable, and the temperature sensing line and the heating cable are put into a well at the same time, so that whether the heating cable is abnormal or not can be intuitively judged through the temperature sensing test line, the accuracy of the heating cable in use is improved, and the operation is facilitated at the same time.

Organic bipolar transistor (100), comprising a crystalline first organic semiconductor layer (108) on or above a substrate (102), wherein the crystalline first organic semiconductor layer (108) has a first conduction type; and a crystalline second organic semiconductor layer (112) on or above the crystalline first organic semiconductor layer (108), wherein the crystalline second organic semiconductor layer (112) has a second conduction type, wherein the first conduction type differs from the second conduction type, wherein the crystalline first organic semiconductor layer (108) has a first dopant and the crystalline second organic semiconductor layer (112) has a second dopant which differs from the first dopant; wherein the crystalline first organic semiconductor layer (108) exhibits a first crystallinity and the crystalline second organic semiconductor layer (112) exhibits a second crystallinity, where the second crystallinity is less than or equal to the first crystallinity; a third organic semiconductor layer (110) arranged between the crystalline first organic semiconductor layer (108) and the crystalline second organic semiconductor layer (112), wherein the third organic semiconductor layer (110) is undoped, wherein the third organic semiconductor layer (110) has a third crystallinity that is less than or equal to the first crystallinity of the crystalline first organic semiconductor layer (108); and a fourth organic semiconductor layer (116) arranged on or above the crystalline second organic semiconductor layer (112), wherein the fourth organic semiconductor layer (116) has the same conduction type as the crystalline first organic semiconductor layer (108), wherein the fourth organic semiconductor layer (116) has a fourth crystallinity that is less than or equal to the second crystallinity of the crystalline second organic semiconductor layer (112).

The utility model discloses a bone conduction type under-pillow sleep-aiding sound box, which comprises a supporting mechanism and a contraction mechanism, the supporting mechanism comprises a sound box, a bidirectional connector, supporting cylinders, a connecting wire, a control switch and a playing head, the bidirectional connector is installed at the upper end of the sound box, the supporting cylinders are installed on the two opposite sides of the bidirectional connector, and the connecting wire is connected with the control switch. The connecting line is connected with the supporting cylinder in an inserted mode, the contraction mechanism comprises at least two arc-shaped fastening plates, telescopic springs, an inner limiting plate, a fixing cylinder, a sliding guide rod, a movable isolation disc, an anti-slip strip and an outer limiting plate, the number of the arc-shaped fastening plates is at least two, and the connecting line is located between the two arc-shaped fastening plates. And the sliding guide rod is mounted on the surface of the upper end of the arc-shaped fastening plate. The two playing heads are arranged, then the distance is adjusted according to the length of the pillow and the sleeping habit of a user, the two playing heads are located on the two sides of the two ears of the user, and the experience feeling of the user is improved.

The invention provides an LDMOS device and a manufacturing method thereof, and relates to the technical field of semiconductors. The LDMOS device may include: a semiconductor substrate; the drift region is located on the semiconductor substrate and is provided with a first conduction type; the body region is located at one end of the drift region and has a second conductive type; the gate structure is positioned on the surface of the body region and partially extends to the drift region; the source region is located in the body region and is adjacent to one side of the gate structure, and the body contact region is adjacent to the source region and is of a second conduction type; the drain region is located at one end, away from the body region, of the drift region; and the plurality of strip-shaped current modulation units are arranged in the drift region in an interdigital alternate arrangement mode, and extend and are arranged in the direction from the body region to the drain region. The chip has the advantages of being low in cost, small in overall chip area and easier to manufacture.

The utility model discloses a low capacitance SCR structure ESD protection device, and relates to the safety protection field, the low capacitance SCR structure ESD protection device comprises a first conduction type substrate, and the first conduction type substrate is successively arranged above the first conduction type substrate; the beneficial effects of the utility model are that the Schottky diode auxiliary trigger structure adopted by the utility model can improve the problem of local overheating caused by delayed starting response speed and current concentration of a conventional low-capacitance SCR device of a PN junction auxiliary trigger structure formed by adopting high-concentration injected N-type and P-type impurities, thereby improving the reliability of the device; due to the fact that the Schottky junction is better in high-temperature performance and current capacity, the overall size of the auxiliary trigger structure can be further compressed during design, for example, the number of stripes or the size of the stripes is reduced, and the capacitance value of the SCR protection device is further reduced in this way.

The invention relates to the technical field of semiconductors, and discloses a semiconductor structure and a semiconductor device. The semiconductor structure comprises a semiconductor substrate layer; the buffer layer and the drift layer are sequentially stacked on the first surface of the semiconductor substrate layer; the doping concentration of the buffer layer is gradually reduced in the direction from the semiconductor substrate layer to the drift layer; a first doped region in the buffer layer; wherein the conduction type of the buffer layer is the same as that of the drift layer, and is opposite to that of the first doped region; the doping concentration of the drift layer is smaller than or equal to the doping concentration of the buffer layer. The semiconductor structure can effectively suppress voltage and current oscillation and overshoot phenomena, and realizes a softer reverse recovery characteristic.

The invention discloses a non-contact conduction type weak ultrasound-assisted laser direct energy deposition device and method, and belongs to the technical field of additive manufacturing equipment. The invention discloses a non-contact conduction type weak ultrasound-assisted laser direct energy deposition device. The non-contact conduction type weak ultrasound-assisted laser direct energy deposition device comprises a powder feeding printing part, a printing platform and an ultrasonic vibration part. The printing end of the powder feeding printing part and a molten pool formed in the upper surface of the printing platform are oppositely arranged. The output end of the ultrasonic vibration part is arranged at a fixed distance from the molten pool; and the ultrasonic vibration part is fixedly connected with the powder feeding and printing part. According to the device disclosed by the invention, ultrasonic sound waves output by the ultrasonic vibration component in the printing process are attenuated from the emission head through air (protective gas) and enter a molten pool in a non-contact transmission mode, and negative effects such as over-strong cavitation bubbles are avoided while grain refinement and residual stress elimination are realized.

The embodiment of the invention discloses a semiconductor device and a preparation method thereof. The semiconductor device comprises a substrate which is of a first conduction type and is provided with second conduction type structures at two sides, an emission unit, an electrode layer and a groove; the second conductive type structure comprises a first region, a short base region and a second region; the ion concentration of the second region is larger than that of the short base region and smaller than that of the first region; the emission unit is of a first conductive type and is located on the side, away from the substrate, of the second conductive type structure. The electrode layer is located at one side of the emission unit and the second conductive type structure away from the substrate; the groove surrounds the second conductive type structure; the groove is in a snake shape; the bottom of the trench is in contact with the substrate, and the side wall of the trench is in contact with the short base region and the second region. According to the technical scheme of the embodiment of the invention, a larger through-flow area is realized while high voltage is met, the through-flow area reduction caused by boundary corrosion expansion is avoided, and the large current resistance of the semiconductor device is improved.

The invention provides a solar cell and a manufacturing method thereof, and relates to the field of solar cells. The invention aims to solve the problem that the passivation influence of laser on a textured P region is relatively large. The manufacturing method comprises the steps that a semiconductor substrate of a first conduction type is provided, the back face of the semiconductor substrate comprises first parts and second parts which are alternately arranged, and third parts located between the adjacent first parts and second parts; the first part comprises a first sub-part and a second sub-part, and the second sub-part is adjacent to the third part; forming a diffusion layer and a first mask layer; forming a tunneling passivation layer; forming a doped polycrystalline material layer and a second mask layer; removing the second mask layer on the third part and the second sub-part by utilizing first laser etching; and exposing the surface of the semiconductor substrate corresponding to the third part and the second sub-part by adopting a wet etching mode to form a step-shaped spacing structure. The manufacturing method has no adverse effect on passivation of the area where the emitter is located.

The present disclosure provides a latch circuit, a dynamic latch, a dynamic D flip-flop, and related apparatuses. The latch circuit includes: first and second transistor groups of a first conduction type and third and fourth transistor groups of a second conduction type that are sequentially connected in series between a power supply and ground. A node between the second and third transistor groups is connected to an output end. A control end of one of the first and second transistor groups and a control end of one of the third and fourth transistor groups are jointly connected to an input end. The other of the first and second transistor groups receives a first clock signal. The other of the third and fourth transistor groups receives an inverted second clock signal. At least one of the first to fourth transistor groups includes a plurality of transistors connected in series.

The invention discloses a semiconductor device and a preparation method thereof, and a power device, the semiconductor device comprises an emitter group, a first base region and a second base region, the emitter group comprises a first emitter and a second emitter, and the first emitter and the second emitter are opposite in conduction type; the first base region is arranged between the first emitter and the second emitter along the first direction, and the first base region and the first emitter are opposite in conduction type; the second base region is arranged between the first base region and the second emitter along the first direction, and the conduction type of the second base region is opposite to that of the second emitter; wherein at least one of the first base region and the second base region comprises a plurality of first doped regions which are stacked along the first direction, a second doped region is arranged between at least two adjacent first doped regions along the first direction, and the second doped region is doped with deep-energy-level impurities. According to the embodiment of the invention, the semiconductor device can reduce the on-state voltage drop under the condition of strong surge current so as to inhibit the further rise of the junction temperature.

The invention relates to a semiconductor power device and a preparation method thereof. The semiconductor power device comprises a substrate, an epitaxial layer, a first grid electrode, a second grid electrode, a first dielectric layer, a second dielectric layer, a polycrystalline silicon region and a source electrode, wherein the material of the substrate comprises silicon carbide; the epitaxial layer comprises a drift region, a well layer, a first groove, a source region and a source contact region; the first groove extends into the drift region from the surface, far away from the substrate, of the epitaxial layer and penetrates through the well layer; the first grid electrode and the second grid electrode are located in the first groove, and the first grid electrode and the second grid electrode are arranged in an isolated mode. The first dielectric layer wraps the first grid electrode, the second dielectric layer wraps the second grid electrode, and the polycrystalline silicon region of the second conduction type is located between the first dielectric layer and the second dielectric layer and is in contact with the drift region to form a heterojunction diode; the source electrode is electrically connected with the second grid electrode to form a transistor of which the local grid electrode and the drain electrode are short-circuited, and the source electrode is also electrically connected with the polycrystalline silicon region. According to the invention, the conduction loss of the third quadrant can be reduced and the switching loss can be significantly reduced.

The invention relates to the technical field of infrared optical materials, and particularly discloses an N-type chromium-doped high-resistance infrared silicon single crystal and a preparation method thereof. The N-type chromium-doped high-resistance infrared silicon single crystal is singly doped, the doping concentration of chromium oxide is 40-160ppm, and in the preparation process, specific constant-temperature heat treatment is carried out in a cooling stage. The concentration of free carriers in the silicon single crystal is remarkably reduced by singly doping chromium oxide and utilizing the deep energy level compensation effect of chromium element, the conduction type of the single crystal is N type, the resistivity is stably increased to above 1120ohm.cm, the average infrared transmittance of the wave band of 2-6 microns is greater than 53%, the stress birefringence is less than 3nm / cm, the process window is wide, and the operation is simple and convenient. The method is particularly suitable for preparing the silicon single crystal of a large-size and high-performance infrared optical system.

The utility model discloses a multilayer heat conduction type flexible circuit board, comprising a supporting seat, two ends of the supporting seat are provided with a plurality of first screws, the supporting seat is fixedly installed in an external equipment shell through the first screws, the upper end of the supporting seat is provided with a multilayer flexible circuit board, the multilayer flexible circuit board is placed on the supporting seat, and the supporting seat is provided with a plurality of second screws. The end, close to the supporting base, of the multi-layer flexible circuit board is a welding end, and the welding end of the multi-layer flexible circuit board is welded to an external hard circuit board. Outer edge thin film parts are fixed to the outer surfaces of the two sides of the multi-layer flexible circuit board, two sets of symmetrically-distributed fixing mechanisms are arranged at the upper end of the supporting base, and the outer edge thin film parts of the multi-layer flexible circuit board are fixed, so that external tension acts on the outer edge thin film parts; and external tension is prevented from directly acting on the welding part of the multi-layer flexible circuit board and the hard circuit board. The fragile welding position can be protected, and the situation that the welding position between the multi-layer flexible circuit board and the circuit board hard board is broken is reduced.

The invention provides an FRD device and a preparation method thereof, and the preparation method of the FRD device comprises the following steps: providing a semiconductor layer at least comprising a cellular region and a terminal region, and forming a patterned dielectric layer on the upper surface of the semiconductor layer; forming a base region located in the cellular region and a voltage-withstanding region located in the terminal region based on the patterned dielectric layer; forming a protective layer on the exposed surfaces of the base region and the voltage-withstanding region, forming a platinum layer covering the bottom surface of the semiconductor layer, and annealing to diffuse platinum into the semiconductor layer; and forming an upper electrode electrically connected with the base region and a metal field plate electrically connected with the semiconductor layer at the edge of one side, far away from the cellular region, of the terminal region above the semiconductor layer, wherein the contact type of the metal field plate and the semiconductor layer is Schottky contact. The manufacturing process of the device is improved, the step of forming a first conduction type field cut-off region is omitted, Schottky contact is formed between the metal field plate and the edge of the device, the performance of the device is guaranteed, meanwhile, the cost is reduced, and the production period is shortened.