129 results about "Conduction type" patented technology

The invention discloses a semiconductor laser and a preparation method thereof, which can be used in the field of semiconductor device preparation, and the method comprises the steps: firstly, providing a first conductive type substrate; then, epitaxially growing a buffer layer of a first conduction type, a lower optical waveguide limiting layer, a quantum well active light-emitting layer, an upper optical waveguide limiting layer, a corrosion barrier layer, a current injection layer and an intrinsic ohmic contact layer on the substrate in sequence to obtain a multi-layer epitaxial layer; then, etching the multi-layer epitaxial layer to the corrosion barrier layer based on a preset pattern to form a ridge-shaped table which starts from the intrinsic ohmic contact layer and is deeply cut off to the corrosion barrier layer; and finally, performing particle doping in a region corresponding to the ridge-shaped table, and converting one sides, close to the corrosion barrier layer, of the intrinsic ohmic contact layer, the current injection layer, the corrosion barrier layer and the upper optical waveguide limiting layer into a second conduction type. Therefore, current limitation can be realized without performing multiple epitaxy like a traditional buried heterojunction, and the production cost and the process difficulty are greatly reduced.

The invention discloses a solar cell and a photovoltaic module, which are used for realizing light trapping, electric leakage prevention, minority carrier lifetime prolonging and cell efficiency improving. Comprising a silicon substrate, a first doped semiconductor layer, a second doped semiconductor layer and a passivation layer, the silicon substrate has a first surface, a second surface and a side surface. The first surface has a pyramid structure, and the side surface comprises a first region and a second region which are sequentially distributed; the first region is adjacent to the first surface and the second region is adjacent to the first region. The second region is recessed into the silicon substrate by a first distance relative to the first region; the first doped semiconductor layer and the second doped semiconductor layer with opposite conduction types are respectively arranged on the first surface and the second surface; the passivation layer is arranged on the first surface, the second surface and the side surface; the second surface comprises groove regions and doped regions which are alternately arranged, and the groove regions are recessed towards the silicon substrate by a second distance relative to the doped regions; the second doped semiconductor layer is located in the doped region, and the passivation layer is located in the trench region and the doped region; wherein the first distance is greater than or equal to the second distance.

The invention discloses a back contact solar cell, a photovoltaic module and a photovoltaic system, and relates to the technical field of solar cells. The back contact solar cell comprises a first region, a second region and an isolation region which are arranged on the backlight surface of a silicon substrate, the first region and the second region are covered with a first doping layer and a second doping layer respectively, and the first doping layer and the silicon substrate are opposite in conduction type; the edges of the first region and the isolation region are provided with extension parts extending to the upper part of the isolation region; a first suede structure is arranged on the first side wall, close to the first area, of the isolation area, and a second suede structure is arranged at the bottom of the isolation area; the first suede structure is formed by protruding the first side wall of the isolation area in the first direction, the second suede structure is formed by protruding the bottom of the isolation area in the second direction, and the first direction is perpendicular to the second direction. According to the invention, the leakage current between the first doped layer and the second doped layer can be reduced, and the recombination of current carriers on the surface of the isolation region is avoided, thereby reducing the parallel resistance.

The invention relates to a back contact battery, a manufacturing method thereof and a photovoltaic module. The back contact battery comprises a substrate which comprises a first surface and a second surface which are oppositely arranged, and a side surface which is connected with the first surface and the second surface; the first surface is provided with first regions and second regions which are alternately arranged, and the conduction types of the first regions and the second regions are different; the first region comprises a tunneling layer, a first semiconductor doping layer and a first transparent conducting layer which are sequentially arranged away from the substrate; the second region comprises an amorphous silicon layer, a second semiconductor doping layer and a second transparent conducting layer which are sequentially arranged in the direction away from the substrate; the side surface comprises a first passivation layer and a second passivation layer which are sequentially arranged away from the substrate, and the first passivation layer is connected with the first semiconductor doping layer and makes contact with the first semiconductor doping layer. The carrier recombination of the side surface is effectively improved, the passivation effect of the side surface is improved, the open-circuit voltage, the filling factor and the photoelectric conversion efficiency of the back contact battery are further improved, and the power generation performance of the back contact battery is improved.

The invention relates to the technical field of semiconductor devices, and discloses a wide bandgap power semiconductor device and a preparation method thereof. The method comprises: providing a substrate layer of a first conductivity type; forming a first doped region which is deep into the substrate layer and comprises a plurality of doped layers which are sequentially nested from outside to inside, wherein the doping concentrations of the plurality of doped layers are sequentially increased from outside to inside; forming a second doped region in the doped layer on the innermost side of the first doped region; forming an isolation layer on the first surface; forming a control electrode on the isolation layer; forming a first electrode on the first surface; a second electrode is formed on the second surface of the substrate layer. According to the invention, the first doped region which is located between the substrate layer and the second doped region and has the doping concentration gradually increased from outside to inside is formed through a mode of multiple times of ion implantation, so that transverse electric field constraint is constructed, transverse depletion of a channel region and a short channel effect under the condition of large voltage are inhibited, the channel width is reduced, and the performance of the device is improved. And the device performance and reliability are improved.

The invention relates to a back-illuminated image sensor and a preparation method thereof. The back-illuminated image sensor comprises a substrate, and photodiodes and target isolation laminations which are located on a first surface of the substrate, are alternately arranged along a first direction parallel to the first surface and extend towards the substrate, the substrate internally comprises a plurality of trench isolation structures which extend into the substrate through the first surface and are arranged at intervals in the first direction; the trench isolation structures are located right below the target isolation laminations which are arranged in a one-to-one manner; the photodiode comprises a first photosensitive area and a second photosensitive area which are stacked in the second direction away from the substrate. The second photosensitive area is formed in the first photosensitive area through solid phase diffusion; the first photosensitive area comprises at least three photosensitive layers made of different materials; the conductive type of the target isolation lamination layer is opposite to that of the first photosensitive area, and the side wall of the target isolation lamination layer is zigzag. The number of Quantum <-> can be increased through the Photo diodes of different layer structures.

The invention provides a solar cell and a preparation method thereof. The solar cell comprises a silicon substrate, the silicon substrate comprises a first main surface and a second main surface which are opposite, and the first main surface comprises a first area; the first silicon oxide layer is arranged in the first region; the first doped polycrystalline silicon layer is arranged on the first silicon oxide layer; the second silicon dioxide layer is arranged on the first doped polycrystalline silicon layer; the second doped polycrystalline silicon layer is arranged on the second silicon dioxide layer; the first doped polycrystalline silicon layer and the second doped polycrystalline silicon layer are the same in conduction type, and the thickness of the second silicon oxide layer is larger than that of the first silicon oxide layer. According to the solar cell, the preparation process difficulty can be reduced, the controllability of the thickness of the second silicon dioxide layer is improved, the stability of the electrical property of the solar cell with the structure is ensured, and the production efficiency is improved.

The present disclosure relates to a trench-type DMOS device and manufacturing method therefor. The trench-type DMOS device includes an expansion gate layer disposed on an inner surface of a gate insulation layer, and the expansion gate layer includes a first expansion gate region with a second conduction type, a second expansion gate region with a first conduction type, and a third expansion gate region, which improves a contradiction relationship between voltage resistance and specific on-resistance of the trench-type DMOS device. Therefore, the trench-type DMOS device has both high voltage resistance and low specific on-resistance. The trench-type DMOS device has a longitudinal voltage resistance structure, which reduces device area and further decreases device on-resistance. At the same time, a source region and a drain region in the trench-type DMOS device may be led out on its front surface, which is compatible with CMOS.

The invention discloses a back contact heterojunction solar cell and a preparation method thereof. The back contact heterojunction solar cell comprises a silicon substrate, wherein a first main surface of the silicon substrate is provided with a first functional region, an isolation region for blocking the first functional region and a second functional region, and a second functional region; the first carrier collection layer is arranged on the first functional area; an insulating layer covering the first carrier collection layer; the second carrier collection layer is arranged on the second functional area and the insulating layer corresponding to the first functional area; a conductive layer disposed on the second carrier collection layer; the conduction types of the first carrier collection layer and the second carrier collection layer are opposite; conductive holes are formed in the second carrier collection layer and the insulating layer corresponding to the first functional area; and the conductive layer corresponding to the first functional area extends to the conductive hole and is in contact with the first carrier collection layer. And the performance of the back contact heterojunction solar cell is effectively improved.

The utility model belongs to the technical field of heating cables, and provides a temperature-sensing heat-conducting high-power insulating heating cable, which comprises three phases of power lines arranged in parallel; the insulating layer is arranged on the outer side of the three-phase power line; the inner protective metal layer is arranged on the outer side of the insulating layer; the temperature sensing test line is arranged on the outer side of the metal layer; the heat conduction wire is arranged on the outer side of the metal layer, and the heat conduction wire and the temperature sensing test wire are arranged in the circumferential direction of the outer wall of the inner protection metal layer; and the corrosion-resistant outer metal sleeve is arranged on the outer side of the temperature sensing test wire and the heat conduction wire. According to the utility model, the temperature sensing test line and the three-phase power line jointly form the temperature sensing heat conduction type high-power insulation heating cable, and the temperature sensing line and the heating cable are put into a well at the same time, so that whether the heating cable is abnormal or not can be intuitively judged through the temperature sensing test line, the accuracy of the heating cable in use is improved, and the operation is facilitated at the same time.

Organic bipolar transistor (100), comprising a crystalline first organic semiconductor layer (108) on or above a substrate (102), wherein the crystalline first organic semiconductor layer (108) has a first conduction type; and a crystalline second organic semiconductor layer (112) on or above the crystalline first organic semiconductor layer (108), wherein the crystalline second organic semiconductor layer (112) has a second conduction type, wherein the first conduction type differs from the second conduction type, wherein the crystalline first organic semiconductor layer (108) has a first dopant and the crystalline second organic semiconductor layer (112) has a second dopant which differs from the first dopant; wherein the crystalline first organic semiconductor layer (108) exhibits a first crystallinity and the crystalline second organic semiconductor layer (112) exhibits a second crystallinity, where the second crystallinity is less than or equal to the first crystallinity; a third organic semiconductor layer (110) arranged between the crystalline first organic semiconductor layer (108) and the crystalline second organic semiconductor layer (112), wherein the third organic semiconductor layer (110) is undoped, wherein the third organic semiconductor layer (110) has a third crystallinity that is less than or equal to the first crystallinity of the crystalline first organic semiconductor layer (108); and a fourth organic semiconductor layer (116) arranged on or above the crystalline second organic semiconductor layer (112), wherein the fourth organic semiconductor layer (116) has the same conduction type as the crystalline first organic semiconductor layer (108), wherein the fourth organic semiconductor layer (116) has a fourth crystallinity that is less than or equal to the second crystallinity of the crystalline second organic semiconductor layer (112).

The invention provides an LDMOS device and a manufacturing method thereof, and relates to the technical field of semiconductors. The LDMOS device may include: a semiconductor substrate; the drift region is located on the semiconductor substrate and is provided with a first conduction type; the body region is located at one end of the drift region and has a second conductive type; the gate structure is positioned on the surface of the body region and partially extends to the drift region; the source region is located in the body region and is adjacent to one side of the gate structure, and the body contact region is adjacent to the source region and is of a second conduction type; the drain region is located at one end, away from the body region, of the drift region; and the plurality of strip-shaped current modulation units are arranged in the drift region in an interdigital alternate arrangement mode, and extend and are arranged in the direction from the body region to the drain region. The chip has the advantages of being low in cost, small in overall chip area and easier to manufacture.

The utility model discloses a low capacitance SCR structure ESD protection device, and relates to the safety protection field, the low capacitance SCR structure ESD protection device comprises a first conduction type substrate, and the first conduction type substrate is successively arranged above the first conduction type substrate; the beneficial effects of the utility model are that the Schottky diode auxiliary trigger structure adopted by the utility model can improve the problem of local overheating caused by delayed starting response speed and current concentration of a conventional low-capacitance SCR device of a PN junction auxiliary trigger structure formed by adopting high-concentration injected N-type and P-type impurities, thereby improving the reliability of the device; due to the fact that the Schottky junction is better in high-temperature performance and current capacity, the overall size of the auxiliary trigger structure can be further compressed during design, for example, the number of stripes or the size of the stripes is reduced, and the capacitance value of the SCR protection device is further reduced in this way.

The invention relates to the technical field of semiconductors, and discloses a semiconductor structure and a semiconductor device. The semiconductor structure comprises a semiconductor substrate layer; the buffer layer and the drift layer are sequentially stacked on the first surface of the semiconductor substrate layer; the doping concentration of the buffer layer is gradually reduced in the direction from the semiconductor substrate layer to the drift layer; a first doped region in the buffer layer; wherein the conduction type of the buffer layer is the same as that of the drift layer, and is opposite to that of the first doped region; the doping concentration of the drift layer is smaller than or equal to the doping concentration of the buffer layer. The semiconductor structure can effectively suppress voltage and current oscillation and overshoot phenomena, and realizes a softer reverse recovery characteristic.

The embodiment of the invention discloses a semiconductor device and a preparation method thereof. The semiconductor device comprises a substrate which is of a first conduction type and is provided with second conduction type structures at two sides, an emission unit, an electrode layer and a groove; the second conductive type structure comprises a first region, a short base region and a second region; the ion concentration of the second region is larger than that of the short base region and smaller than that of the first region; the emission unit is of a first conductive type and is located on the side, away from the substrate, of the second conductive type structure. The electrode layer is located at one side of the emission unit and the second conductive type structure away from the substrate; the groove surrounds the second conductive type structure; the groove is in a snake shape; the bottom of the trench is in contact with the substrate, and the side wall of the trench is in contact with the short base region and the second region. According to the technical scheme of the embodiment of the invention, a larger through-flow area is realized while high voltage is met, the through-flow area reduction caused by boundary corrosion expansion is avoided, and the large current resistance of the semiconductor device is improved.

The present disclosure provides a latch circuit, a dynamic latch, a dynamic D flip-flop, and related apparatuses. The latch circuit includes: first and second transistor groups of a first conduction type and third and fourth transistor groups of a second conduction type that are sequentially connected in series between a power supply and ground. A node between the second and third transistor groups is connected to an output end. A control end of one of the first and second transistor groups and a control end of one of the third and fourth transistor groups are jointly connected to an input end. The other of the first and second transistor groups receives a first clock signal. The other of the third and fourth transistor groups receives an inverted second clock signal. At least one of the first to fourth transistor groups includes a plurality of transistors connected in series.

The invention relates to the technical field of infrared optical materials, and particularly discloses an N-type chromium-doped high-resistance infrared silicon single crystal and a preparation method thereof. The N-type chromium-doped high-resistance infrared silicon single crystal is singly doped, the doping concentration of chromium oxide is 40-160ppm, and in the preparation process, specific constant-temperature heat treatment is carried out in a cooling stage. The concentration of free carriers in the silicon single crystal is remarkably reduced by singly doping chromium oxide and utilizing the deep energy level compensation effect of chromium element, the conduction type of the single crystal is N type, the resistivity is stably increased to above 1120ohm.cm, the average infrared transmittance of the wave band of 2-6 microns is greater than 53%, the stress birefringence is less than 3nm / cm, the process window is wide, and the operation is simple and convenient. The method is particularly suitable for preparing the silicon single crystal of a large-size and high-performance infrared optical system.

The utility model discloses a multilayer heat conduction type flexible circuit board, comprising a supporting seat, two ends of the supporting seat are provided with a plurality of first screws, the supporting seat is fixedly installed in an external equipment shell through the first screws, the upper end of the supporting seat is provided with a multilayer flexible circuit board, the multilayer flexible circuit board is placed on the supporting seat, and the supporting seat is provided with a plurality of second screws. The end, close to the supporting base, of the multi-layer flexible circuit board is a welding end, and the welding end of the multi-layer flexible circuit board is welded to an external hard circuit board. Outer edge thin film parts are fixed to the outer surfaces of the two sides of the multi-layer flexible circuit board, two sets of symmetrically-distributed fixing mechanisms are arranged at the upper end of the supporting base, and the outer edge thin film parts of the multi-layer flexible circuit board are fixed, so that external tension acts on the outer edge thin film parts; and external tension is prevented from directly acting on the welding part of the multi-layer flexible circuit board and the hard circuit board. The fragile welding position can be protected, and the situation that the welding position between the multi-layer flexible circuit board and the circuit board hard board is broken is reduced.

The invention discloses a semiconductor device and a manufacturing method thereof, a power module, a power conversion circuit and a vehicle. The manufacturing method comprises the following steps: providing a semiconductor body which comprises a first surface and a second surface which are oppositely arranged; a well region and a first region are formed on the semiconductor body, the first region is located on the first surface, and the well region is located on one side of the first region away from the first surface; forming a gate trench on the first surface; performing primary ion implantation on the semiconductor body to form a third sub-region, and then performing secondary ion implantation to form a second region; the second region and the third sub-region are located at the bottom of the gate trench, the position of the second region is the same as the position of the third sub-region, and the implanted ion conduction type of the primary ion implantation is opposite to the implanted ion conduction type of the secondary ion implantation; and forming a grid electrode in the grid electrode groove. According to the embodiment of the invention, the voltage endurance capability of the gate oxide layer of the trench gate can be improved, and the reliability of the semiconductor device is improved.

The invention relates to the technical field of solar cells, and particularly discloses a solar cell piece, a cell assembly and a photovoltaic system.The cell piece comprises a substrate, the back face of the substrate comprises first areas, second areas and connecting areas, and the first areas and the second areas are alternately arranged; the connecting area is at least partially arranged between the adjacent first area and second area and is respectively connected with the first area and the second area; the doped layer comprises a first doped layer and a second doped layer which are opposite in conduction type, the first doped layer is at least partially arranged in the first region, the second doped layer is at least partially arranged in the second region, and the first doped layer and the second doped layer are conductively connected in the connecting region; the back surface is recessed along the direction close to the front surface to form the polyhedral structures, and the plurality of polyhedral structures are arranged on the first area, the second area and the connecting area. According to the invention, the cell can show better optical performance and electrical performance, and the conversion efficiency of the cell is effectively improved.

The application relates to the technical field of semiconductor devices, and provides a modulation type silicon carbide junction terminal extension structure, a preparation method and a semiconductor. The modulation type silicon carbide junction terminal extension structure comprises a semiconductor layer and a stepped junction terminal extension region arranged in the semiconductor layer. The stepped junction terminal extension region comprises at least two steps arranged in turn from one side close to an active region to an outer side direction of a terminal region. The thickness of the steps gradually decreases, and the steps are connected through step surfaces between adjacent steps. At least one reverse doped region has semiconductor material of a first conduction type, is embedded in the stepped junction terminal extension region, forms a compensation structure in a vertical direction to a surface of the semiconductor layer and forms a compensation structure in a horizontal direction to the surface of the semiconductor layer. The application realizes two-dimensional regulation of an electric field and effectively smoothes the electric field distribution.

A solar cell element (1) is provided with a substrate (2), an oxide film (3), and a polysilicon layer (4). The substrate (2) has a first region (21) that is a region of a semiconductor of a first conductivity type. The oxide film (3) is in contact with the first region (21). The polysilicon layer (4) is in contact with the surface of the oxide film (3) on the opposite side from the first region (21). The polysilicon layer (4) contains a dopant. The polysilicon layer (4) includes a second region (41). The second region (41) is an oxide film-side region of the polycrystalline silicon layer (4) that is in contact with the oxide film (3). In a region from the second region (41) to the first region (21) via the oxide film (3), the distribution of the concentration of the dopant in the direction toward the substrate (2) from the surface of the polycrystalline silicon layer (4) on the opposite side from the substrate (2) has the largest first peak (Pk1) and second peak (Pk2). In the distribution of the concentration of the dopant, the second peak (Pk2) is positioned at a distance of 3 nm or more from the position at which the first peak (Pk1) is displayed in the direction from the first region (21) toward the second region (41) via the oxide film (3). The dopant is a dopant of a first conductivity type or a second conductivity type different from the first conductivity type.

The invention relates to the technical field of power supplies, in particular to an integrated power supply device which comprises a self-adjusting type vertical heat dissipation mechanism and a heat conduction type element combination mounting mechanism. The self-adjusting type vertical heat dissipation mechanism comprises a rectangular pyramid surface cylinder, and a four-edge vertical flow guide cylinder is vertically arranged at the upper end of the rectangular pyramid surface cylinder; the heat conduction type element combination installation mechanism comprises positioning installation columns vertically arranged on the four edges of the rectangular pyramid face cylinder, and a plurality of right-angle element installation covers are arranged above the four edges of the rectangular pyramid face cylinder. Through combination of passive diversion and pressure feedback active adjustment based on a phase change medium, dynamic matching of heat dissipation efficiency and power load is realized, and heat dissipation capability and operation reliability are significantly improved. Due to the unique three-dimensional modular layout, vertical multi-layer stacking of elements is achieved through the positioning installation columns and the right-angle element installation covers, the structure is compact, and maintenance is convenient; an efficient heat conduction channel from the elements to the heat dissipation core is built in the device, and it is ensured that heat is rapidly conducted out.

The utility model discloses a semiconductor device, a power module, a power conversion circuit and a vehicle, the semiconductor device comprises a semiconductor body, the semiconductor body comprises a first surface and a second surface which are oppositely arranged, the semiconductor body also comprises a plurality of first areas and a plurality of second areas, the first areas and the second areas are arranged on the first surface, and the first areas and the second areas are arranged on the second surface; the second regions extend into the semiconductor body and are located between the adjacent first regions; the semiconductor structure layer is located on the first surface, and the orthographic projection of the semiconductor structure layer on the first surface at least covers the orthographic projection of the second area on the first surface; the semiconductor structure layer and the second region have the same conduction type; the first metal layer is located on one side, away from the first surface, of the semiconductor structure layer; and the second metal layer is located on the second surface, so that the forward on resistance of the device is reduced, the leakage current of the device is further reduced, and the performance and the stability of the semiconductor device are improved.

According to the thermoplastic composite molding equipment and the production line provided by the utility model, electrode conduction type heating and composite self-resistance heating are organically combined, and a mode of independently using a mold temperature controller or self-resistance heating in the prior art is replaced, so that the problem that the heating efficiency and the temperature uniformity are difficult to consider at the same time is fundamentally solved; and the accuracy of temperature control over materials such as carbon fibers in the mold pressing process can be remarkably improved. On the basis, welding and hot stamping procedures before and after die pressing are further designed and integrated, a corresponding production line is designed, efficient and accurate machining of thermoplastic composite products can be achieved, and the device and production cost is low.

The invention discloses a back contact passivation solar cell and a preparation method thereof, and relates to the technical field of solar cell manufacturing, and the back contact passivation solar cell comprises a silicon substrate; a first carrier collection layer, a first conductive thin film layer and a second conductive thin film layer which are stacked from inside to outside are arranged in a first area of the first main surface of the silicon substrate; a second carrier collection layer and a third conductive film layer which are laminated from inside to outside in a second region of the first main surface of the silicon substrate; wherein a spacer region is arranged between the first region and the second region, and the conduction type of the first carrier collection layer is opposite to that of the second carrier collection layer; wherein the first carrier collection layer, the first conductive thin film layer and the second conductive thin film layer extend from the first region to the interval region, the third conductive thin film layer extends from the second region to the interval region, and the second conductive thin film layer and the third conductive thin film layer are not connected. According to the embodiment, carriers in the interval region can be effectively exported.

The invention discloses a Micro-LED chip based on a passivation layer and a side wall metal layer and a preparation method, the Micro-LED chip comprises an LED structure and an electrode structure which are arranged on a substrate, and a first passivation layer and a dielectric layer which are sequentially arranged on the surface of the LED structure, and one side of the dielectric layer is provided with a metal layer; the LED structure sequentially comprises a first semiconductor layer, a light-emitting layer and a second semiconductor layer, and the first semiconductor layer and the second semiconductor layer are opposite in conduction type. According to the invention, low interface trap density and fixed charge density are realized through the first passivation layer on the surface of the LED structure, the non-radiative recombination of side wall carriers is significantly reduced, and the EQE of the Micro-LED chip is improved; forward bias voltage is applied through the dielectric layer / metal layer side wall structure, the energy difference between a surface defect state and an electron energy state is reduced, surface non-radiative recombination is reduced, EQE is improved, and the method is suitable for low-current-density operation.

The utility model discloses a heating panel mounting seat and an infrared heating plate, and relates to the field of infrared heating source equipment, the heating panel mounting seat comprises a base, the base is provided with an accommodating groove, the accommodating groove is provided with a conductive device mounting position and a temperature measuring device mounting position, a conductive device is arranged in the conductive device mounting position, the conductive device is provided with a power supply end and a wiring end, and the temperature measuring device mounting position is provided with a temperature measuring device. The power supply end is located in the containing groove and faces a groove opening of the containing groove, the temperature measuring device is arranged in the temperature measuring device installation position, the temperature measuring device is provided with a temperature measuring end, the temperature measuring end is located in the containing groove and faces the groove opening of the containing groove, the infrared heating plate heating panel and the heating panel installation base are arranged, and the heating panel is fixed in the containing groove in an adhesive mode. The electrode of the heating panel is in contact with the power supply end of the conductive device, and the heating panel is in contact with the temperature measuring end of the temperature measuring device. The heating panel can be installed without opening holes, stable power supply of the heating panel is guaranteed, the temperature measuring device can be in direct contact with the heating panel to achieve heat conduction type temperature measurement, and the temperature measuring result is visual and accurate.

The utility model discloses a high-performance conduction type automatic welding solder tip which comprises an electric soldering iron body and a lantern ring, the lantern ring is arranged on the side wall of the electric soldering iron body in a sleeved mode, two fixing plates are fixedly connected to the side wall of the lantern ring, a connecting cylinder is arranged between the two fixing plates, a first motor is installed on the side wall of one fixing plate, and a second motor is installed on the side wall of the other fixing plate. A first motor is arranged on the electric soldering iron body, an output shaft of the first motor is fixedly connected with a connecting cylinder, a movable rod is arranged in the connecting cylinder, a locking assembly is arranged on the side wall of the connecting cylinder, the bottom end of the movable rod is movably connected with a mounting plate, and the mounting plate is in a U shape. The angle of the cleaning brush is controlled through the first motor, rotation of the cleaning brush is controlled through the second motor, and therefore rapid cleaning of the solder tip is achieved.

This application relates to a high-frequency carrier electromagnetic protection system, method, and electronic device for power energy storage. The system includes: a high-frequency carrier detection module for acquiring high-frequency carrier digital signals; an interference suppression control module that uses an interference signal identification algorithm to obtain the interference type and intensity level of the interference signal, and uses a filtering parameter optimization algorithm to obtain the optimal filtering parameters based on the interference type and intensity level, and obtains a shielding status monitoring command through a shielding status linkage algorithm; an adaptive filtering module that controls the on / off or combination of capacitor arrays and inductor arrays according to the optimal filtering parameters to filter out conducted interference signals; and a multi-layer shielding module that responds to the shielding status monitoring command to filter out radiated interference signals. This solves the problems of insufficient protection targeting, single protection level, and poor compatibility in electromagnetic protection technologies, achieving precise and efficient protection against high-frequency carrier electromagnetic interference, while ensuring the operating efficiency and stability of the power energy storage system.