Semiconductor device and method of fabricating the same

Abstract

A semiconductor device includes a semiconductor substrate of a first conduction type, a first well of a second conduction type formed on the semiconductor substrate, a plurality of second wells of the first conduction type provided in the first well for forming memory cells and a peripheral circuit respectively, each second well having a first depth, a first trench isolating region formed so as to isolate an element within the second well for the memory cells and having a first depth, a guard-ring diffusion region of the first conduction type provided in the vicinity of a peripheral edge of each second well for the memory cells and doped with a high density impurity so as to encompass a forming region of the memory cells, a second trench isolating region formed so that a p-n junction of each second well terminates on a bottom thereof in the vicinity of an outside of the guard-ring diffusion region, the second trench isolating region having a second depth larger than the first depth of each second well, and a third trench isolating region isolating an element formed in each second well for the peripheral circuit, the third trench isolating region having the second depth.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS [0001] This application claims priority to Japanese patent application No. 2003-376816, the content of which is incorporated hereinto by reference.BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] The present invention relates to a semiconductor device employing a shallow trench isolation structure (STI) as an element isolating structure and a method of fabricating the semiconductor device. [0004] 2. Description of the Related Art [0005] A technique of isolating elements has recently been changing from local oxidation of silicon (LOCOS) to shallow trench isolation (STI) for the purposes of high integration and miniaturization in the fabrication process of semiconductor memory devices. In the element isolation technique employing STI, shallow trenches are formed and filled with an isolator so as to be flattened, whereupon a trench isolating region is provided. [0006] Furthermore, in the element isolating technique employing ST...

AI Technical Summary

Benefits of technology

[0020] Therefore, an object of the present invention is to provide a semiconductor device in which an increase in the chip area and occurrence of dishing or the like can be prevented although trench isolating regions with different depths are formed and a method of fabricating such a semiconductor device.

Problems solved by technology

However, either method requires a large width of trench isolating region in order that a large element isolation width may be ensured or a stopper region may be formed, resulting in a problem that an area for the element isolation is increased.

However, the STI technique forming a trench isolating region with a depth in accordance with the withstand pressure results in the following new problem: a non-volatile memory generally comprises a memory cell and a peripheral circuit.

Consequently, there is a definite limit in the reduction in the size of the semiconductor memory device.

In such a case as described above, there is a possibility that the CMP process, when carried out, may cause dishing in the trench isolating region 12 formed in the boundary region 4 between the high withstand pressure circuit region 3 and the memory cell region 2, resulting in a problem of abnormal shape.

However, the number of dummy patterns needs to be increased with increase in the degree of dishing, whereupon a new problem arises that an area of the cell (or chip size) should be increased.

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