7 results about "LOCOS" patented technology

A local oxidation of silicon (LOCOS) in a region 30 of SOI substrate 4 partially oxidises 34 the silicon first epitaxial layer 10. Etching the SOI substrate 4 in region 30 creates a trench 16 through

A method of creating a vertical semiconductor device, the method includes the steps of performing a LOCal Oxidation of Silicon, LOCOS, process in a vertical trench of a semiconductor material so that oxide material is formed inside the vertical trench, and ledges are formed by the oxide material, inside the vertical trench, as a result of the LOCOS process, so that a lower region of reduced lateral distance is formed between the oxide material, at a base of the trench, depositing the trench with polysilicon and etching the polysilicon downward up to the oxide material using interferometric end point detection, so that polysilicon remains in the lower region.

An integrated circuit includes a source region and a drain region spaced apart and extending into a semiconductor layer. A gate electrode extends between the source and the drain regions, and a dielectric layer is between the gate electrode and the semiconductor layer. The dielectric layer includes a first portion having a first thickness and a second portion having a second greater second thickness and a lateral perimeter surrounding the source region. The lateral perimeter includes a first edge having a first linear segment extending between the source region and the drain region along a first direction and a second edge having a second linear segment extending over the semiconductor layer along a different second direction. A fillet of the second portion connects the first linear segment and the second linear segment of the lateral perimeter. .

Semiconductor devices and fabrication methods thereof are described. For example, a semiconductor device includes a source region and a drain region spaced apart in a semiconductor layer, a gate dielectric layer on a top surface of the semiconductor layer and extending from the source region toward the drain region, and a field relief dielectric structure over the semiconductor layer and extending from the gate dielectric layer toward the drain region. The field relief dielectric structure includes a dielectric layer and a local oxidation of silicon (LOCOS) layer between the dielectric layer and the semiconductor layer, the LOCOS layer extending below the top surface of the semiconductor layer by no more than 10 nanometers.

Semiconductor devices including high-k field mitigation dielectric structures (122) are described. A microelectronic device (100) comprises: a substrate (103) comprising a body region (108) and a drain drift region (145) on the substrate (103); a gate dielectric layer (152) extending over the body region (108) and the drift region (145); a field relief trench (115) formed by removing the silicon dioxide layer from the LOCOS silicon region; a high-k field mitigation dielectric structure (122) laterally abutting the gate dielectric layer (152) at a location in the drift region (145); and a gate electrode (158) on the gate dielectric layer (152) and the field mitigation dielectric layer. A field relief trench (115) formed in the trench left after removal of silicon dioxide in the LOCOS region provides improved trench depth uniformity.

Semiconductor devices and fabrication methods thereof are described. For example, a semiconductor device (100) includes a source region (130) and a drain region (118) spaced apart in a semiconductor layer (104), a gate dielectric layer (120) on a top surface of the semiconductor layer (104) and extending from the source region (130) toward the drain region (118), and a field relief dielectric structure over the semiconductor layer (104) and extending from the gate dielectric layer (120) toward the drain region (118). The field relief dielectric structure includes a dielectric layer (124) and a local oxidation of silicon (LOCOS) layer (122) between the dielectric layer (124) and the semiconductor layer (104), the LOCOS layer (122) extending below the top surface of the semiconductor layer (104) by no more than 10 nanometers.

Planar field-effect transistor (100) which features: a drain extension area (102) between a channel area (104) and a drain connection (D) on a first surface (106) of a semiconductor body (112); a first electrode part (108) and a second electrode part (110) which are laterally spaced apart from each other, wherein the first electrode part (108) is arranged as a gate electrode above the channel area (104) and the second electrode part (110) is arranged above the drain expansion area (102) and is electrically separated from the first electrode part (108); a gate dielectric (1141) between the first electrode part (108) and the channel region (104); and a further dielectric (1142) between the first electrode part (108) and the drain expansion region (102), wherein the thickness of the further dielectric (1142) is greater than the thickness of the gate dielectric (1141) and the gate dielectric (1141) borders the further dielectric in the direction of the drain terminal (D), and wherein the further dielectric (1142) comprises a first dielectric, as well as a planar dielectric (1147) between the first dielectric and the gate dielectric (1141), wherein the planar dielectric (1147) is thicker than the gate dielectric (1141) and borders a top surface (106) of a part of the drain expansion region (102), and the first dielectric is a LOCOS dielectric or a beveled dielectric, and the further dielectric (1142) is located under the second electrode part (110) is thicker than the planar dielectric (1147) under the first electrode part (108).