26 results about "LOCOS" patented technology

The invention relates to the technical field of semiconductors, in particular to a VDMOS semiconductor power device and a preparation method thereof, and the VDMOS semiconductor power device comprises a semiconductor substrate and a semiconductor epitaxial layer. The well region is positioned in the semiconductor epitaxial layer; the source region is positioned in the well region; the local thick oxygen layer is positioned below the grid electrode between the adjacent well regions on the semiconductor epitaxial layer; the gate dielectric layer is positioned below the gate between the adjacent source regions on the semiconductor epitaxial layer; the grid electrode is positioned above the grid dielectric layer and the local thick oxygen layer; wherein the local thick oxygen layer is formed before diffusion of the well region. The VDMOS semiconductor power device adopts a gate-last oxide process and is provided with a local thick oxygen layer structure, and the local thick oxygen layer structure is formed before well region diffusion, so that the LOCOS boron absorption and phosphorus discharge effect is effectively avoided, and the reliability and the electrical property of the device are improved.

The invention provides an LDMOS (Laterally Diffused Metal Oxide Semiconductor) drift region LOCOS growth method. The LDMOS drift region LOCOS growth method comprises the following steps: providing a silicon substrate; defining an LOCOS region on the surface of the silicon substrate, wherein the region except the LOCOS region in the silicon substrate is a non-LOCOS region; surface modification is carried out on the silicon substrate in the LOCOS area, a lattice damage area is formed in the LOCOS area, and the area outside the lattice damage area in the silicon substrate is a non-lattice damage area; the oxide growing on the surface of the silicon substrate is consumed through a furnace tube, and the growth rate of the oxide in the lattice damage area is larger than that of the oxide in the non-lattice damage area; the oxide is etched, the oxide in the non-LOCOS area is removed, and the remaining oxide in the LOCOS area serves as LOCOS. According to the technical scheme, the LOCOS is generated through the difference formed by the silicon substrate by utilizing the characteristics that crystal lattices are damaged after the ions are injected into the silicon substrate and the speed of generating oxides during high-temperature oxidation is higher than that of generating oxides during high-temperature oxidation of the silicon substrate, and compared with a traditional mode, the proportion of beaks is reduced, so that the size of the device is reduced.

Semiconductor devices including a high-k field relief dielectric structure are described. The microelectronic device comprises a substrate including a body region and a drain drift region on the substrate, a gate dielectric layer extending over the body region and the drift region, a drain drift trench is formed by removal of silicon dioxide from a LOCOS silicon region, a high-k field relief dielectric structure laterally abutting the gate dielectric layer at a location in the drift region, and a gate electrode on the gate dielectric layer and the field relief dielectric layer. Increasing the dielectric constant of the field relief dielectric structure may improve channel hot carrier performance, improve breakdown voltage, and reduce the specific on resistance. A drain drift trench formed in a trench left after removal of silicon dioxide in a LOCOS region provides improved trench depth uniformity.

The invention provides a layout of a power device, the power device and a forming method of the power device, a plurality of redundant active regions are arranged in an insulation region outside an active region in a substrate of the layout of the power device, and a pattern of the layout of the power device is transferred to the substrate in the forming method of the power device; then executing an LOCOS process so as to form a field oxide layer in the redundant active region and an insulating region outside the active region; and performing a chemical mechanical polishing process to flatten the top surface of the field oxide layer. Because the area of the insulation region in the high-voltage power device is large, a plurality of redundant active regions are arranged in the insulation region, namely, the large-area insulation region is divided into a plurality of small-area insulation regions, and field oxide layers are not formed on the surfaces of the active regions and the redundant active regions in the LOCOS process, the field oxide layers are not formed on the surfaces of the active regions and the redundant active regions in the chemical mechanical grinding process, and the field oxide layers are not formed on the surfaces of the active regions and the redundant active regions. The difficulty of the chemical mechanical grinding process is reduced, and the thickness uniformity of the chemical mechanical grinding process of the field oxide layer is improved.

A local oxidation of silicon (LOCOS) in a region 30 of SOI substrate 4 partially oxidises 34 the silicon first epitaxial layer 10. Etching the SOI substrate 4 in region 30 creates a trench 16 through

A semiconductor device includes an active region, a LOCOS region formed within the active region and that extends vertically above a top surface of the active region, a gate region formed above the top surface of the active region, and a polysilicon resistor having a bottom surface that is offset vertically and physically isolated from a top surface of the LOCOS region. The active region includes a source region laterally disposed from the gate region, a drain region laterally disposed from the gate region, and a drift region laterally disposed between the gate region and the drain region. The polysilicon resistor is formed above the drift region. The active region further includes a first charge balance region formed in the active region below the drift region.

Described examples include a method having steps of forming an isolation pad oxide layer on a substrate and forming and patterning a silicon nitride layer on the isolation pad oxide layer. The method also has steps of oxidizing portions of the substrate not covered by the silicon nitride layer to form a LOCOS layer and oxidizing the silicon nitride layer in an oxidizing ambient containing a chlorine source to form a silicon dioxide layer.

A method of fabricating an integrated circuit includes forming a first opening having a first width and a second opening having a second width in a first dielectric layer over a silicon substrate. The openings expose the silicon substrate and the exposed silicon substrate is oxidized to form first and second LOCOS structures having a first thickness. A polysilicon layer is formed over the silicon substrate, so that the polysilicon layer fills the first and second openings. A blanket etch of the polysilicon layer is performed to remove at least a portion of the polysilicon layer over the second LOCOS structure while leaving the first LOCOS structure protected by the polysilicon layer. The silicon substrate under the second LOCOS structure is further oxidized such that the second LOCOS structure has a second thickness greater than the first thickness.

An integrated circuit includes a source region and a drain region spaced apart and extending into a semiconductor layer. A gate electrode extends between the source and the drain regions, and a dielectric layer is between the gate electrode and the semiconductor layer. The dielectric layer includes a first portion having a first thickness and a second portion having a second greater second thickness and a lateral perimeter surrounding the source region. The lateral perimeter includes a first edge having a first linear segment extending between the source region and the drain region along a first direction and a second edge having a second linear segment extending over the semiconductor layer along a different second direction. A fillet of the second portion connects the first linear segment and the second linear segment of the lateral perimeter.

A method of creating a vertical semiconductor device, the method includes the steps of performing a LOCal Oxidation of Silicon, LOCOS, process in a vertical trench of a semiconductor material so that oxide material is formed inside the vertical trench, and ledges are formed by the oxide material, inside the vertical trench, as a result of the LOCOS process, so that a lower region of reduced lateral distance is formed between the oxide material, at a base of the trench, depositing the trench with polysilicon and etching the polysilicon downward up to the oxide material using interferometric end point detection, so that polysilicon remains in the lower region.

An integrated circuit includes a source region and a drain region spaced apart and extending into a semiconductor layer. A gate electrode extends between the source and the drain regions, and a dielectric layer is between the gate electrode and the semiconductor layer. The dielectric layer includes a first portion having a first thickness and a second portion having a second greater second thickness and a lateral perimeter surrounding the source region. The lateral perimeter includes a first edge having a first linear segment extending between the source region and the drain region along a first direction and a second edge having a second linear segment extending over the semiconductor layer along a different second direction. A fillet of the second portion connects the first linear segment and the second linear segment of the lateral perimeter. .

A method of manufacturing an electronic device includes forming a shallow trench isolation (STI) structure on or in a semiconductor surface layer and forming a mask on the semiconductor surface layer, where the mask exposes a surface of a dielectric material of the STI structure and a prospective local oxidation of silicon (LOCOS) portion of a surface of the semiconductor surface layer. The method also includes performing an oxidation process using the mask to oxidize silicon in an indent in the dielectric material of the STI structure and to grow an oxide material on the exposed LOCOS portion of the surface of the semiconductor surface layer.

An integrated circuit includes a gate electrode over a silicon substrate and a local oxidation of silicon (LOCOS) structure between the gate electrode and the silicon substrate. The LOCOS structure has bird's beak portions, peripheral portions between the bird's beak portions, and a central portion between the peripheral portions. The peripheral portions have a first thickness, and the central portion has a greater second thickness.

The present invention relates to a layout correction method for an active region photomask and a manufacturing method for semiconductor components. The correction method includes: the active region photomask is used to manufacture semiconductor components adopting a local oxidation of silicon (LOCOS) isolation process. By adding OPC correction patterns to three sides of the active region pattern end that are in contact with the LOCOS region, the bird's beak deformation of the silicon local oxidation isolation structure in the semiconductor components manufactured using the active region photomask becomes negligible at the active region end position; wherein the active region end is used to set through holes or contact holes. The present invention improves the topography at the junction of the active region end and the LOCOS region through special OPC, avoids the active region being eroded by the bird's beak, enables the active region end to achieve good electrical contact with the through hole / contact hole with a smaller area, and finally achieves the purpose of effectively applying the LOCOS process to products with smaller line widths.

Semiconductor devices and fabrication methods thereof are described. For example, a semiconductor device includes a source region and a drain region spaced apart in a semiconductor layer, a gate dielectric layer on a top surface of the semiconductor layer and extending from the source region toward the drain region, and a field relief dielectric structure over the semiconductor layer and extending from the gate dielectric layer toward the drain region. The field relief dielectric structure includes a dielectric layer and a local oxidation of silicon (LOCOS) layer between the dielectric layer and the semiconductor layer, the LOCOS layer extending below the top surface of the semiconductor layer by no more than 10 nanometers.

An integrated circuit (IC) (100) comprises a first capacitor (150a), a second capacitor (150b) and a functional circuit (180) configured together with the capacitors for implementing at least one circuit function in a semiconductor surface layer (106) on a substrate (102). The capacitor comprises a top plate (112) on a local oxidation of silicon (LOCOS) oxide (110a, 110b), wherein the thickness of the LOCOS oxide for the second capacitor is thicker than the thickness of the LOCOS oxide for the first capacitor. There are contacts (122a) for the top plate and contacts (122b) for the bottom plate for the first and second capacitors.

The VDMOS comprises a first conductive layer, an N + substrate layer, an N-epitaxial layer and a source gate structure which are sequentially stacked from bottom to top, and further comprises two first P-body regions which are symmetrically arranged at the top of the N-epitaxial layer, and first NSD regions are embedded in the top surfaces of the first P-body regions; the groove structure is arranged in the middle of the top of the N-epitaxial layer, and the two first P-body regions are arranged on the two sides of the groove structure; the trench structure includes a second P-body region, a second NSD region, and a LOCOS oxide layer. According to the invention, the channel of a common VDMOS is not changed and is ensured to participate in the forward conduction process, so that the channel density is not reduced, and the current capability and the conduction resistance of the device are not deteriorated; during reverse conduction, the source electrode and the grid electrode of the channel diode are in short circuit, current flows to the drain electrode from the source electrode of the VDMOS through the opened channel diode, minority carrier injection caused by conduction of the body diode is reduced, reverse recovery charge and reverse recovery time are reduced, and the reverse recovery performance of the device is optimized.

Semiconductor devices including high-k field mitigation dielectric structures (122) are described. A microelectronic device (100) comprises: a substrate (103) comprising a body region (108) and a drain drift region (145) on the substrate (103); a gate dielectric layer (152) extending over the body region (108) and the drift region (145); a field relief trench (115) formed by removing the silicon dioxide layer from the LOCOS silicon region; a high-k field mitigation dielectric structure (122) laterally abutting the gate dielectric layer (152) at a location in the drift region (145); and a gate electrode (158) on the gate dielectric layer (152) and the field mitigation dielectric layer. A field relief trench (115) formed in the trench left after removal of silicon dioxide in the LOCOS region provides improved trench depth uniformity.

Semiconductor devices including a high-k field relief dielectric structure (122) are described. The microelectronic device (100) comprises a substrate (103) including a body region (108) and a drain drift region (145) on the substrate (103), a gate dielectric layer (152) extending over the body region (108) and the drift region (145), a field relief trench (115) is formed by removal of a silicon dioxide layer from a LOCOS silicon region, a high- k field relief dielectric structure (122) laterally abutting the gate dielectric layer (152) at a location in the drift region (145), and a gate electrode (158) on the gate dielectric layer (152) and the field relief dielectric layer. A field relief trench (115) formed in a trench left after removal of silicon dioxide in a LOCOS region provides improved trench depth uniformity.

The present invention relates to the field of semiconductors and provides a fully isolated lateral double diffused semiconductor device and a manufacturing method. The fully isolated lateral double diffused semiconductor device includes a semiconductor substrate, a source body region, a drain drift region, a source, a drain, and a gate, and also includes: a first buried layer of the first type, a second buried layer, and a field oxygen isolation combination structure; the field oxygen isolation combination structure includes a shallow trench isolation structure and two LOCOS bird's beak structures that cover the wall corners on both sides of the shallow trench isolation structure; the drain drift region is connected to the first buried layer of the first type in the vertical direction, and the source body regions located on both sides of the drain drift region are connected to the first buried layer of the first type in the vertical direction to form a first isolation ring structure. The present invention adopts a field oxygen isolation combination structure that combines LOCOS and STI to improve the breakdown voltage of the device; the drain drift region is fully isolated by the first isolation ring structure to form a lateral conduction path and a vertical conduction path, thereby reducing the on-resistance and improving reliability.

Semiconductor devices and fabrication methods thereof are described. For example, a semiconductor device (100) includes a source region (130) and a drain region (118) spaced apart in a semiconductor layer (104), a gate dielectric layer (120) on a top surface of the semiconductor layer (104) and extending from the source region (130) toward the drain region (118), and a field relief dielectric structure over the semiconductor layer (104) and extending from the gate dielectric layer (120) toward the drain region (118). The field relief dielectric structure includes a dielectric layer (124) and a local oxidation of silicon (LOCOS) layer (122) between the dielectric layer (124) and the semiconductor layer (104), the LOCOS layer (122) extending below the top surface of the semiconductor layer (104) by no more than 10 nanometers.

Planar field-effect transistor (100) which features: a drain extension area (102) between a channel area (104) and a drain connection (D) on a first surface (106) of a semiconductor body (112); a first electrode part (108) and a second electrode part (110) which are laterally spaced apart from each other, wherein the first electrode part (108) is arranged as a gate electrode above the channel area (104) and the second electrode part (110) is arranged above the drain expansion area (102) and is electrically separated from the first electrode part (108); a gate dielectric (1141) between the first electrode part (108) and the channel region (104); and a further dielectric (1142) between the first electrode part (108) and the drain expansion region (102), wherein the thickness of the further dielectric (1142) is greater than the thickness of the gate dielectric (1141) and the gate dielectric (1141) borders the further dielectric in the direction of the drain terminal (D), and wherein the further dielectric (1142) comprises a first dielectric, as well as a planar dielectric (1147) between the first dielectric and the gate dielectric (1141), wherein the planar dielectric (1147) is thicker than the gate dielectric (1141) and borders a top surface (106) of a part of the drain expansion region (102), and the first dielectric is a LOCOS dielectric or a beveled dielectric, and the further dielectric (1142) is located under the second electrode part (110) is thicker than the planar dielectric (1147) under the first electrode part (108).

The present invention provides a semiconductor structure and a manufacturing method thereof, which are applied to the field of semiconductor technology. Specifically, in the manufacturing method provided by the present invention, by increasing the etching time of the active region, the depth of the local oxidation of silicon (LOCOS) isolation structure in the semiconductor substrate is deepened. Therefore, when forming the trench for forming the LOCOS structure, a certain silicon loss of the semiconductor substrate will occur. Thus, the obtained LOCOS structure can have a greater depth, and it is required that the formed LOCOS depth is greater than the junction depth of N+ and P+ of the NPN, and at the same time, the impact on the manufacturing process of the NPN device structure is small. That is, without increasing the production cost, the problem of unstable beta parameter of the NPN device structure caused by metal plug etching fluctuations can be avoided.

The invention discloses a VLD terminal structure, a preparation method and a preparation system thereof, and a storage medium. The terminal structure comprises a substrate; a VLD terminal ring region is formed downwards from the surface of the substrate; the first groove region is formed in the front part of the VLD terminal ring region, and the first LOCOS oxide layer grows in the first groove region; the second trench region is formed in the rear part of the VLD terminal ring region, and the second LOCOS oxide layer grows in the second trench region; the first groove region is adjacent to the second groove region, and the depth of the first groove region is greater than that of the second groove region. The VLD terminal structure with high reliability is formed through twice mask photoetching, LOCOS growth and CMP removal, two oxide layer steps are realized, boron ion implantation and annealing in a terminal region are matched, the boron ion implantation dosage can be further improved on the premise of being not affected by movable ion charges of a process production line, the process is simple and reliable, and the implementation difficulty is low.

Disclosed are a power semiconductor device having a withstand voltage region of a VLD structure, and a method for manufacturing same. The method for manufacturing a power semiconductor device comprises the steps of: deforming an oxide film formed on the top of a first conductive semiconductor substrate into an alternately thick and thin oxide film by using a LOCOS process in a withstand voltage holding region of a power semiconductor device; injecting a second conductive impurity into the semiconductor substrate from the top of the deformed oxide film toward the withstand voltage holding region by using the same concentration of the second conductive impurity and the same injection energy; and diffusing the second conductivity type impurity injected into the semiconductor substrate through the deformed oxide film, thereby forming an inclined doping region of a VLD structure.

A method of manufacturing an electronic device includes forming a shallow trench isolation (STI) structure on or in a semiconductor surface layer and forming a mask on the semiconductor surface layer, where the mask exposes a surface of a dielectric material of the STI structure and a prospective local oxidation of silicon (LOCOS) portion of a surface of the semiconductor surface layer. The method also includes performing an oxidation process using the mask to oxidize silicon in an indent in the dielectric material of the STI structure and to grow an oxide material on the exposed LOCOS portion of the surface of the semiconductor surface layer.