Method for manufacturing high-voltage lateral dual-diffusion N-channel metal oxide semiconductor (NMOS) based on standard complementary metal-oxide-semiconductor transistor (CMOS) process

Abstract

The invention provides a method for manufacturing a high-voltage lateral dual-diffusion N-channel metal oxide semiconductor (NMOS) based on a standard complementary metal-oxide-semiconductor transistor (CMOS) process. The method comprises the following steps of: providing a P type silicon substrate, manufacturing local oxidation of silicon (LOCOS) on the P type silicon substrate, and dividing theLOCOS into a low-voltage CMOS area and a high-voltage lateral diffused N-channel metal oxide semiconductor (LDNMOS) area; injecting phosphor into the LDNMOS area and diffusing the phosphor to form a high-voltage N well; performing a two-well process in the CMOS area to form a low-voltage N well and a low-voltage P well; sequentially forming a thick gate oxide layer and a thin gate oxide layer in the LDNMOS area; sequentially forming a polysilicon layer and a silicon nitride layer and sequentially etching the polysilicon layer and the silicon nitride layer to form a grid electrode and a buffering layer respectively; coating a photoresist, and exposing the injection position of a P type area of the LDNMOS area after exposing and development; injecting P type ions for two times at the anglesof more than 30 degrees and less than 7 degrees respectively to form channels of an LDNMOS, wherein the photoresist and the buffering layer serve as masks; and forming source areas and drain areas ofa P-channel metal oxide semiconductor (PMOS) and an NMOS, and contact ends of a source area, a drain area and a P type area of the LDNMOS by taking the grid electrode as an alignment mark. Because a large-angle injection process is used for forming the channels after the grid electrode is formed, a long-time high-temperature heating process is not required and the process is compatible.

Description

technical field [0001] The present invention relates to the technical field of semiconductor manufacturing, in particular, the present invention relates to a high-voltage lateral double-diffused NMOS (Lateral Double Diffused NMOS, LDNMOS for short) manufacturing method based on a standard CMOS process. Background technique [0002] High-voltage MOSFET drive devices and their modules (12V~30V LDNMOS, DDDMOS, DECMOS, etc.) are widely used in LED backlight drive, motor drive, and chip control, and are a hot research field in recent years. [0003] Among them, a power device with a lateral diffusion structure (Lateral Diffused MOSFET, LDMOS for short) is one of the most popular devices. The traditional high lateral double-diffusion NMOS (LDNMOS) uses the principle of simultaneous implantation of boron (P) and arsenic (As) ions, and the principle that boron diffuses faster than arsenic in the high-temperature and long-term thermal process to form a fixed-length self-aligned P-ty...

AI Technical Summary

Problems solved by technology

Compared with traditional high-voltage MOSFET devices such as DECMOS, the power device of this lateral diffusion structure can obtain a shorter self-aligned channel size to reduce the requirement of photolithography alignment level, and because the channel has a higher concentration gradient , to prevent the occurrence of punch-through and improve the driving capability, but the biggest disadvantage of traditional LDNMOS is that its manufacturing process is difficult to integrate with the manufacturing process of control circuit CMOS

[0004] In addition, with the rapid development of CMOS integrated circuit manufacturing technology, the long-term high-temperature thermal process (Thermal Budget) necessary to form the channel of high-voltage LDMOS devices will have a particularly prominent impact on the compatibility of high-voltage LDMOS devices and low-voltage CMOS devices. However, the existing technology is still not well compatible with the two processes.

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