294 results about "Cmos process" patented technology

The invention relates to the technical field of monolithic integration, in particular to a monolithic three-dimensional integration implementation method and device for a hybrid precision in-memory computing architecture, and the method comprises the steps: obtaining a silicon-based CMOS technology and a subsequent integration technology in a monolithic three-dimensional integration technology; manufacturing a control logic circuit on the computing architecture in the mixed precision memory by adopting a silicon-based CMOS (Complementary Metal Oxide Semiconductor) process; a plurality of functional layers are vertically stacked on a logic circuit by adopting a back-end integration process, communication among the functional layers is realized through interlayer dielectric via holes in the vertical direction, an analog in-memory array, a digital in-memory array and a cache are arranged on the functional layers, the analog in-memory array realizes matrix and vector multiplication with fixed weight, and the digital in-memory array realizes matrix and vector multiplication with fixed weight. And the array in the digital memory realizes matrix multiplication of refresh weight. Therefore, the problems that an in-memory computing architecture usually needs to occupy a relatively large part of chip area, the computing efficiency is relatively low and the like in related technologies are solved.

The invention discloses a diamond MOSFET device compatible with a CMOS ohmic contact process and a preparation method of the diamond MOSFET device. The preparation method comprises the steps that S1, a diamond substrate is selected, and an intrinsic diamond layer is grown on the diamond substrate in a homoepitaxial mode; s2, preparing a mask, and forming a boron-doped diamond layer in a source region and a drain region on the intrinsic diamond layer through boron ion implantation; s3, depositing a layer of Si film and a layer of Ti film on the surface of the sample; s4, performing two-step annealing on the sample to obtain ohmic contact formed by the boron-doped diamond layer, the boron-doped silicon layer and the titanium silicide layer; s5, removing the mask and the thin film above the mask; s6, preparing a terminal diamond surface layer; s7, preparing a passivation layer and windowing to form a source window and a drain window; and S8, preparing a gate electrode. According to the method, high-quality ohmic contact can be formed on the diamond through the gold-free process, the gold ion pollution risk is thoroughly avoided, and CMOS process compatibility is achieved.

The invention belongs to the field of microelectronics, and particularly relates to a preparation method and application of a ferroelectric diode based on a scandium-doped aluminum nitride thin film, and the ferroelectric diode is prepared through the following steps: S1, growing an adhesion layer on a substrate through magnetron sputtering; s2, growing a bottom electrode on the adhesion layer through magnetron sputtering; s3, growing a ferroelectric film on the bottom electrode through magnetron co-sputtering at room temperature; s4, coating photoresist on the ferroelectric film, and exposing and developing; s5, growing a top electrode on the exposed and developed ferroelectric film through magnetron sputtering; and S6, stripping to obtain the ferroelectric diode. Compared with the prior art, the method has the advantages that the problems of high preparation temperature of the Al1-xScxN layer and large thickness of the Al1-xScxN layer in the prior art are solved, the ferroelectric diode memory of the scandium-doped aluminum nitride film is prepared at room temperature for the first time, and compatibility with a CMOS (complementary metal oxide semiconductor) process is better realized.

The invention relates to a preparation method of a surface acoustic wave filter integrated with a CMOS (Complementary Metal Oxide Semiconductor) process, which comprises the following steps of: preparing a CMOS radio-frequency signal processing circuit by using a silicon or silicon carbide substrate, combining a dielectric buffer layer with a piezoelectric material, and then depositing a metal interdigital structure on the surface of the piezoelectric material to prepare the surface acoustic wave filter. A passivation layer is deposited on the surface of the filter to protect the filter structure, finally a metal interconnection line and the passivation layer are prepared above the filter, and in order to not affect the performance of the filter, an air cavity is prepared between the passivation layer and the metal interconnection layer of the filter, so that the passivation layer and the metal interconnection layer are effectively isolated. According to the preparation method, the surface acoustic wave filter and the CMOS radio frequency circuit can be integrated, the problem that radio frequency front-end and rear-end signal processing cannot be integrated at the same time at present is solved, and the preparation method plays an important role in promoting development of a radio frequency chip in the directions of high integration, low cost, miniaturization and the like; and the radio frequency chip has wide practical value and economic value in the radio frequency chip application field.

The present application provides an all-digital multi-phase DC-DC controller. The digital DC-DC controller includes time-based analog-to-digital converters (ADCs) for converting analog voltage signals into digital-domain signals so as to benefit from gate length scaling without limited by the low voltage swing. Also, the DC-DC controller further includes a digital control circuit and a time-based modulator. The digital control circuit can control the time-based modulator in a digital domain, thereby reducing the affection caused by process, voltage and temperature (PVT) variation. Also, the time-based modulator can adjust the timing of the PWM signals and avoid the performance degradation caused by circuit mismatch. Since the digital control circuit can be fully synthesizable, it allows implementations in all kinds of digital CMOS processes with a small chip area.

The invention provides a development method of a heterogeneous integrated PCB (Printed Circuit Board) device library based on a silicon-based CMOS (Complementary Metal Oxide Semiconductor) under Cadence Virtuoso. The development method comprises the following steps: S1, compiling a tecfile.tf file, a display.drf file and a CMOS. Layermap file based on CMOS process information; s2, creating a heterogeneous integration library; s3, in the heterogeneous integrated library, creating a view symbol corresponding to the device according to the type of the device, and setting a CDF parameter attribute of the corresponding device according to a parameter file of the device; s4, creating a callback.il file of a callback function of the device, and carrying out abnormal value detection; s5, creating a layout Pcell of the device; 6, developing a design rule check file based on an interconnection process between the CMOS device and the PCB device by using a skill language; by means of the method, the application range of the PDK is widened, and heterogeneous integration of the silicon-based CMOS technology and the PCB library is completed; and a method for checking the design rule of the interconnection process between the CMOS device and the PCB device is provided, so that the PDK can be used for drawing and developing a board-level circuit, and the limitation of development under different platforms is broken through.

The invention provides a CMOS-MEMS (Complementary Metal Oxide Semiconductor-Micro-Electro-Mechanical System) flow and gas thermal conductivity integrated sensor as well as a preparation method and application thereof, and belongs to the field of sensors. The thermal insulation structure is designed between the thermal flow sensor and the gas thermal conductivity sensor, so that external thermal interference and thermal interference among different internal sensors are reduced, related thermophysical parameters of gas are detected at the same time, the flow is corrected, and the detection accuracy is improved. And the performance of the flow sensor is further improved so as to meet the requirements of flow detection and gas parameter detection in a more complex environment. When the sensor is prepared, a Post-CMOS (Complementary Metal Oxide Semiconductor) process without a mask is adopted, so that a complicated photoetching step is avoided, and the post-processing efficiency of the whole Post-CMOS is greatly improved. According to the sensor disclosed by the invention, a CMOS-MEMS (Complementary Metal Oxide Semiconductor-Micro-Electro-Mechanical System) process of monolithic integration and integrated preparation molding of various sensors is realized through reasonable process design.

The invention discloses a high-performance reference voltage implementation method and circuit. The method comprises the following steps: constructing a framework adaptive to low power supply voltage, and determining initial working parameters by selecting a conventional CMOS (Complementary Metal-Oxide-Semiconductor Transistor) process device; a low reference voltage value generation module is designed, a low-voltage NMOS device in a sub-threshold region is matched with a current mirror and a resistance network to output accurate low voltage, and interference is suppressed. First-order and second-order temperature compensation is implemented, and the temperature stability of the reference voltage is improved by utilizing devices with different temperature characteristics and specific NMOS electric leakage characteristics at high temperature. An ultra-low power consumption OP is designed, a low-voltage NMOS and a high-voltage native device are combined, and a bias circuit is optimized. The circuit integrates a low reference voltage module, a first-order temperature compensation module, a second-order temperature compensation module, an ultra-low power consumption OP module and the like. Finally, the working power supply voltage as low as 1V, the power consumption smaller than 100nA and the excellent second-order temperature compensation effect in the full-temperature range are achieved, and stable and accurate reference voltage is provided for related circuits.

The invention discloses a transformer type differential series resonant cavity, a differential series resonant oscillator, a chip and equipment, the resonant cavity comprises a two-port transformer and a variable capacitance module, the two-port transformer comprises an inductor LP1, an inductor LP2, an inductor LS1 and an inductor LS2 which are mutually coupled, and the variable capacitance module comprises a variable capacitor CP and a variable capacitor CS; one end of the inductor LP1 is connected with the first port, and the other end is connected with the variable capacitor CP; one end of the inductor LP2 is connected with the second port, and the other end is connected with the variable capacitor CP; one end of the inductor LS1 and one end of the inductor LS2 are connected with the third port and the fourth port respectively, and the other end of the inductor LS1 and the other end of the inductor LS2 are connected with each other; two ends of the variable capacitor CS are respectively connected with the third port and the fourth port; a plurality of pole frequencies of the voltage gain function AV are set to be equal such that AV at the zero phase increases. According to the invention, the problem that a series resonant oscillator cannot realize pure differential output in the current pure CMOS process is solved.

The invention discloses a CMOS (Complementary Metal Oxide Semiconductor) process humidity sensor capacitor layout implementation method, which comprises the following steps of: arranging top-layer metals with equal width at equal intervals, and connecting strip-shaped metals to form a positive electrode; the top layer metal is formed by arranging the top layer metal with the same width at the same interval, and the strip-shaped metal is connected to form a negative electrode; negative electrode metal plates are inserted into gaps between the metal plates of the positive electrodes at equal intervals to form an interdigital capacitor; a secondary top layer metal strip is inserted into a gap between the positive electrode and the negative electrode of the capacitor; a dielectric material is spin-coated in a gap between the positive electrode and the negative electrode of the interdigital capacitor; the MEMS back-end processing technology compatible with the CMOS technology is adopted, the technology is mature and stable, the top metal aluminum of the CMOS technology is adopted for the electrodes, no new metal material is additionally added, and meanwhile the interdigital capacitor is higher in sensitivity, good in chemical stability and higher in response speed.

The invention relates to the technical field of semiconductors, and discloses an electro-optical modulator and a preparation method thereof, and the preparation method comprises the steps: forming a waveguide core and a plurality of electrodes on a part of the surface of one side, opposite to a first substrate, of a first cladding, and dividing the waveguide core into an internal waveguide core and an external waveguide core; at least part of the electrode further goes deep into the first cladding of partial thickness; forming a second wrapping layer wrapping the electrode and the waveguide core on the surface of the first wrapping layer; forming a plurality of metal interconnection lines on the surface of the second cladding, wherein each metal interconnection line also penetrates through the second cladding and is connected with one electrode; forming a bonding groove penetrating into the partial thickness of the second cladding; forming an electro-optical thin film layer comprising an equal-thickness region and a thickness gradient region in the bonding groove; the projection of the equal-thickness area completely covers the internal waveguide core, and the projection of the thickness gradient area at least covers part of the external waveguide core. The CMOS technology compatibility of the device can be improved, the insertion loss of the device is reduced, and the integration level and the space utilization rate of an optical chip are improved.

Methods and devices to split electromagnetic waves across broad bandwidths in correspondence with predefined polarization state vectors are disclosed. The described methods can be used cameras or image sensors measuring directly the polarization states of an incident electromagnetic waves. The devices include three-dimensional (3D) scattering structures made of dielectric pillars and using existing CMOS processes and direct write lithography techniques. Performance metrics based on the intensity and contrast of the split electromagnetic waves are also disclosed.

The invention relates to the technical field of radio frequency integrated circuits, and discloses a dynamic bias C-type voltage-controlled oscillator based on a CMOS (complementary metal oxide semiconductor) process, the voltage-controlled oscillator adopts a C-type structure, a cross-coupled network adds two resistors and a capacitor on the basis of a cross-coupled transistor, a circuit works in the C type by adjusting bias voltage at a resistor end, and the voltage-controlled oscillator works in the C type. The C-type voltage-controlled oscillator, a tail current source, a variable capacitance network, a switched capacitor array and a fixed LC resonance network form a core structure of the C-type voltage-controlled oscillator capable of numerical control tuning and voltage-controlled tuning, so as to determine the working frequency of the circuit and realize numerical control and voltage-controlled tuning functions; and the operational amplifiers with two bandwidth modes are introduced, so that the problem of difficult oscillation starting is solved, and the oscillation starting speed and the phase noise performance in a stable state are considered at the same time.

The invention belongs to the field of accelerometers, and particularly relates to a nanometer optical accelerometer and a preparation method thereof.The preparation method comprises the steps that silicon nitride films are deposited on the two faces of a silicon wafer, and a target pattern is formed on the top silicon nitride film on one face through the photoetching technology; etching the silicon nitride film at the target pattern by adopting an etching method to form a hole of the target pattern, then etching the silicon wafer by adopting the etching method, and releasing the silicon nitride film to obtain a suspended surface with a mass block; a suspended surface with a mass block is used as a top chip of the nano accelerometer; a quartz plate of which the two surfaces are respectively plated with a high-reflective film and an antireflection film and the middle is provided with a groove is used as a bottom chip, and the top chip and the bottom chip are integrated to prepare the nano optical accelerometer; only one photoetching process is needed, the micro-nano machining process is simple and compatible with the CMOS process, the cost is lower, and the yield of device preparation is improved.

The invention provides a magnetic superconducting memory and a preparation method and a read-write method thereof. According to the magnetic superconducting memory, the superconducting layer maps the magnetization state by using the resistance difference between the superconducting state and the normal state; the ferromagnetic layer serves as a free layer capable of adjusting magnetization, and the magnitude of superconductive critical current of the superconductive layer is influenced through the magnetization direction. The heavy metal layer generates spin orbit torque through a spin Hall effect to drive the ferromagnetic layer to be magnetized and overturned; an infinite switching ratio between a superconducting state and a normal state is realized through a superconducting diode magnetoresistance effect, a high-efficiency and high-reliability nonvolatile storage scheme is realized in combination with a current-driven spin-orbit torque magnetization overturning technology, inherent defects of a traditional TMR are thoroughly overcome, and the signal contrast of a storage unit is remarkably improved; the heterostructure designed by the invention replaces a traditional magnetic tunnel junction, reduces material stacking and process complexity, and adopts a material compatible with a CMOS (Complementary Metal-Oxide-Semiconductor Transistor) process to promote large-scale integration of the low-temperature memory.

The invention provides a high-speed clock duty ratio calibration circuit. The high-speed clock duty ratio calibration circuit comprises an upper-path adjustment sub-circuit and a lower-path adjustment sub-circuit, wherein a feedback control sub-circuit is arranged between the upper-path adjustment sub-circuit and the lower-path adjustment sub-circuit; clock signals input by the input ends of the upper adjusting sub-circuit and the lower adjusting sub-circuit form clock differential signals. The feedback control sub-circuit is used for generating optimal duty ratio control codes of an upper path and a lower path; and the upper adjusting sub-circuit and the lower adjusting sub-circuit control rising edges and falling edges of own clocks according to the corresponding optimal duty ratio control codes, so that the duty ratio is adjusted. The duty ratio calibration circuit can be applied to the CMOS technology of 28 nm or below, high-speed ADC, DAC and SERDES chip design for duty ratio calibration, and the duty ratio calibration circuit has the advantages of being high in precision, low in power consumption and small in area.

The invention discloses a capacitive semiconductor miniature vacuum gauge and a vacuum detection method, and the vacuum gauge achieves the high precision, miniaturization and low power consumption of vacuum measurement through the combination of the electrical amplification characteristic of a semiconductor device and a capacitive sensing principle, makes full use of the compatibility of a standard CMOS technology, and improves the measurement precision. The air pressure sensing module and the signal processing unit are vertically integrated, so that the manufacturing process is simplified, the production cost is reduced, the reliability and the mass production potential of the device are remarkably improved, the measurement range is further widened and the sensitivity is optimized by adjusting the geometric parameters of the electrode, and the sensor has important practical value and wide commercial prospect and is worthy of popularization and application. And an efficient and economic solution is provided for the development of the next generation of miniature vacuum gauges.

The invention belongs to the technical field of semiconductor memories, and particularly relates to a memory chip based on a two-dimensional material flash memory device and a CMOS (complementary metal oxide semiconductor) and a preparation method of the memory chip. The memory chip comprises a substrate and a flash memory array, wherein the substrate is prepared by a CMOS (Complementary Metal Oxide Semiconductor) process and is provided with a memory peripheral circuit; the flash memory array is constructed by a two-dimensional material flash memory device; the substrate with a memory peripheral circuit includes: a bottom substrate; the MOS device is arranged on the surface of the substrate; an isolation layer between the metal wires; based on the ultrafast nonvolatile storage characteristic of the two-dimensional material flash memory device, the integration density of the flash memory device is further improved, and the method comprises the steps of flash memory device stacking design, flash memory device structure design and flash memory array circuit structure design. On the basis of keeping the basic performance of the ultra-fast flash memory device, the three-dimensional stacking and scale integration of the flash memory device compatible with the CMOS process are realized, and the collaborative breakthrough of the storage performance and the storage density of a storage chip is further realized.

The invention relates to the technical field of microelectronics and MEMS manufacturing, in particular to a bulk acoustic resonator with a double-layer piezoelectric film and a preparation method thereof, according to the method, a heterogeneous integrated key structure is formed by a first piezoelectric layer and a second piezoelectric layer which are deposited on the two sides of a middle electrode layer respectively, the physical and process limits of a single-layer piezoelectric film FBAR are broken through, the high-frequency band is improved, and the high-frequency band is improved. A wider bandwidth is realized; middle electrode layer tuning is combined with back silicon through hole leading-out, front routing inductance is eliminated, and the low-loss characteristic of the filter under high frequency is guaranteed; the self-heating problem under large bandwidth and high power is effectively inhibited through heat dissipation integrated packaging, and the power bearing capacity is improved; the method is compatible with a CMOS (complementary metal oxide semiconductor) process and can be directly embedded into an existing production line, so that the volume is further reduced while the bulk acoustic wave resonator with the double-layer piezoelectric film can effectively cover a frequency band of more than 3GHz, and the problem that a single-layer piezoelectric film and a matched process thereof cannot meet the requirements of a next-generation radio frequency front end on high frequency, large bandwidth, high power and wafer-level packaging is solved.

The present application provides a composite waveguide structure and a preparation method thereof, belonging to the technical field of electro-optical modulators, comprising a first waveguide wafer, including a substrate, a SiO2 film, a first metal electrode, a first waveguide structure, a second metal electrode and a groove; the second metal electrode is connected to the first metal electrode through a metal interconnection through-hole, the second metal electrode is also connected to a thermal adjustment structure, a pad hole is provided above the second metal electrode, and the bottom of the groove is located above the first waveguide structure in the area to be bonded; the electro-optical film comprises a SiO2 film, a waveguide boss and a second waveguide structure, the waveguide boss and the second waveguide structure are located in the groove, the second waveguide structure is bonded to the bottom of the groove, a bonding reserved hole is provided on the SiO2 film, the position of which corresponds to the position of the pad hole, and the material of the second waveguide structure is an electro-optical material. The present application scheme improves the process structure compatibility between the bonding area and the non-bonding area, and the CMOS process compatibility of W2W in heterogeneous integration applications.

The application relates to a gallium nitride epitaxial structure forming method and a semiconductor device. The method comprises the following steps: sequentially forming a buffer layer, an intrinsic GaN layer and an AlGaN layer on a substrate; growing a P-type doped GaN epitaxial layer on the AlGaN layer, controlling the doping concentration and thickness of the P-type GaN layer, performing N-type ion implantation on the P-type GaN layer, controlling the implantation depth in the range of 20nm-30nm, and then performing annealing. In another mode, the AlGaN layer is subjected to P-type ion implantation before the P-type GaN layer is grown to form an asymmetric P-type doped area, and then annealing is performed, and the implantation area is still P-type after annealing by controlling the implantation dose. In the semiconductor device, the contact layer is obtained by patterning the P-type GaN layer, and the P-type doped area with the highest doping concentration or the largest doping area is arranged at the position of the contact layer. The gate breakdown voltage can be improved, the threshold voltage can be stabilized, the low on-resistance can be maintained, and the CMOS process compatibility can be realized.

The application discloses a reset pulse width adjustable Timer circuit and a driver, and realizes an effective method for adjusting the reset pulse width based on a CMOS process technology.The reset pulse width adjustable Timer circuit comprises a state indication module, a current source module, a charge and discharge module and a comparator module for realizing the adjustable pulse width.The source voltage comparison circuit can effectively determine the end time of the reset signal pulse by the comparison result of the comparison voltage and the threshold value of the Timer, so that the pulse width of the reset signal is adjustable, the precision of the Timer timing and resetting is greatly improved, the problem that the Timer may be abnormally stopped and the abnormal situation may be missed due to the fixed pulse width of the reset signal of the traditional Timer structure after the timing period is accumulated is solved, and the reliability and stability of the synchronous rectification driver in the isolated DC / DC power supply are improved.

The invention belongs to the technical field of semiconductor memory packaging, and particularly relates to a memory chip based on two-dimensional material and CMOS circuit 2.5 D integration and a preparation method thereof. According to the chip, a 2.5 D packaging structure is adopted, two-dimensional material ultra-flash memory device core particles and peripheral control circuit core particles prepared by adopting a standard CMOS technology are integrated on an intermediate layer, reliable electric connection is achieved through a metal bump-solder ball interconnection structure, a low-temperature flip-chip technology is adopted in the packaging process, and therefore the reliability of the chip is improved. The design of a multi-layer metal bump laminated structure is matched, and the heat sensitivity and interconnection reliability of the two-dimensional material are considered; and the intermediate layer is further connected with a PCB test board below the intermediate layer to construct signal channels among the core particles and outside the chip. According to the structure, the ultrafast programming / erasing characteristic of the two-dimensional material flash memory and the logic function advantage of the CMOS circuit are fully combined, and a feasible path and technical support are provided for engineering and system-level application of a two-dimensional material ultrafast memory device.

The present invention discloses a steep subthreshold swing bipolar transistor based on ferroelectric nanogaps and a preparation method thereof. The transistor comprises, arranged from bottom to top, a substrate, a buffer layer, a conductive film layer, a ferroelectric dielectric film layer, and a gate, as well as a top gate control signal unit and a source-drain signal input unit. One end of the top gate control signal unit is connected to the gate, and the other end is connected to a series branch. The two ends of the source-drain signal input unit are respectively connected to the source and drain of the conductive film layer to form a series branch. The source-drain signal input unit is used to read the current of the steep subthreshold swing bipolar transistor. The top gate control signal unit is used to output a voltage to generate a vertical electric field to control the opening and closing of the nanogaps in the conductive film layer. The steep subthreshold swing bipolar transistor proposed in the present invention has the advantages of near-zero off-current, large on-current, steep subthreshold swing, low power consumption, and compatibility with traditional CMOS processes.

The invention discloses an OTP (One Time Programmable) memory array and an operation method thereof. The OTP storage array comprises a plurality of OTP storage units, and the OTP storage units are arranged to form a plurality of rows and columns; each OTP storage unit comprises a selection tube and a storage module, a grid electrode of the selection tube is connected with a word line, a first end of the selection tube is connected with a bit line, a second end of the selection tube is connected with a first end of the storage module, and a second end of the storage module is a control end and is connected with a programming line; grid electrodes of the selection tubes in the same row are connected with the same word line, first ends of the selection tubes in the same column are connected with the same bit line, and control ends of the storage modules in two adjacent rows are connected with the same programming line. According to the invention, the area of the OTP storage array is reduced, the OTP storage array can be realized completely based on a CMOS process flow, and the operation method of the OTP storage array is simpler and more convenient.

The present invention provides a curvature-corrected bandgap reference circuit, which includes a bandgap reference module, a low-temperature curvature correction module, and a high-temperature curvature correction module. The bandgap reference module generates a bandgap reference voltage by superimposing a positive temperature coefficient voltage and a negative temperature coefficient voltage. The low-temperature curvature correction module compensates and adjusts the positive temperature coefficient voltage to correct the low-temperature curvature of the bandgap reference voltage. The high-temperature curvature correction module compensates and adjusts the positive temperature coefficient voltage to correct the high-temperature curvature of the bandgap reference voltage, further reducing the temperature drift coefficient of the bandgap reference voltage and improving the temperature stability of the bandgap reference voltage. An adjusting resistor is introduced to balance the curvature correction compensation degree at low and high temperatures, further improving performance. At the same time, the curvature-corrected bandgap reference circuit proposed by the present invention can be used in a relatively low power supply voltage environment and is suitable for advanced CMOS processes of 28nm and below.

The invention provides a gate injection type ferroelectric field effect transistor and a preparation method thereof, and belongs to the technical field of micro-nano electronics. The ferroelectric field effect transistor structurally comprises a semiconductor substrate, a highly-doped source region, a highly-doped drain region, a metal gate electrode and a gate stack, the structure of the gate stack sequentially comprises a channel insulating layer, a ferroelectric layer, a charge trapping layer and a gate insulating layer from bottom to top, the charge trapping layer comprises three layers of materials, and the structure of the charge trapping layer sequentially comprises a layer of charge trapping material, a layer of barrier layer insertion layer and a layer of charge trapping material from bottom to top; the metal gate electrode is located on the gate stack, and the highly-doped source region and the highly-doped drain region are located on the two sides of a channel region below the gate stack respectively. By introducing the charge trapping layer and inserting the barrier layer in the charge trapping layer, the storage characteristic of the device is improved, the preparation method is simple, and a material system is compatible with a CMOS (Complementary Metal-Oxide-Semiconductor Transistor) process; the storage window and the retention characteristic of the gate injection type ferroelectric field effect transistor are improved, and the gate injection type ferroelectric field effect transistor has high practical value.

The invention discloses a wide-swing output stage circuit. The wide-swing output stage circuit comprises a substrate bias control unit and an output stage circuit, wherein the substrate bias control unit is used for generating substrate bias voltages VBP and VBN according to output swing requirements and outputting the substrate bias voltages VBP and VBN to the output stage unit, and the output stage unit generates output signals meeting the output swing requirements by accessing the substrate bias voltages. According to the scheme, the swing increasing circuit is simple in structure and convenient to control, high-voltage devices and expensive complex processes are not needed, high-swing output can be achieved by adopting a conventional common commercial CMOS process tape-out, under the condition that a power supply is not increased, the output swing of a processing signal is increased by adjusting the substrate voltage of the MOS transistor output by the operational amplifier, and therefore the signal processing efficiency is improved. The dynamic range of an analog integrated circuit designed by applying the operational amplifier of the type can be effectively improved, and the operational amplifier is very suitable for the design of a low-power-supply-voltage analog integrated circuit with a smaller deep submicron size.

The invention discloses a finger type Hall sensor, and relates to the field of microelectronics and solid state electronics, in particular to a Hall sensor. A traditional cross-shaped Hall element is modified into a structure comprising four or more fingers, so that the influence of a multi-contact structure on current flowing in equipment is optimized, more current flows in an effective vector direction, and weakening of device geometric factors on sensitivity is reduced. A three-dimensional COMSOL model is used for simulating and comparing a current flow schematic diagram and current related sensitivity of a Hall device under the condition that a gap is 1-3 microns, and a Hall sensor with relatively high sensitivity is provided. The Hall device is characterized in that the Hall device is of a 90-degree rotationally symmetrical finger-shaped structure, the up-down width and the left-right width of the sensor size are 40 microns, the thickness of the sensor size is 5 microns, an active region adopts a silicon material 2.6 E + 16 cm < 3 > N well doped CMOS process, and when the gap width is 1.2 microns, the optimal 308.55 V / (AT) current related sensitivity can be obtained; compared with a traditional Hall piece model, the sensitivity is improved.

Techniques of integrating lateral HBT devices into a silicon on insulator (SOI) CMOS process. Similar approaches could also be applied to Fin Field-Effect Transistors (FinFETs). A first technique makes use of a CMOS replacement gate process that is typically associated with a partially depleted SOI (PDSOI) or fully depleted SOI (FDSOI) process. A second technique is independent of the CMOS process. Both techniques can accommodate silicon germanium (SiGe) and / or III-V materials, include a self-aligned base contact, and can be used to construct both NPN and PNP transistors with varied peak fT and breakdown voltages.