207 results about "Cmos process" patented technology

The present application provides an all-digital multi-phase DC-DC controller. The digital DC-DC controller includes time-based analog-to-digital converters (ADCs) for converting analog voltage signals into digital-domain signals so as to benefit from gate length scaling without limited by the low voltage swing. Also, the DC-DC controller further includes a digital control circuit and a time-based modulator. The digital control circuit can control the time-based modulator in a digital domain, thereby reducing the affection caused by process, voltage and temperature (PVT) variation. Also, the time-based modulator can adjust the timing of the PWM signals and avoid the performance degradation caused by circuit mismatch. Since the digital control circuit can be fully synthesizable, it allows implementations in all kinds of digital CMOS processes with a small chip area.

The invention relates to the technical field of radio frequency integrated circuits, and discloses a dynamic bias C-type voltage-controlled oscillator based on a CMOS (complementary metal oxide semiconductor) process, the voltage-controlled oscillator adopts a C-type structure, a cross-coupled network adds two resistors and a capacitor on the basis of a cross-coupled transistor, a circuit works in the C type by adjusting bias voltage at a resistor end, and the voltage-controlled oscillator works in the C type. The C-type voltage-controlled oscillator, a tail current source, a variable capacitance network, a switched capacitor array and a fixed LC resonance network form a core structure of the C-type voltage-controlled oscillator capable of numerical control tuning and voltage-controlled tuning, so as to determine the working frequency of the circuit and realize numerical control and voltage-controlled tuning functions; and the operational amplifiers with two bandwidth modes are introduced, so that the problem of difficult oscillation starting is solved, and the oscillation starting speed and the phase noise performance in a stable state are considered at the same time.

The invention belongs to the field of accelerometers, and particularly relates to a nanometer optical accelerometer and a preparation method thereof.The preparation method comprises the steps that silicon nitride films are deposited on the two faces of a silicon wafer, and a target pattern is formed on the top silicon nitride film on one face through the photoetching technology; etching the silicon nitride film at the target pattern by adopting an etching method to form a hole of the target pattern, then etching the silicon wafer by adopting the etching method, and releasing the silicon nitride film to obtain a suspended surface with a mass block; a suspended surface with a mass block is used as a top chip of the nano accelerometer; a quartz plate of which the two surfaces are respectively plated with a high-reflective film and an antireflection film and the middle is provided with a groove is used as a bottom chip, and the top chip and the bottom chip are integrated to prepare the nano optical accelerometer; only one photoetching process is needed, the micro-nano machining process is simple and compatible with the CMOS process, the cost is lower, and the yield of device preparation is improved.

The invention provides a magnetic superconducting memory and a preparation method and a read-write method thereof. According to the magnetic superconducting memory, the superconducting layer maps the magnetization state by using the resistance difference between the superconducting state and the normal state; the ferromagnetic layer serves as a free layer capable of adjusting magnetization, and the magnitude of superconductive critical current of the superconductive layer is influenced through the magnetization direction. The heavy metal layer generates spin orbit torque through a spin Hall effect to drive the ferromagnetic layer to be magnetized and overturned; an infinite switching ratio between a superconducting state and a normal state is realized through a superconducting diode magnetoresistance effect, a high-efficiency and high-reliability nonvolatile storage scheme is realized in combination with a current-driven spin-orbit torque magnetization overturning technology, inherent defects of a traditional TMR are thoroughly overcome, and the signal contrast of a storage unit is remarkably improved; the heterostructure designed by the invention replaces a traditional magnetic tunnel junction, reduces material stacking and process complexity, and adopts a material compatible with a CMOS (Complementary Metal-Oxide-Semiconductor Transistor) process to promote large-scale integration of the low-temperature memory.

The invention relates to the technical field of microelectronics and MEMS manufacturing, in particular to a bulk acoustic resonator with a double-layer piezoelectric film and a preparation method thereof, according to the method, a heterogeneous integrated key structure is formed by a first piezoelectric layer and a second piezoelectric layer which are deposited on the two sides of a middle electrode layer respectively, the physical and process limits of a single-layer piezoelectric film FBAR are broken through, the high-frequency band is improved, and the high-frequency band is improved. A wider bandwidth is realized; middle electrode layer tuning is combined with back silicon through hole leading-out, front routing inductance is eliminated, and the low-loss characteristic of the filter under high frequency is guaranteed; the self-heating problem under large bandwidth and high power is effectively inhibited through heat dissipation integrated packaging, and the power bearing capacity is improved; the method is compatible with a CMOS (complementary metal oxide semiconductor) process and can be directly embedded into an existing production line, so that the volume is further reduced while the bulk acoustic wave resonator with the double-layer piezoelectric film can effectively cover a frequency band of more than 3GHz, and the problem that a single-layer piezoelectric film and a matched process thereof cannot meet the requirements of a next-generation radio frequency front end on high frequency, large bandwidth, high power and wafer-level packaging is solved.

The present application provides a composite waveguide structure and a preparation method thereof, belonging to the technical field of electro-optical modulators, comprising a first waveguide wafer, including a substrate, a SiO2 film, a first metal electrode, a first waveguide structure, a second metal electrode and a groove; the second metal electrode is connected to the first metal electrode through a metal interconnection through-hole, the second metal electrode is also connected to a thermal adjustment structure, a pad hole is provided above the second metal electrode, and the bottom of the groove is located above the first waveguide structure in the area to be bonded; the electro-optical film comprises a SiO2 film, a waveguide boss and a second waveguide structure, the waveguide boss and the second waveguide structure are located in the groove, the second waveguide structure is bonded to the bottom of the groove, a bonding reserved hole is provided on the SiO2 film, the position of which corresponds to the position of the pad hole, and the material of the second waveguide structure is an electro-optical material. The present application scheme improves the process structure compatibility between the bonding area and the non-bonding area, and the CMOS process compatibility of W2W in heterogeneous integration applications.

The application relates to a gallium nitride epitaxial structure forming method and a semiconductor device. The method comprises the following steps: sequentially forming a buffer layer, an intrinsic GaN layer and an AlGaN layer on a substrate; growing a P-type doped GaN epitaxial layer on the AlGaN layer, controlling the doping concentration and thickness of the P-type GaN layer, performing N-type ion implantation on the P-type GaN layer, controlling the implantation depth in the range of 20nm-30nm, and then performing annealing. In another mode, the AlGaN layer is subjected to P-type ion implantation before the P-type GaN layer is grown to form an asymmetric P-type doped area, and then annealing is performed, and the implantation area is still P-type after annealing by controlling the implantation dose. In the semiconductor device, the contact layer is obtained by patterning the P-type GaN layer, and the P-type doped area with the highest doping concentration or the largest doping area is arranged at the position of the contact layer. The gate breakdown voltage can be improved, the threshold voltage can be stabilized, the low on-resistance can be maintained, and the CMOS process compatibility can be realized.

The application discloses a reset pulse width adjustable Timer circuit and a driver, and realizes an effective method for adjusting the reset pulse width based on a CMOS process technology.The reset pulse width adjustable Timer circuit comprises a state indication module, a current source module, a charge and discharge module and a comparator module for realizing the adjustable pulse width.The source voltage comparison circuit can effectively determine the end time of the reset signal pulse by the comparison result of the comparison voltage and the threshold value of the Timer, so that the pulse width of the reset signal is adjustable, the precision of the Timer timing and resetting is greatly improved, the problem that the Timer may be abnormally stopped and the abnormal situation may be missed due to the fixed pulse width of the reset signal of the traditional Timer structure after the timing period is accumulated is solved, and the reliability and stability of the synchronous rectification driver in the isolated DC / DC power supply are improved.

The invention belongs to the technical field of semiconductor memory packaging, and particularly relates to a memory chip based on two-dimensional material and CMOS circuit 2.5 D integration and a preparation method thereof. According to the chip, a 2.5 D packaging structure is adopted, two-dimensional material ultra-flash memory device core particles and peripheral control circuit core particles prepared by adopting a standard CMOS technology are integrated on an intermediate layer, reliable electric connection is achieved through a metal bump-solder ball interconnection structure, a low-temperature flip-chip technology is adopted in the packaging process, and therefore the reliability of the chip is improved. The design of a multi-layer metal bump laminated structure is matched, and the heat sensitivity and interconnection reliability of the two-dimensional material are considered; and the intermediate layer is further connected with a PCB test board below the intermediate layer to construct signal channels among the core particles and outside the chip. According to the structure, the ultrafast programming / erasing characteristic of the two-dimensional material flash memory and the logic function advantage of the CMOS circuit are fully combined, and a feasible path and technical support are provided for engineering and system-level application of a two-dimensional material ultrafast memory device.

The present invention discloses a steep subthreshold swing bipolar transistor based on ferroelectric nanogaps and a preparation method thereof. The transistor comprises, arranged from bottom to top, a substrate, a buffer layer, a conductive film layer, a ferroelectric dielectric film layer, and a gate, as well as a top gate control signal unit and a source-drain signal input unit. One end of the top gate control signal unit is connected to the gate, and the other end is connected to a series branch. The two ends of the source-drain signal input unit are respectively connected to the source and drain of the conductive film layer to form a series branch. The source-drain signal input unit is used to read the current of the steep subthreshold swing bipolar transistor. The top gate control signal unit is used to output a voltage to generate a vertical electric field to control the opening and closing of the nanogaps in the conductive film layer. The steep subthreshold swing bipolar transistor proposed in the present invention has the advantages of near-zero off-current, large on-current, steep subthreshold swing, low power consumption, and compatibility with traditional CMOS processes.

The invention provides a gate injection type ferroelectric field effect transistor and a preparation method thereof, and belongs to the technical field of micro-nano electronics. The ferroelectric field effect transistor structurally comprises a semiconductor substrate, a highly-doped source region, a highly-doped drain region, a metal gate electrode and a gate stack, the structure of the gate stack sequentially comprises a channel insulating layer, a ferroelectric layer, a charge trapping layer and a gate insulating layer from bottom to top, the charge trapping layer comprises three layers of materials, and the structure of the charge trapping layer sequentially comprises a layer of charge trapping material, a layer of barrier layer insertion layer and a layer of charge trapping material from bottom to top; the metal gate electrode is located on the gate stack, and the highly-doped source region and the highly-doped drain region are located on the two sides of a channel region below the gate stack respectively. By introducing the charge trapping layer and inserting the barrier layer in the charge trapping layer, the storage characteristic of the device is improved, the preparation method is simple, and a material system is compatible with a CMOS (Complementary Metal-Oxide-Semiconductor Transistor) process; the storage window and the retention characteristic of the gate injection type ferroelectric field effect transistor are improved, and the gate injection type ferroelectric field effect transistor has high practical value.

The invention discloses a wide-swing output stage circuit. The wide-swing output stage circuit comprises a substrate bias control unit and an output stage circuit, wherein the substrate bias control unit is used for generating substrate bias voltages VBP and VBN according to output swing requirements and outputting the substrate bias voltages VBP and VBN to the output stage unit, and the output stage unit generates output signals meeting the output swing requirements by accessing the substrate bias voltages. According to the scheme, the swing increasing circuit is simple in structure and convenient to control, high-voltage devices and expensive complex processes are not needed, high-swing output can be achieved by adopting a conventional common commercial CMOS process tape-out, under the condition that a power supply is not increased, the output swing of a processing signal is increased by adjusting the substrate voltage of the MOS transistor output by the operational amplifier, and therefore the signal processing efficiency is improved. The dynamic range of an analog integrated circuit designed by applying the operational amplifier of the type can be effectively improved, and the operational amplifier is very suitable for the design of a low-power-supply-voltage analog integrated circuit with a smaller deep submicron size.

Techniques of integrating lateral HBT devices into a silicon on insulator (SOI) CMOS process. Similar approaches could also be applied to Fin Field-Effect Transistors (FinFETs). A first technique makes use of a CMOS replacement gate process that is typically associated with a partially depleted SOI (PDSOI) or fully depleted SOI (FDSOI) process. A second technique is independent of the CMOS process. Both techniques can accommodate silicon germanium (SiGe) and / or III-V materials, include a self-aligned base contact, and can be used to construct both NPN and PNP transistors with varied peak fT and breakdown voltages.

This invention discloses a method for controlling the polarization reversal characteristics of hafnium-based ferroelectric thin films through surface ion treatment, relating to the field of ferroelectric memory device technology. The method includes: providing a substrate; forming a hafnium-based ferroelectric thin film on the substrate; and after rapid thermal annealing of the hafnium-based ferroelectric thin film, introducing control ions onto the film surface through a surface ion treatment process to control the polarization reversal characteristics. The surface ion treatment process includes electrochemical treatment or plasma treatment, and the control ions include one or more of halide ions, hydrogen ions, hydroxide ions, sulfur-containing ions, and nitrogen-containing ions. This invention achieves effective control of the surface electric field distribution and polarization reversal barrier of the hafnium-based ferroelectric thin film through surface ion treatment, significantly reducing the coercive field and optimizing polarization stability, enabling ferroelectric domains to flip at lower voltages. This method is simple, low-cost, and compatible with CMOS processes, making it suitable for fabricating high-performance, low-power ferroelectric memory devices.

The application discloses a low-power bandgap reference current source circuit and a control method, and the circuit comprises a current mode bandgap circuit, an error amplifier input stage circuit, a threshold modulation circuit and a current mirror circuit; the current mode bandgap circuit is internally provided with an error amplifier OPAMP and a proportional resistance network; the error amplifier input stage circuit is a PMOS pair tube input stage circuit; the threshold modulation circuit is a source-liner forward bias threshold modulation circuit, which is used for forward biasing the threshold voltage of all PMOS tubes in the low-power bandgap reference current source circuit and enabling the NMOS tube connected with the error amplifier OPAMP output stage to work in a saturation region; and the current mirror circuit is a series diode compensation method current mirror circuit structure. The application is compatible with a standard CMOS process, realizes sub-1V low voltage, micro-nano ampere level low power consumption, high-precision low-noise small area effect, solves various technical pain points of a traditional scheme, and has excellent application prospects in a wearable device power management system.

The application discloses a parallel polynomial gradient calculation system and method based on a CMOS nerve synapse transistor, and relates to the technical field of calculation systems.The parallel polynomial gradient calculation system based on the CMOS nerve synapse transistor adopts a basic calculation unit containing at least one CMOS transistor, and configures the CMOS transistor to exhibit the dual-mode characteristics of neuron behavior and synapse behavior in a floating substrate operation mode, and meanwhile, combines a parallel array architecture, so that the application realizes a neuromorphic calculation hardware based on a standard CMOS process, utilizes mature CMOS manufacturing technology, avoids special materials and post-integration processes required by emerging devices such as memristors, thereby improving the manufacturability and yield of the system, and reducing production costs.Meanwhile, the inherent device consistency and long-term stability of the CMOS transistor effectively overcome the problems of large differences between devices and state drift in the memristor scheme, and realize high-precision polynomial gradient calculation.

According to the photodiode structure, the preparation method thereof and the CMOS image sensor, the perovskite / silicon heterojunction is constructed in the photodiode structure, and the spectral response range is remarkably expanded by using the high absorption coefficient of perovskite in an ultraviolet-visible region and the light absorption advantage of silicon in a near-infrared region; after photons irradiate on the silicon and the perovskite light absorption layer to excite and generate photo-induced electron-hole pairs, holes in the perovskite light absorption layer are extracted by the photo-induced hole transport layer, photo-induced electrons enter the N-well region through the electron transport layer, the photo-induced holes in the silicon diffuse and drift to the P-type substrate, and the photo-induced electrons are collected and temporarily stored in the N-well region; the compound probability of photon-generated carriers is effectively reduced, the photoelectric response speed is increased, the preparation process is simple, the method can be compatible with an existing CMOS process technology, large-area manufacturing is easy to achieve, the manufacturing cost is reduced, and the method has great significance in promoting development of a next-generation wide-spectrum and high-sensitivity image sensor.

This invention discloses a radio frequency millimeter-wave phase-to-voltage converter, belonging to the field of radio frequency microwave integrated circuit technology. The converter includes: a first and second frequency divider chain for dividing two input signals to achieve phase compression; a first and second quadrature generator for providing a -90° linearized bias; a three-state coupling network connected between the two frequency divider chains to eliminate phase mode ambiguity introduced by the frequency dividers through reconfigurable coupled phase; and a symmetrical phase detector for converting the linearized phase difference into a voltage signal output. This invention compresses the ±180° phase difference to a small angle range using phase compression technology, combined with linearized bias to allow the phase detector to operate in the linear region, and utilizes the three-state coupling network to achieve unambiguous detection across the entire 360° phase range. Implemented using a 40nm CMOS process, it requires no external clock, has no inductor design, a core area of ​​only 0.016mm², power consumption of 22mW, a response speed of 120ns, and a linearity of 1.05% FSR.

The application belongs to the technical field of radio frequency band micro-antenna, and particularly relates to a flexible transverse field excited film bulk acoustic wave magnetoelectric antenna. The flexible transverse field excited film bulk acoustic wave magnetoelectric antenna comprises a flexible support substrate, a piezoelectric single crystal arranged on the flexible support substrate, a coplanar electrode arranged on the piezoelectric single crystal, and a magnetostrictive film arranged between an input electrode and a grounding electrode. The magnetoelectric antenna works in an in-plane vibration mode, has a stronger magnetoelectric coupling coefficient, and can effectively improve the radiation power. Compared with a traditional cavity FBAR magnetoelectric antenna, the flexible transverse field excited film bulk acoustic wave magnetoelectric antenna has a simple preparation process, is compatible with a CMOS process, can work in a flexible application scenario, and has a high quality factor.

The invention relates to the technical field of integrated circuit design, in particular to a non-zero potential output level conversion circuit realized based on a CMOS (complementary metal oxide semiconductor) process, and a low-voltage differential circuit realizes conversion from a single-end low level to a differential level. The pre-stage level conversion circuit realizes conversion from a low level to a working IO level. The post-stage level conversion circuit realizes conversion of a process limit high level; and the voltage selection circuit controls a voltage selector through a signal output by the post-stage level conversion circuit so as to realize switching between the working IO voltage and the process limit voltage. Through a three-stage gradient voltage distribution architecture and a dynamic substrate bias technology, digital low voltage passes through a level conversion and voltage selection circuit, a special level conversion circuit for outputting low level exceeding zero potential is realized, and the working voltage of all MOS transistors is ensured to be strictly lower than a process breakdown threshold. The method can be applied to burning of a one-time programmable chip in a system on chip and other scenes needing non-zero low potential and process limit high voltage switching.

The present invention provides a phase shifter that can be manufactured using a CMOS process, exhibits low optical propagation loss, can maintain refractive index changes without power supply, and allows for the resetting of those refractive index changes. [Solution] The phase shifter 100 of the present invention comprises an optical waveguide 101 composed of a core 105 and a cladding 106 surrounding the core 105, a substrate 102 on which the optical waveguide 101 is mounted, a heating means 103 for heating the core 105, and an ultraviolet irradiation means 104 for irradiating the core 105 with ultraviolet U, wherein the core 105 mainly contains silicon nitride, and the density of silicon dangling bonds of silicon nitride is 10 in terms of spin density 18 cm -3 The above 10 20 cm -3 The following applies:

The invention relates to the technical field of semiconductor manufacturing, in particular to a multiband infrared detector and a preparation method thereof. The invention provides a collaborative innovation scheme of low stress stripping and multiband physical stacking of silicon-based heteroepitaxy Hg (1-x n) CdxnTe. Aiming at the problems of strong substrate dependence, out-of-control warping rate of a large-size silicon substrate, difficulty in multi-band expansion and the like in the prior art, higher functionality and compatibility of silicon substrate, Hg (1-x n) CdxnTe and CMOS processes are realized through silicon-based ZnTe sacrificial layer design, a perfect stripping and transferring scheme and a high-precision physical stacking framework, the yield is improved, and the preparation complexity of a multi-band detector is reduced. According to the invention, warping of a molecular beam epitaxy silicon substrate can be solved, the dark current density is effectively reduced, and a multiband infrared detection function can be more efficiently and freely realized.

This application belongs to the field of semiconductor device technology, specifically disclosing a threshold switching device based on a p-x-n structure and its fabrication method. In the threshold switching device, the first polar semiconductor layer and the second polar semiconductor layer have opposite polarities, being one of an n-type semiconductor layer and a p-type semiconductor layer, respectively. The charge trapping layer contains trap energy levels, used to achieve volatile threshold switching behavior through a charge trapping and releasing mechanism under voltage. The lower electrode and the upper electrode are used to apply voltage. The device fabricated in this application is fully compatible with CMOS processes and possesses both self-rectification capabilities and nanosecond-level fast switching characteristics.

According to the tensile strain germanium wafer on the glass substrate, the imaging chip and the forming method of the imaging chip, the acceptor substrate comprises the transparent glass substrate, the light transmittance of the short-wave infrared band is extremely high, light of the short-wave infrared band can reach the tensile strain germanium layer, the transparent glass substrate can also enable visible light to penetrate, and the imaging chip can be applied to the imaging chip. Visible light can also reach the tensile strain germanium layer. Light of more wavebands enters the tensile strain germanium wafer on the glass substrate through the transparent glass substrate, the tensile strain of the tensile strain germanium layer is further increased through direct wafer bonding operation, the response capacity to incident light is improved, and the wavelength response range of the tensile strain germanium wafer on the glass substrate is expanded to be within the range of 400 nm to 1700 nm. The wafer taking the transparent glass as the substrate is large in size and low in batch production cost, can be highly compatible with a CMOS (complementary metal oxide semiconductor) process production line, can overcome the defects of fragility, high cost and the like of a bulk germanium material, and improves the quality of the tensile strain germanium wafer on the glass substrate.

The application discloses a thermal type wind speed and direction sensor based on thermistors and thermoelectric piles and a working method thereof. The sensor structure comprises a thermistor, a thermoelectric pile, a heating resistor, a silicon substrate and a measurement and control IC. The heating resistor is square and located at the center of the substrate. Four thermistors and a thermoelectric pile parallel to the side edges of the heating resistor are distributed on the four sides of the heating resistor. The four parallel thermistors are connected to form a Wheatstone full-bridge temperature measurement structure, and the two parallel thermoelectric piles are connected to form a thermoelectric pile temperature measurement structure. The measurement and control IC is distributed at the four corners of the substrate and connected to the temperature measurement structure formed by the heating resistor, the thermoelectric pile and the thermistor, and is used for driving the detection structure and processing the output signal thereof. The application adopts a CMOS process, and the thermistor and the thermoelectric pile structure are redundant to each other, so that the wind speed and direction detection precision can be improved.

A method of preparing a programmable diode, including: forming a tungsten plug by a standard CMOS process; taking the tungsten plug as a lower electrode and depositing a functional layer material such as a ferroelectric film on the tungsten plug; depositing an upper electrode on the functional layer material; and patterning the upper electrode and a functional layer to complete a preparation of the programmable diode. The present disclosure further discloses a ferroelectric memory of a programmable diode prepared by the method of preparing a programmable diode. The method of preparing a programmable diode does not require growing a lower electrode and reduces a complexity of the process. The ferroelectric memory includes a transistor and a programmable diode. This design stores information according to different polarities of the diode, thus a device area may be further reduced and a storage density may be improved.

The application discloses a multi-channel VLC system based on a CMOS process, comprising a transmitting module and a receiving module; the transmitting module comprises a vertical polarization transmitting submodule and a horizontal polarization transmitting submodule; the receiving module comprises a vertical polarization receiving submodule and a horizontal polarization receiving submodule; the vertical polarization transmitting submodule emits three routes of non-polarized light emitted by a first RGB-LED after vertical polarization dispersion, parallel conversion and emission, and the vertical polarization receiving submodule forms three routes of analog electric signals after filtering of the received multicolor visible light signals by a metasurface; the horizontal polarization transmitting submodule emits three routes of non-polarized light emitted by a second RGB-LED after horizontal polarization dispersion, parallel conversion and emission, and the horizontal polarization receiving submodule converts the received multicolor visible light signals into three routes of analog electric signals after filtering by a metasurface; and six routes of analog electric signals are converted into one route of digital electric signal output. The application can realize clear and complete multi-channel high-speed communication.

The invention relates to the technical field of optical waveguides, and particularly discloses a manufacturing method of an optical waveguide end face coupler and the optical waveguide end face coupler, in the process of manufacturing the optical waveguide end face coupler, a dielectric material, namely silicon oxynitride or silicon oxycarbide, is deposited on a siliceous substrate wafer through a CVD method in a CMOS process, in the manufacturing process, the manufacturing process can be connected with the manufacturing process of an electronic device, the high-refractive-index gradient layers of the lower gradient layer, the middle gradient layer and the upper gradient layer and the core layer are finally manufactured, and the effective refractive index is linearly changed in cooperation with a common insulating medium in the semiconductor technology, namely, the low-refractive-index gradient layers prepared from silicon dioxide, and the effective refractive index is changed in a linear mode. And based on the characteristic that the refractive indexes of the silicon oxynitride and the silicon oxycarbide are adjustable, the optical waveguide end face coupler which can adapt to a semiconductor photon-electron heterogeneous integrated scene, can be compatible to the manufacturing process of an electronic device and has a wide-range core cladding refractive index difference is finally obtained.

A method for fabricating a semiconductor device is described. Generally, the method includes forming a customizable oxide-nitride (ONO) stack on a substrate in an in situ atomic layer deposition (ALD) tool or chamber. A radical oxidation or oxide deposition process step is performed to form a tunnel dielectric layer overlying the substrate. A silicon nitride deposition process step is also performed to form a multilayer charge trapping (CT) layer, and at least some of the process parameters of the silicon nitride deposition process step are adjusted in forming first and second CT sublayers of the multilayer CT layer. A subsequent radical oxidation or oxide deposition process step is performed in the ALD tool to form a blocking dielectric layer overlying the multilayer CT layer.

The invention relates to the technical field of integrated circuits and electronic circuits, in particular to a multi-mode multiplexing differential driving circuit based on a CMOS (complementary metal oxide semiconductor) process, which comprises an auxiliary current control circuit and a core current control circuit, and is characterized in that the auxiliary current control circuit comprises a first auxiliary circuit and a second auxiliary circuit; the first auxiliary circuit and the second auxiliary circuit have the same structure and are symmetrically arranged on the left and right sides of the core current control circuit. The problems of large output parasitic capacitance, limited circuit speed, high power consumption and large circuit complexity caused by multi-mode multiplexing realized through module parallel connection in the prior art are solved.