133 results about "Cmos process" patented technology

The invention relates to the technical field of radio frequency integrated circuits, and discloses a dynamic bias C-type voltage-controlled oscillator based on a CMOS (complementary metal oxide semiconductor) process, the voltage-controlled oscillator adopts a C-type structure, a cross-coupled network adds two resistors and a capacitor on the basis of a cross-coupled transistor, a circuit works in the C type by adjusting bias voltage at a resistor end, and the voltage-controlled oscillator works in the C type. The C-type voltage-controlled oscillator, a tail current source, a variable capacitance network, a switched capacitor array and a fixed LC resonance network form a core structure of the C-type voltage-controlled oscillator capable of numerical control tuning and voltage-controlled tuning, so as to determine the working frequency of the circuit and realize numerical control and voltage-controlled tuning functions; and the operational amplifiers with two bandwidth modes are introduced, so that the problem of difficult oscillation starting is solved, and the oscillation starting speed and the phase noise performance in a stable state are considered at the same time.

The invention relates to the technical field of microelectronics and MEMS manufacturing, in particular to a bulk acoustic resonator with a double-layer piezoelectric film and a preparation method thereof, according to the method, a heterogeneous integrated key structure is formed by a first piezoelectric layer and a second piezoelectric layer which are deposited on the two sides of a middle electrode layer respectively, the physical and process limits of a single-layer piezoelectric film FBAR are broken through, the high-frequency band is improved, and the high-frequency band is improved. A wider bandwidth is realized; middle electrode layer tuning is combined with back silicon through hole leading-out, front routing inductance is eliminated, and the low-loss characteristic of the filter under high frequency is guaranteed; the self-heating problem under large bandwidth and high power is effectively inhibited through heat dissipation integrated packaging, and the power bearing capacity is improved; the method is compatible with a CMOS (complementary metal oxide semiconductor) process and can be directly embedded into an existing production line, so that the volume is further reduced while the bulk acoustic wave resonator with the double-layer piezoelectric film can effectively cover a frequency band of more than 3GHz, and the problem that a single-layer piezoelectric film and a matched process thereof cannot meet the requirements of a next-generation radio frequency front end on high frequency, large bandwidth, high power and wafer-level packaging is solved.

The application relates to a gallium nitride epitaxial structure forming method and a semiconductor device. The method comprises the following steps: sequentially forming a buffer layer, an intrinsic GaN layer and an AlGaN layer on a substrate; growing a P-type doped GaN epitaxial layer on the AlGaN layer, controlling the doping concentration and thickness of the P-type GaN layer, performing N-type ion implantation on the P-type GaN layer, controlling the implantation depth in the range of 20nm-30nm, and then performing annealing. In another mode, the AlGaN layer is subjected to P-type ion implantation before the P-type GaN layer is grown to form an asymmetric P-type doped area, and then annealing is performed, and the implantation area is still P-type after annealing by controlling the implantation dose. In the semiconductor device, the contact layer is obtained by patterning the P-type GaN layer, and the P-type doped area with the highest doping concentration or the largest doping area is arranged at the position of the contact layer. The gate breakdown voltage can be improved, the threshold voltage can be stabilized, the low on-resistance can be maintained, and the CMOS process compatibility can be realized.

The application discloses a reset pulse width adjustable Timer circuit and a driver, and realizes an effective method for adjusting the reset pulse width based on a CMOS process technology.The reset pulse width adjustable Timer circuit comprises a state indication module, a current source module, a charge and discharge module and a comparator module for realizing the adjustable pulse width.The source voltage comparison circuit can effectively determine the end time of the reset signal pulse by the comparison result of the comparison voltage and the threshold value of the Timer, so that the pulse width of the reset signal is adjustable, the precision of the Timer timing and resetting is greatly improved, the problem that the Timer may be abnormally stopped and the abnormal situation may be missed due to the fixed pulse width of the reset signal of the traditional Timer structure after the timing period is accumulated is solved, and the reliability and stability of the synchronous rectification driver in the isolated DC / DC power supply are improved.

Techniques of integrating lateral HBT devices into a silicon on insulator (SOI) CMOS process. Similar approaches could also be applied to Fin Field-Effect Transistors (FinFETs). A first technique makes use of a CMOS replacement gate process that is typically associated with a partially depleted SOI (PDSOI) or fully depleted SOI (FDSOI) process. A second technique is independent of the CMOS process. Both techniques can accommodate silicon germanium (SiGe) and / or III-V materials, include a self-aligned base contact, and can be used to construct both NPN and PNP transistors with varied peak fT and breakdown voltages.

This invention discloses a method for controlling the polarization reversal characteristics of hafnium-based ferroelectric thin films through surface ion treatment, relating to the field of ferroelectric memory device technology. The method includes: providing a substrate; forming a hafnium-based ferroelectric thin film on the substrate; and after rapid thermal annealing of the hafnium-based ferroelectric thin film, introducing control ions onto the film surface through a surface ion treatment process to control the polarization reversal characteristics. The surface ion treatment process includes electrochemical treatment or plasma treatment, and the control ions include one or more of halide ions, hydrogen ions, hydroxide ions, sulfur-containing ions, and nitrogen-containing ions. This invention achieves effective control of the surface electric field distribution and polarization reversal barrier of the hafnium-based ferroelectric thin film through surface ion treatment, significantly reducing the coercive field and optimizing polarization stability, enabling ferroelectric domains to flip at lower voltages. This method is simple, low-cost, and compatible with CMOS processes, making it suitable for fabricating high-performance, low-power ferroelectric memory devices.

The application discloses a low-power bandgap reference current source circuit and a control method, and the circuit comprises a current mode bandgap circuit, an error amplifier input stage circuit, a threshold modulation circuit and a current mirror circuit; the current mode bandgap circuit is internally provided with an error amplifier OPAMP and a proportional resistance network; the error amplifier input stage circuit is a PMOS pair tube input stage circuit; the threshold modulation circuit is a source-liner forward bias threshold modulation circuit, which is used for forward biasing the threshold voltage of all PMOS tubes in the low-power bandgap reference current source circuit and enabling the NMOS tube connected with the error amplifier OPAMP output stage to work in a saturation region; and the current mirror circuit is a series diode compensation method current mirror circuit structure. The application is compatible with a standard CMOS process, realizes sub-1V low voltage, micro-nano ampere level low power consumption, high-precision low-noise small area effect, solves various technical pain points of a traditional scheme, and has excellent application prospects in a wearable device power management system.

The application discloses a parallel polynomial gradient calculation system and method based on a CMOS nerve synapse transistor, and relates to the technical field of calculation systems.The parallel polynomial gradient calculation system based on the CMOS nerve synapse transistor adopts a basic calculation unit containing at least one CMOS transistor, and configures the CMOS transistor to exhibit the dual-mode characteristics of neuron behavior and synapse behavior in a floating substrate operation mode, and meanwhile, combines a parallel array architecture, so that the application realizes a neuromorphic calculation hardware based on a standard CMOS process, utilizes mature CMOS manufacturing technology, avoids special materials and post-integration processes required by emerging devices such as memristors, thereby improving the manufacturability and yield of the system, and reducing production costs.Meanwhile, the inherent device consistency and long-term stability of the CMOS transistor effectively overcome the problems of large differences between devices and state drift in the memristor scheme, and realize high-precision polynomial gradient calculation.

According to the photodiode structure, the preparation method thereof and the CMOS image sensor, the perovskite / silicon heterojunction is constructed in the photodiode structure, and the spectral response range is remarkably expanded by using the high absorption coefficient of perovskite in an ultraviolet-visible region and the light absorption advantage of silicon in a near-infrared region; after photons irradiate on the silicon and the perovskite light absorption layer to excite and generate photo-induced electron-hole pairs, holes in the perovskite light absorption layer are extracted by the photo-induced hole transport layer, photo-induced electrons enter the N-well region through the electron transport layer, the photo-induced holes in the silicon diffuse and drift to the P-type substrate, and the photo-induced electrons are collected and temporarily stored in the N-well region; the compound probability of photon-generated carriers is effectively reduced, the photoelectric response speed is increased, the preparation process is simple, the method can be compatible with an existing CMOS process technology, large-area manufacturing is easy to achieve, the manufacturing cost is reduced, and the method has great significance in promoting development of a next-generation wide-spectrum and high-sensitivity image sensor.

This invention discloses a radio frequency millimeter-wave phase-to-voltage converter, belonging to the field of radio frequency microwave integrated circuit technology. The converter includes: a first and second frequency divider chain for dividing two input signals to achieve phase compression; a first and second quadrature generator for providing a -90° linearized bias; a three-state coupling network connected between the two frequency divider chains to eliminate phase mode ambiguity introduced by the frequency dividers through reconfigurable coupled phase; and a symmetrical phase detector for converting the linearized phase difference into a voltage signal output. This invention compresses the ±180° phase difference to a small angle range using phase compression technology, combined with linearized bias to allow the phase detector to operate in the linear region, and utilizes the three-state coupling network to achieve unambiguous detection across the entire 360° phase range. Implemented using a 40nm CMOS process, it requires no external clock, has no inductor design, a core area of ​​only 0.016mm², power consumption of 22mW, a response speed of 120ns, and a linearity of 1.05% FSR.

The invention relates to the technical field of integrated circuit design, in particular to a non-zero potential output level conversion circuit realized based on a CMOS (complementary metal oxide semiconductor) process, and a low-voltage differential circuit realizes conversion from a single-end low level to a differential level. The pre-stage level conversion circuit realizes conversion from a low level to a working IO level. The post-stage level conversion circuit realizes conversion of a process limit high level; and the voltage selection circuit controls a voltage selector through a signal output by the post-stage level conversion circuit so as to realize switching between the working IO voltage and the process limit voltage. Through a three-stage gradient voltage distribution architecture and a dynamic substrate bias technology, digital low voltage passes through a level conversion and voltage selection circuit, a special level conversion circuit for outputting low level exceeding zero potential is realized, and the working voltage of all MOS transistors is ensured to be strictly lower than a process breakdown threshold. The method can be applied to burning of a one-time programmable chip in a system on chip and other scenes needing non-zero low potential and process limit high voltage switching.

The present invention provides a phase shifter that can be manufactured using a CMOS process, exhibits low optical propagation loss, can maintain refractive index changes without power supply, and allows for the resetting of those refractive index changes. [Solution] The phase shifter 100 of the present invention comprises an optical waveguide 101 composed of a core 105 and a cladding 106 surrounding the core 105, a substrate 102 on which the optical waveguide 101 is mounted, a heating means 103 for heating the core 105, and an ultraviolet irradiation means 104 for irradiating the core 105 with ultraviolet U, wherein the core 105 mainly contains silicon nitride, and the density of silicon dangling bonds of silicon nitride is 10 in terms of spin density 18 cm -3 The above 10 20 cm -3 The following applies:

This application belongs to the field of semiconductor device technology, specifically disclosing a threshold switching device based on a p-x-n structure and its fabrication method. In the threshold switching device, the first polar semiconductor layer and the second polar semiconductor layer have opposite polarities, being one of an n-type semiconductor layer and a p-type semiconductor layer, respectively. The charge trapping layer contains trap energy levels, used to achieve volatile threshold switching behavior through a charge trapping and releasing mechanism under voltage. The lower electrode and the upper electrode are used to apply voltage. The device fabricated in this application is fully compatible with CMOS processes and possesses both self-rectification capabilities and nanosecond-level fast switching characteristics.

According to the tensile strain germanium wafer on the glass substrate, the imaging chip and the forming method of the imaging chip, the acceptor substrate comprises the transparent glass substrate, the light transmittance of the short-wave infrared band is extremely high, light of the short-wave infrared band can reach the tensile strain germanium layer, the transparent glass substrate can also enable visible light to penetrate, and the imaging chip can be applied to the imaging chip. Visible light can also reach the tensile strain germanium layer. Light of more wavebands enters the tensile strain germanium wafer on the glass substrate through the transparent glass substrate, the tensile strain of the tensile strain germanium layer is further increased through direct wafer bonding operation, the response capacity to incident light is improved, and the wavelength response range of the tensile strain germanium wafer on the glass substrate is expanded to be within the range of 400 nm to 1700 nm. The wafer taking the transparent glass as the substrate is large in size and low in batch production cost, can be highly compatible with a CMOS (complementary metal oxide semiconductor) process production line, can overcome the defects of fragility, high cost and the like of a bulk germanium material, and improves the quality of the tensile strain germanium wafer on the glass substrate.

The application discloses a thermal type wind speed and direction sensor based on thermistors and thermoelectric piles and a working method thereof. The sensor structure comprises a thermistor, a thermoelectric pile, a heating resistor, a silicon substrate and a measurement and control IC. The heating resistor is square and located at the center of the substrate. Four thermistors and a thermoelectric pile parallel to the side edges of the heating resistor are distributed on the four sides of the heating resistor. The four parallel thermistors are connected to form a Wheatstone full-bridge temperature measurement structure, and the two parallel thermoelectric piles are connected to form a thermoelectric pile temperature measurement structure. The measurement and control IC is distributed at the four corners of the substrate and connected to the temperature measurement structure formed by the heating resistor, the thermoelectric pile and the thermistor, and is used for driving the detection structure and processing the output signal thereof. The application adopts a CMOS process, and the thermistor and the thermoelectric pile structure are redundant to each other, so that the wind speed and direction detection precision can be improved.

The application discloses a multi-channel VLC system based on a CMOS process, comprising a transmitting module and a receiving module; the transmitting module comprises a vertical polarization transmitting submodule and a horizontal polarization transmitting submodule; the receiving module comprises a vertical polarization receiving submodule and a horizontal polarization receiving submodule; the vertical polarization transmitting submodule emits three routes of non-polarized light emitted by a first RGB-LED after vertical polarization dispersion, parallel conversion and emission, and the vertical polarization receiving submodule forms three routes of analog electric signals after filtering of the received multicolor visible light signals by a metasurface; the horizontal polarization transmitting submodule emits three routes of non-polarized light emitted by a second RGB-LED after horizontal polarization dispersion, parallel conversion and emission, and the horizontal polarization receiving submodule converts the received multicolor visible light signals into three routes of analog electric signals after filtering by a metasurface; and six routes of analog electric signals are converted into one route of digital electric signal output. The application can realize clear and complete multi-channel high-speed communication.

The invention relates to the technical field of optical waveguides, and particularly discloses a manufacturing method of an optical waveguide end face coupler and the optical waveguide end face coupler, in the process of manufacturing the optical waveguide end face coupler, a dielectric material, namely silicon oxynitride or silicon oxycarbide, is deposited on a siliceous substrate wafer through a CVD method in a CMOS process, in the manufacturing process, the manufacturing process can be connected with the manufacturing process of an electronic device, the high-refractive-index gradient layers of the lower gradient layer, the middle gradient layer and the upper gradient layer and the core layer are finally manufactured, and the effective refractive index is linearly changed in cooperation with a common insulating medium in the semiconductor technology, namely, the low-refractive-index gradient layers prepared from silicon dioxide, and the effective refractive index is changed in a linear mode. And based on the characteristic that the refractive indexes of the silicon oxynitride and the silicon oxycarbide are adjustable, the optical waveguide end face coupler which can adapt to a semiconductor photon-electron heterogeneous integrated scene, can be compatible to the manufacturing process of an electronic device and has a wide-range core cladding refractive index difference is finally obtained.

A method for fabricating a semiconductor device is described. Generally, the method includes forming a customizable oxide-nitride (ONO) stack on a substrate in an in situ atomic layer deposition (ALD) tool or chamber. A radical oxidation or oxide deposition process step is performed to form a tunnel dielectric layer overlying the substrate. A silicon nitride deposition process step is also performed to form a multilayer charge trapping (CT) layer, and at least some of the process parameters of the silicon nitride deposition process step are adjusted in forming first and second CT sublayers of the multilayer CT layer. A subsequent radical oxidation or oxide deposition process step is performed in the ALD tool to form a blocking dielectric layer overlying the multilayer CT layer.

The invention relates to the technical field of integrated circuits and electronic circuits, in particular to a multi-mode multiplexing differential driving circuit based on a CMOS (complementary metal oxide semiconductor) process, which comprises an auxiliary current control circuit and a core current control circuit, and is characterized in that the auxiliary current control circuit comprises a first auxiliary circuit and a second auxiliary circuit; the first auxiliary circuit and the second auxiliary circuit have the same structure and are symmetrically arranged on the left and right sides of the core current control circuit. The problems of large output parasitic capacitance, limited circuit speed, high power consumption and large circuit complexity caused by multi-mode multiplexing realized through module parallel connection in the prior art are solved.

The application discloses a low-power-consumption high-gain low-noise amplifier based on a CMOS process, comprising: an input stage circuit and an output stage circuit; the input stage circuit comprises: a first transformer, a second transformer, a feedback resistor Rf, a first transistor M1 and a first capacitor C1; and the output stage circuit comprises: a second transistor M2, a third transistor M3, a second capacitor C2, a third capacitor C3, a third transformer, a first inductor L1, a second inductor L2, a third inductor L3 and a first resistor R1. The LNA can realize good performance indexes such as low noise, high gain and low power consumption under the premise of guaranteeing to meet the requirement of realizing good input and output port impedance matching within a wide bandwidth.

A method of depositing an AlN thin film according to an embodiment of the disclosure comprises: a step of forming an insulating layer on a base substrate; and a step of depositing an AlN thin film on the insulating layer through a sputtering process, wherein the step of depositing the AlN thin film is performed through a continuous deposition type, at lower than a CMOS-compatible process temperature and in a state of applying a bias positive voltage to the base substrate such that the AlN thin film has an adjustable deposition thickness. Therefore, an embodiment of the disclosure is advantageous in that an AlN thin film having excellent piezo characteristics can be obtained at a low process temperature compatible with a CMOS process.

The application discloses a phase shifter (100), an optical phased array (10) and a preparation method of the optical phased array (10). The phase shifter (100) comprises a signal generator (110) and a waveguide (120). The signal generator (110) is used for generating an electromagnetic wave signal. The waveguide (120) is located on a transmission path of the electromagnetic wave signal, so that the phase of light transmitted in the waveguide (120) under the action of the electromagnetic wave signal can be changed. The preparation material of the waveguide (120) comprises aluminum nitride. By setting the preparation material of the waveguide (120) as aluminum nitride, the aluminum nitride is compatible with a CMOS process and can be deposited on a substrate (130) in the form of a thin film through a magnetron sputtering method. The formed aluminum nitride thin film has a crystal lattice structure and an electro-optic effect, and can realize a faster phase modulation speed than a phase modulation speed based on a thermo-optic effect.

The embodiment of the specification provides a low-temperature drift coefficient oscillator circuit, comprising: a first charge-discharge capacitor CL and a second charge-discharge capacitor CR connected in parallel at a first input end of a latch circuit, current input ends of first and second current steering switches are connected to a current output end of a bias current generation circuit, the current input ends of the first and second current steering switches are connected to the first and second input ends of the latch circuit respectively, controlled input ends of the first and second current steering switches are connected to output ends of a second buffer and a first buffer respectively, input ends of the first and second buffers are connected to first and second output ends of the latch respectively, and output ends of the first and second buffers are used for outputting complementary first and second square wave signals CKB and CK. The on-chip oscillator is realized by using a standard CMOS process, and the production cost is reduced.

This invention relates to the field of power management technology. This application discloses a low-dropout voltage regulator circuit based on low-voltage devices adapted to high-voltage power supplies. To solve the problems of existing solutions requiring high-voltage devices, high cost, and inability to reuse low-voltage designs, this invention uses only low-voltage process devices. Overvoltage protection is achieved through a common-gate transistor with fixed gate bias, clamping the high-voltage input to a safe range. The control signal voltage is limited through a voltage divider clamping network. During power down, a voltage divider design is used to simultaneously turn off the power supply and ground switches. A pull-up start-up circuit to prevent degeneracy is also integrated. This circuit can directly convert a high-voltage input into a stable low-voltage output, driving ordinary low-voltage circuits without any modification, realizing the direct reuse of low-voltage designs in high-voltage scenarios. This solution has the advantages of extremely low cost, high security, low power consumption, reliable startup, and full compatibility with standard low-voltage CMOS processes, greatly expanding the application boundaries of low-voltage processes.

The application discloses a preparation method of a nano or atomic scale spin valve, which comprises the following steps: preparing a buffer layer and a metal electrode on a substrate surface, preparing a magnetic metal point contact device based on a proximity effect photolithography method, placing the device on a vacuum probe station, preparing an atomic scale point contact structure by using a current feedback control method, and preparing a magnetic tunnel junction with a magnetic resistance of up to 40% by natural oxidation, so as to obtain the nano or atomic scale spin valve. The preparation method can effectively control the contact width of the atomic contact point, and compared with the prior art, the complexity of the spin valve structure is reduced, and the device power consumption is reduced to a certain extent. The preparation method is simple, the magnetic tunnel junction has a large magnetic resistance, and is compatible with a traditional CMOS process, so that an advantage is provided for the integration of subsequent devices.

The application provides a preparation method of a hole spin quantum bit, which comprises the following two steps: preparing a tilted quantum well structure based on a CMOS process, and realizing growth of a quantum well in a [110] direction by controlling a tilt angle, wherein the quantum well structure is a P-type doped germanium quantum well; and preparing a two-dimensional gate-controlled quantum dot in the quantum well structure based on an electric dipole spin resonance (EDSR) technology, so as to realize a high-quality hole spin quantum bit. Compared with a traditional quantum well grown in a [100] direction, the quantum well in the [110] growth direction has the largest linear Rashba spin-orbit coupling effect and can provide the fastest Rabi spin flip. The application overcomes the difficulty of directly growing the [110] quantum well on a plane by designing the tilted quantum well, and provides a brand-new solution for realizing the high-quality hole spin quantum bit.

The application discloses a kind of high-power radio frequency magnetron sputtering patterning preparation CoTaZr film and high-frequency performance regulation process, belongs to soft magnetic film preparation technical field.The application is with high-power radio frequency magnetron sputtering as core deposition process, stripe pattern is as characteristic regulation means, and the composition ratio of preparation patterned CoTaZr amorphous soft magnetic film is Co:89 at.%;Ta:5 at.%;Zr:6 at.% on Si (111) substrate;By 140W high sputtering power optimization film intrinsic structure and morphology, in combination with the mask plate induced shape anisotropy that stripe spacing is fixed at 50 μm, width 30 μm~70 μm, realize the synergic regulation of film high-frequency performance, surface morphology and resistivity.The application is carried out at room temperature, and compatible with standard CMOS process, the film cutoff frequency is continuously regulated at 2.19~3.06 GHz, saturation magnetization is stable at 12000~12500 Gs, initial permeability is 191~371 adjustable, surface roughness is 0.401~1.284 nm, resistivity keeps low loss characteristics, solve the problem that film morphology, resistivity and high-frequency performance are difficult to take into account in traditional process, can meet the application demand of GHz frequency band on-chip integrated inductor, 5G communication module and other high-frequency devices on magnetic core material.

The application relates to a CMOS voltage-controlled oscillator applied to an anti-interference unmanned aerial vehicle millimeter wave radar and belonging to the millimeter wave radar design field, which comprises a resonance circuit, a negative resistance active circuit and two switch circuits with the same structure. The resonance circuit comprises a switch capacitor, a direct-current isolation capacitor, a resonance capacitor, a grounding resistor, a tuning resistor and a resonance inductor; the negative resistance active circuit comprises a cross-coupled MOS pair and a current source; and the switch circuits each comprise a switch MOS, a grounding resistor and a switch-coupled inductor. The application utilizes a dual-phase transformer structure to make the resonance inductor and the switch-coupled inductor mutually inductive, thereby changing the inductance value of the resonance inductor and realizing frequency band switching; the combination of switch capacitor conduction and shutdown and switch-coupled inductor conduction and shutdown is used to realize VCO bandwidth tuning; the CMOS process is adopted for design, and the VCO is miniaturized and integrated. While the performance of the voltage-controlled oscillator and the layout area are ensured, a full-frequency-band wide-band tuning range is realized, thereby improving the detection capability and resolution of the millimeter wave radar, realizing frequency hopping communication and spread spectrum communication of the unmanned aerial vehicle, and effectively improving the anti-interference capability and safety of the unmanned aerial vehicle.

The invention relates to a gallium nitride epitaxial structure forming method and a semiconductor device. The method comprises the steps that a buffer layer, an intrinsic GaN layer and an AlGaN layer are sequentially formed on a substrate; a P-type doped GaN epitaxial layer grows on an AlGaN layer, the doping concentration and thickness of the P-type doped GaN epitaxial layer are controlled, N-type ion implantation is carried out on the P-type GaN layer, the implantation depth is controlled within the range of 20 nm to 30 nm, and then annealing is carried out. In the other mode, before the P-type GaN layer grows, P-type ion implantation is carried out on the AlGaN layer to form an asymmetric P-type doped region, then annealing is carried out, and the implantation region after annealing is still P-type by controlling the implantation dosage. In the semiconductor device, the contact layer is obtained by patterning the P-type GaN layer, and the position, corresponding to the contact layer, of the barrier layer is provided with a P-type doped region with the highest doping concentration or the maximum doping area. The gate breakdown voltage can be improved, the threshold voltage can be stabilized, the low on-resistance can be maintained, and the CMOS process compatibility can be realized.

The invention provides a silicon electron spin quantum bit quantum device compatible with a CMOS process and capable of resisting interface disorder and a preparation method thereof, the preparation method comprises the steps of providing a substrate, forming a silicon quantum well on the substrate, and forming at least one group of metal electrodes on the silicon quantum well, and the interior of the silicon quantum well comprises a first interval for forming grid control quantum dots, and the second section is used for forming shear strain in the preset direction in the first section. Different voltages are synchronously applied to the metal electrode, so that in the process of forming the grid-control quantum dot grid in the first interval, the grid-control quantum dot grid is synchronously influenced by the cutting strain continuously provided by the second interval, and therefore, the grid-control quantum dot can obtain relatively strong energy valley splitting resistant to interface disorder; and thus, the preparation of the high-quality silicon electron spinning quantum bit with meV-magnitude energy valley splitting and interface disorder resistance is realized.