100 results about "Subthreshold swing" patented technology

A Ferroelectric tunnel FET switch as ultra-steep (abrupt) switch with subthreshold swing better than the MOSFET limit of 60 mV/decade at room temperature combining two key principles: ferroelectric gate stack and band-to-band tunneling in gated p-i-n junction, wherein the ferroelectric material included in the gate stack creates, due to dipole polarization with increasing gate voltage, a positive feedback in the capacitive coupling that controls the band-to-band (BTB) tunneling at the source junction of a silicon p-i-n reversed bias structure, wherein the combined effect of BTB tunneling and ferroelectric negative capacitance offers more abrupt off-on and on-off transitions in the present proposed Ferroelectric tunnel FET than for any reported tunnel FET or any reported ferroelectric FET.

The invention provides a heterojunction carbon nano-tube field effect transistor of which a subthreshold swing is smaller than 60 millivolt/magnitude in the room temperature and a preparation method thereof. The device uses the semiconductor carbon nano-tube as the active layer, the heterojunction formed by the graphene layer and the semiconductor carbon nano-tube is used as the source end of the device, the gate medium and the gate electrode modulate the carbon nano-tube channel and the graphene/carbon nano-tube junction at the same time, so that the turn-off of the transistor is accelerated by using the character that the graphene/carbon nano-tube junction barrier is modulated by the gate voltage. The transistor can control the polarity through the selection of the source-drain metal, namely the metal of high power function is used as the source-drain electrode for realizing the p-type field effect transistor, and the metal of low power function is used as the source-drain electrode for realizing the n-type field effect transistor.

A two-dimensional (2D) heterojunction interlayer tunneling field effect transistor (Thin-TFET) allows for particle tunneling in a vertical stack comprising monolayers of two-dimensional semiconductors separated by an interlayer. In some examples, the two 2D materials may be misaligned so as to influence the magnitude of the tunneling current, but have a modest impact on gate voltage dependence. The Thin-TFET can achieve very steep subthreshold swing, whose lower limit is ultimately set by the band tails in the energy gaps of the 2D materials produced by energy broadening. These qualities in turn make the Thin-TFET an ideal low voltage, low energy solid state electronic switch.

The invention discloses an indium-doped N-type organic thin-film transistor and a preparation method thereof. The N-type organic thin-film transistor has a top gate bottom contact structure. The preparation method comprises the following steps: firstly, preparing a layer of gold on a glass substrate through a mask plate to serve as a source electrode and a drain electrode; secondly preparing a layer of indium on a gold electrode to serve as a doped layer; thirdly forming an N-type organic semiconductor active layer on the surface of a sample subjected to electrode preparation by using a sol-gel method; fourthly spin-coating an active layer with a layer of dielectric material to serve as an insulating layer; and finally, preparing aluminum on the surface of the insulating layer through the mask plate to form a gate electrode. Compared with a traditional organic thin-film transistor, the organic thin-film transistor prepared by the method has the advantages that the switching ratio and the carrier mobility are obviously improved, and the subthreshold swing amplitude and the threshold voltage of a device are greatly reduced. The method improves the electrical property of the N-type organic thin-film transistor with the top gate bottom contact structure, and has the characteristics of low cost, simple process steps and wide applicability to the N-type organic thin-film transistor.

The present invention provides an ultra steep average subthreshold swing nano wire tunneling field effect transistor and a method for preparing the same which belong to the field effect transistor logic device field of the CMOS ultra large scale integration (ULSI). The tunneling field effect transistor adopts a nano wire structure of core-multilayered shell, and the material band gap of a multilayered shell part is increased continuously along the radius direction of the nano wire. According to the present invention, a subthreshold slope degradation phenomenon in a device transfer characteristic can be restrained effectively, at the same time, an average subthreshold slope of the tunneling field effect transistor is reduced remarkably, and a more steep minimum subthreshold slope is kept.

The invention belongs to the technical field of semiconductor devices, and particularly relates to a U-shaped channel tunneling transistor with a laminated structure and a preparation method thereof. According to the invention, a highly doped silicon layer of which the doping type is opposite to that of a SiGe source area is formed under the SiGe source area of the tunneling transistor by an epitaxial growth method; and the forbidden bandwidth of the SiGe is narrower than that of silicon, so that the band bending degree between the source area and a channel region can be improved, then the length of tunneling can be reduced and the tunneling efficiency is improved. The U-shaped channel tunneling transistor with the laminated structure which is provided by the invention can substantially improve firing current and reduces subthreshold swing under the circumstance that shutdown current is not influenced.

A highly responsive semiconductor device in which the subthreshold swing (S value) is small and reduction in on-current is suppressed is manufactured. A semiconductor layer in which a thickness of a source region or a drain region is larger than that of a channel formation region is formed. A semiconductor layer having a concavo-convex shape which is included in the semiconductor device is formed by the steps of forming a first semiconductor layer over a substrate; forming a first insulating layer and a conductive layer over the first semiconductor layer; forming a second insulating layer over a side surface of the conductive layer; forming a second semiconductor layer over the first insulating layer, the conductive layer and the second insulating layer; etching the second semiconductor layer using a resist formed partially as a mask; and performing heat treatment to the first semiconductor layer and the second semiconductor layer.

The invention discloses a low off-state current tunneling field effect transistor, comprises a source region, a channel region, a drain region and a first gate dielectric layer, wherein the channel region is provided with the first gate dielectric layer, the first gate dielectric layer is provided with a first grid, the source region is arranged under the channel region and close to the lower part of the channel region, the source region is provided with a source electrode, the drain region is arranged at one side of the channel region, a drain electrode is arranged at the right end of the drain region, an adjusting region is arranged between the channel region and the drain region, a transition region is arranged between the channel region and the adjusting region, a second gate dielectric layer is arranged on the adjusting region and is provided with a second grid, the first grid and the second grid are connected together through a lead to function as the grid of the whole field effect transistor, and an isolation region is arranged on the transition region. Since the adjusting region is introduced between the channel region and the drain region, the equivalent resistance of the adjusting region functions so that the low off-state current tunneling field effect transistor can obtain lower subthreshold swing and quiescent dissipation, thus improving the performance of the low off-state current tunneling field effect transistor.

Provided is a transistor containing a semiconductor with low density of defect states, a transistor having a small subthreshold swing value, a transistor having a small short-channel effect, a transistor having normally-off electrical characteristics, a transistor having a low leakage current in an off state, a transistor having excellent electrical characteristics, a transistor having high reliability, or a transistor having excellent frequency characteristics. An insulator is formed, a layer is formed over the insulator, oxygen is added to the insulator through the layer, the layer is removed, an oxide semiconductor is formed over the insulator to which the oxygen is added, and a semiconductor element is formed using the oxide semiconductor.

A semiconductor device having a highly responsive thin film transistor (TFT) with low subthreshold swing and suppressed decrease in the on-state current and a manufacturing method thereof are demonstrated. The THF of the present invention is characterized by its semiconductor layer where the thickness of the source region or the drain region is larger than that of the channel formation region. Manufacture of the TFT is readily achieved by the formation of an amorphous semiconductor layer on a projection portion and a depression portion, which is followed by subjecting the melting process of the semiconductor layer, resulting in the formation of a crystalline semiconductor layer having different thicknesses. Selective addition of impurity to the thick portion of the semiconductor layer provides a semiconductor layer in which the channel formation region is thinner than the source or drain region.

The present invention discloses a gate-all-around anti-irradiation MOS field effect transistor based on a 65 nm technology for mainly solving the problems of threshold voltage drift, subthreshold swing degeneration and off-state leakage current degeneration of a conventional 65 nm MOS field effect transistor under a total dose radiation environment. The gate-all-around anti-irradiation MOS field effect transistor based on the 65 nm technology comprises a P-type substrate (1) and an epitaxial layer (2) located on the substrate, a drain region (3) is arranged in the middle of the epitaxial layer, and a grid (4) is arranged above the epitaxial layer adjacent to the periphery of the drain region (3). Light doping source drain regions (5) are arranged in the epitaxial layer below the boundaries at the inner and outer sides of the grid, an area between the light doping source drain regions forms a channel, and a source region (6) is arranged in the epitaxial layer adjacent to the periphery of the grid. An isolating groove (7) is arranged in the epitaxial layer adjacent to the periphery of source region, and a grating ring, a source ring and an isolating groove ring sleeve structure surrounding the exterior of an active region orderly are formed. The gate-all-around anti-irradiation MOS field effect transistor based on the 65 nm technology of the present invention enables the device anti-total dose radiation capability to be improved, and can be used to manufacture a large-scale integrated circuit.

The present invention discloses an organic light-emitting display device and a manufacturing method thereof. The organic light-emitting display device includes a switching thin film field effect transistor, a driving thin film field effect transistor, and a storage capacitor connected with the switching thin film field effect transistor and the driving thin film field effect transistor; the switching thin film field effect transistor is provided with a first active layer for reducing the subthreshold swing of the transfer characteristic curve of the switching film field effect transistor; and the driving thin film field effect transistor is provided with a second active layer for increasing the subthreshold swing of the transfer characteristic curve of the driving thin film field effect transistor. According to the organic light-emitting display device of the invention, fast switching on and switching off of the switching thin film field effect transistor and slow debugging of the grayscale of an OLED (Organic Light Emitting Diode) by the driving thin film field effect transistor can be simultaneously realized.

Sol-gel-processed thin-film transistors (TFTs) with amorphours Y—In—Zn—O (YIZO) as an active layer are fabricated with various mole ratios of Y, which indicates that Y³⁺ could play the role of carrier suppressor in InZnO (IZO) systems and reduce off current of YIZO-TFT and its channel mobility, threshold voltage, subthreshold swing voltage, and on/off ratio.

The invention discloses an array substrate, a preparation method of the array substrate, a display panel, and a display device. The array substrate is characterized in that the thickness of a gate oxidation layer of a driving transistor is larger than the thickness of a gate oxidation layer of a switching transistor. According to I=K(Vgs-Vth)<2> and (the formula is as shown in the description), the fact that the thickness of the gate oxidation layer of the driving transistor is larger than the thickness of the gate oxidation layer of the switching transistor indicates that K of the driving transistor is smaller than K of the switching transistor, so that current changes of the driving transistor with voltages are smaller, i.e., subthreshold swing requirements are higher, which facilitatesbetter grayscale control, and current changes of the switching transistor with the voltages are larger, i.e., subthreshold swing requirements are lower, which ensures good switching performance; and therefore, effective grayscale and switching control in the display panel can be simultaneously achieved.

The invention provides a thin-film transistor, a manufacturing method of the thin-film transistor, an array substrate and a display device. The manufacturing method of the thin-film transistor comprises the steps that a grid, a gate insulator, an active area, a source and a drain are formed on the substrate, the active area is made of a ZnON material, and nitrogen ions are implanted in the active area while the active area is formed, so that the subthreshold swing of the thin-film transistor is smaller than or equal to 0.5 mV/dec. According to the manufacturing method, as the nitrogen ions are implanted in the active area while the active area is formed, the concentration of the nitrogen ions, at the effective electricity conducting position, in the active area can be greatly improved, when the thin-film transistor works, nitrogen, lost due to the diffusion effect, in the active area can be supplemented sufficiently, the migration rate of nitrogen vacancy in the active area can be greatly increased, namely, the migration rate of current carriers in the active area is greatly increased, the subthreshold swing of the thin-film transistor is further reduced, and the semi-conductor property of the thin-film transistor is improved.

The invention discloses an SOI (silicon on insulator) substrate based ring-gate radiation-proof MOS (metal oxide semiconductor) field-effect transistor. The field-effect transistor comprises an Si substrate (1), a buried oxide layer (2) located in the Si substrate (1) and an epitaxial layer (3) on the Si substrate (1), a drain region (5) is arranged in the middle of the epitaxial layer, a ring gate (4) is arranged over the epitaxial layer and next to the outer boundary of the drain region, lightly doped source drain regions (7) are arranged in the epitaxial layer under the edges of the inner and outer sides of the ring gate (4), and a region between the lightly doped source drain regions forms a channel; a ring source active region (6) is arranged in the epitaxial layer next to the outer edge of the gate, and a ring isolation channel (8) is arranged in the epitaxial layer adjacent to the periphery of the ring source active region (6) and is of a loop structure comprising a gate ring, a source ring and an isolation channel ring sequentially encircling the outside of the passive region. By the field-effect transistor, threshold voltage shift and subthreshold swing degradation are inhibited, total dose radiation performance tolerance of the device is enhanced, and the field-effect transistor is used for preparation of large-scale integrated circuits.

An embodiment of the invention discloses a TFT preparation method, a TFT, an array substrate and a display device. The TFT preparation method comprises the steps of: forming a buffer layer, a polysilicon layer, a gate insulating layer, a source layer, a drain layer and a gate layer on a substrate, wherein the polysilicon layer is formed on the buffer layer, the source layer and the drain layer areformed on both sides of the polysilicon layer, and the gate insulating layer is formed on the polysilicon layer, the source layer and the drain layer; and performing primary ion implantation on the polysilicon layer after the buffer layer and the polysilicon layer are formed on the substrate and before the gate insulating layer is formed on the substrate, so as to adjust a subthreshold swing to be not lower than a preset threshold value and enable a peak value of the implanted ion concentration falls in the buffer layer under the polysilicon layer. According to the TFT preparation method, adverse effect on other electrical characteristic parameters of the TFT cannot be caused under the condition of adjusting the subthreshold swing of the TFT, and the overall product performance of the TFTis improved.

The invention provides a ferroelectric /piezoelectric field effect transistor and a preparation method thereof. The iron/piezoelectric field effect transistor comprises a substrate, a source electrode, a drain electrode and a gate electrode. The gate electrode comprises silicon dioxide, a high dielectric layer, a piezoelectric material layer, a titanium nitride layer, a ferroelectric material layer and a tantalum nitride layer, which are sequentially stacked from bottom to top. The preparation method comprises the following steps: providing a silicon substrate, and doping P-type ions into thesilicon substrate to form a substrate; forming a source electrode and a drain electrode at two sides of the substrate; sequentially forming the silicon dioxide layer and the high dielectric layer between the source electrode and the drain electrode above the substrate; and sequentially forming the piezoelectric material layer, the titanium nitride layer, the ferroelectric material layer and the tantalum nitride layer on the high dielectric layer. Based on the field effect transistor, the ferroelectric material and the piezoelectric material are introduced into the gate electrode, and the negative capacitance effect of the ferroelectric material and the electrostrictive effect of the piezoelectric material are used for jointly achieving the voltage amplification function. The working voltage of the device is reduced, the subthreshold swing is reduced, the on/off speed of the device is improved, and the working power consumption is further reduced.