40 results about "Subthreshold swing" patented technology

The invention relates to the technical field of kits, in particular to a MoS2 back gate field effect transistor based on a wet transfer process and a preparation method of the MoS2 back gate field effect transistor. The MoS2 back gate field effect transistor is formed by sequentially arranging a silicon-based substrate, a SiO2 insulating layer, a MoS2 conducting channel layer and an Ag source drain electrode from bottom to top; a high-quality single-layer MoS2 thin film is prepared through a chemical vapor deposition (CVD) method, PMMA is adopted as a supporting layer, clean Van der Waals contact of the MoS2 thin film and a SiO2 / Si substrate is achieved through a wet transfer process of NaOH solution etching, deionized water cleaning and acetone stripping of the supporting layer, and finally a source electrode and a drain electrode are prepared by combining photoetching and thermal evaporation processes. According to the method, the problems of pollutant residues and traps of an interface between MoS2 and the substrate in the traditional process are effectively solved, the carrier mobility, transconductance and on-state current of the device are remarkably improved, the sub-threshold swing is reduced, and the method is suitable for manufacturing a two-dimensional material integrated circuit device with low power consumption and high performance.

Various embodiments disclosed presents pixel driver circuits that utilize integrated diode structures to enhance sub-threshold swing and modulate threshold voltage. Conventional transistor-only designs often encounter challenges in achieving precise control and efficiency, limited by their sub-threshold swing and voltage modulation capabilities. Various embodiments incorporate advanced MOSFETs in series with diodes without an additional mask and process knob, enabling advanced control over the LED current without a larger area penalty and less process variation with device sub-threshold engineering. Such transistor-diode configuration improves brightness, gray-scale accuracy, and overall display performance, leading to improved power efficiency, advanced display uniformity, and improved reliability for LED devices.

The invention relates to the field of semiconductor devices, in particular to an ultra-low sub-threshold swing transistor based on a hafnium-aluminum-oxygen ultra-thin matching layer film and a preparation method of the ultra-low sub-threshold swing transistor based on the hafnium-aluminum-oxygen ultra-thin matching layer film. And the driving capability and switching speed of the device are further improved. On the premise of ensuring stable characteristics of the ferroelectric film, a proper matching layer medium is introduced to achieve the purpose of reducing clockwise hysteresis caused by an interface state so as to further reduce total hysteresis, the introduced new matching layer Hf1-aAlaOb is compared with a common Al2O3 matching layer, nitridation process research is carried out, a capacitance matching medium most suitable for Zr1-xAlxOy is explored, and the performance of the ferroelectric film is improved. And the driving capability and switching speed of the device are further improved.

The invention provides a novel field effect transistor fused with a memristor and a preparation method of the novel field effect transistor, and belongs to the technical field of integrated circuit micro-nano electronic devices. A gate electrode on the substrate; the gate dielectric layer is located on the gate electrode; the drain electrode is located on the gate dielectric layer; the channel layer is located on the drain electrode; a source electrode and a first memristive electrode, wherein the source electrode and the first memristive electrode are both located on the channel layer; wherein the drain electrode is multiplexed as a second memristive electrode, the vertical projection of the first memristive electrode and the vertical projection of the drain electrode are at least partially overlapped, and the channel layer is arranged between the source electrode and the drain electrode and between the first memristive electrode and the drain electrode. The subthreshold swing limit of a traditional transistor is broken through, the power consumption of a device is effectively reduced, and the switching performance is improved.

A high-voltage transistor may include a composite gate dielectric layer having multiple regions with different dielectric constant values and / or a composite gate structure having multiple regions of different work function values. The composite dielectric layer having multiple regions with different dielectric constant values and / or the composite gate structure having multiple regions with different work functions increases the threshold voltage uniformity across a channel region of the high-voltage transistor. The increased threshold voltage uniformity may enable a low subthreshold swing and a low subthreshold off-stage current leakage to be achieved for the high-voltage transistor, which increases the operating efficiency of the high-voltage transistor and enables the size of the high-voltage transistor to be reduced without increasing (or with minimal increase to) the subthreshold swing and and / or the subthreshold off-stage current leakage of the high-voltage transistor.

The application discloses an equivalent sub-threshold swing regulation method of a single-gate transistor and a pixel circuit. The method comprises the following steps: obtaining a coupling control voltage based on a preset linear function relationship and a data voltage; coupling the coupling control voltage and the data voltage to obtain a coupling result; and providing the coupling result to a gate node of the single-gate transistor. The preset linear function relationship comprises a gain coefficient, and the gain coefficient is configured to program and regulate the equivalent sub-threshold swing of the single-gate transistor. Through the design of the preset linear function relationship between the data voltage and the coupling control voltage and the synergistic effect of circuit compensation, the high-precision uniformity control of the current under the low gray scale condition and the improvement of the high-resolution electroluminescent display quality are realized.

The invention discloses a high-performance two-dimensional transistor and a preparation method and application thereof, and relates to the technical field of semiconductor material manufacturing, and the structure of the transistor comprises a channel layer, a gate dielectric layer and an electrode assembly. Wherein the channel layer is made of a two-dimensional semiconductor material; the gate dielectric layer is made of a layered phosphorus gallium sulfide material; the electrode assembly comprises a grid electrode, a source electrode and a drain electrode; the channel layer and the gate dielectric layer are combined through Van der Waals force. The preparation method comprises the following steps: obtaining a two-dimensional material sheet through mechanical stripping, and sequentially stacking the two-dimensional semiconductor material channel, the layered phosphorus gallium sulfide dielectric layer and the graphite grid electrode by adopting a dry transfer technology. The obtained transistor shows excellent electrical properties: the current on-off ratio is greater than or equal to 3 * 10 < 8 >, the gate leakage current is less than or equal to 1 * 10 <-13 > A, the subthreshold swing is about 85 mV / dec, and the interface hysteresis voltage is as low as 20 mV. The method is suitable for low-power-consumption and high-performance integrated circuits, logic electronic devices and optoelectronic devices.

This invention provides a method for fabricating a field-effect transistor (FET), relating to the field of semiconductor electronic device technology. The invention uses an epitaxially grown SrTiO3 thin film as the gate dielectric layer, which has the advantage of low roughness. Furthermore, PPC is used as a support layer to achieve the transfer of the SrTiO3 thin film, which greatly reduces the introduction of residues during the fabrication process, resulting in a clean and smooth SrTiO3 film surface. After depositing a two-dimensional layered semiconductor material as the channel material, the interface between the SrTiO3 thin film and the two-dimensional material is effectively optimized, forming a quasi-van der Waals contact. This yields a high-quality gate dielectric and channel material interface, significantly improving device performance. Example results show that the FET fabricated by this invention exhibits a 10-1 8 High on / off ratio, ultra-low subthreshold swing of 69.2mV / dec, and up to 230cm 2 The mobility of a field-effect transistor is 1 / (V·s).

The invention belongs to the technical field of semiconductor devices, and particularly relates to a low-temperature preparation method for improving performance and stability of a metal oxide thin film transistor. According to the preparation method disclosed by the invention, the thin film transistor is firstly subjected to fluorine plasma treatment and then subjected to low-temperature annealing treatment, so that the electrical property and the stability of the thin film transistor are effectively improved, and compared with a traditional high-temperature annealing technology, the temperature thermal budget is reduced, and the flexible application of the device is expanded. The metal oxide thin film transistor prepared by the invention comprises a substrate, a bottom gate electrode, a gate dielectric layer, a channel layer, a first source electrode, a first drain electrode, a second source electrode and a second drain electrode. In the preparation process, reasonable plasma processing sputtering power and time are set, metal hydroxyl defects existing on the surface of the active channel layer are reduced under the condition that a channel layer material is not damaged, and therefore the performance such as the switching ratio and the subthreshold swing of the thin film transistor is improved.

The invention discloses a display substrate and a preparation method thereof, a display panel and a display device. The display substrate comprises a substrate and at least one first transistor, and the first transistor is located on one side of the substrate; the first transistor comprises a first active layer, a first grid electrode and a second grid electrode; the first grid electrode is located on one side, away from the substrate, of the first active layer; the second grid electrode is located on the side, close to the substrate, of the first active layer, is coupled with the first grid electrode and the first active layer and is used for controlling on-off of the first active layer based on an electric signal provided by the first grid electrode. Under the condition that on-off of the first active layer is controlled based on an electric signal provided by the first grid electrode, capacitance of a control end formed by connecting the two capacitors in series is smaller, so that the size of the first active layer and the thickness of the first insulating layer and the thickness of the second insulating layer are not increased, the sub-threshold swing of the first transistor is increased, and gray scale expansion under low brightness is improved.

This invention belongs to the field of semiconductor technology, specifically disclosing an Al-ITZO target material, its preparation method, and its applications. The raw materials for preparing the Al-ITZO target material of this invention include indium oxide, tin oxide, zinc oxide, and aluminum oxide, as well as binders and plasticizers. The Al-ITZO target material of this invention exhibits high ion mobility when used as a channel layer material in thin-film transistor (TFT) devices, with a maximum mobility reaching 38 cm⁻¹. 2 ·V ‑1 ·S ‑1 Compared to IGZO, the Al-ITZO target exhibits significant improvements, with an extremely low subthreshold swing (SS) value, demonstrating high stability. Furthermore, the Al-ITZO target of this invention has lower cost and a wider range of raw material sources. This invention also provides a method for preparing the Al-ITZO target and its applications.

The present disclosure provides a transistor and an electronic device, adopts GaAsSb / InGaAs heterojunction material, can adjust the doping concentration of the P+ type GaAsSb layer, the In component in the InGaAs layer, and the side inclination angle of the InGaAs layer and the P+ type GaAsSb layer and other parameters, so that GaAsSb / InGaAs is more flexible in the adjustment of the energy band structure and the device structure, can effectively increase the tunneling probability of the carrier, enhance the gate control ability, so as to reduce the subthreshold swing of the tunneling field effect transistor and increase the on-current, therefore, the present disclosure can realize the significant improvement of the device performance of the GaAsSb / InGaAs tunneling field effect transistor without increasing the complexity of the device preparation.

A thin film transistor is provided. The thin film transistor may comprise a stacked channel structure in which a first material layer including an oxide semiconductor and a second material layer including a metal oxide insulator are stacked, wherein the channel structure forms a multi-channel by stacking a plurality of stacks each having the first material layer and the second material layer stacked, and as the number of the stacks stacked increases, mobility and subthreshold swing may increase.

The present application relates to Si 1‑x Ge x / Si heterojunction gate oxide layer ladder channel double gate tunnel field effect transistor; the purpose is to further improve the on-state current and on-off current ratio of double gate TFET (DGTFET) and reduce the subthreshold swing on the basis of relieving the bipolar effect problem of double gate TFET (DGTFET); it comprises a drain region, a channel region and a source region, the channel region is a ladder structure, the thin end of the channel region is connected with the source region, and the thick end of the channel region is connected with the drain region; both sides of the channel region are provided with ladder structure low-k gate oxide layers matched with the shape of the channel region, the step surface of the low-k gate oxide layer is located on the left side of the step surface of the channel region, and the thickness of the thin end of the low-k gate oxide layer is smaller than the thickness of the thick end of the low-k gate oxide layer; both sides of the thin end of the low-k gate oxide layer are provided with high-k gate oxide layers with the same length; the low-k gate oxide layer is prepared by using low-k dielectric material, and the high-k gate oxide layer is prepared by using high-k dielectric material; the source region is prepared by using Si 1‑x Ge x , the channel region and the drain region are prepared by using silicon.

The invention provides a junction-free transistor with a planar core-shell structure, which comprises a substrate, a core layer, a shell layer, a source-drain region, a grid electrode and a first side wall, the substrate, the core layer, the shell layer and the source-drain region are sequentially stacked along the stacking direction, the grid electrode and the first side wall are arranged on the same layer, the first side wall is arranged between the grid electrode and the source-drain region, and the first dielectric constant of the first side wall is greater than 7.5. In the stacking direction, the projection area of the shell layer in the plane where the substrate is located at least covers the projection areas of the grid electrode and the side wall in the plane where the substrate is located. By arranging the first side wall with a relatively high dielectric constant, the trend that the threshold voltage drops along with the shortening of the channel length can be slowed down, the roll-off of the threshold voltage can be inhibited, and the first side wall with the relatively high dielectric constant can also enhance the control capability of the grid electrode on the channel, improve the switching characteristic and inhibit the subthreshold swing degradation. And the modulation of the leakage voltage on the threshold voltage can be effectively suppressed, the leakage induced barrier lowering effect is weakened, and the suppression effect on the short channel effect is realized.

This invention proposes an indium oxide / indium gallium tin oxide (IGa Tin) dual-channel thin-film transistor and its fabrication method. The specific fabrication method involves using heavily doped p-type silicon and silicon dioxide as the gate and insulating layers, respectively, as the substrate. First, an ultrathin layer of indium oxide is grown on the substrate using radio frequency magnetron sputtering. Then, a thicker layer of IGa Tin oxide is grown using radio frequency magnetron sputtering. Next, aluminum is grown as the metal electrode using DC magnetron sputtering. Finally, aluminum oxide is used as the passivation layer. All deposition layers are patterned using a mask to fabricate the IGa Tin / indium gallium tin oxide dual-channel thin-film transistor. This invention utilizes the highly conductive ultrathin layer of indium oxide to provide carrier concentration and the thicker IGa Tin oxide film to regulate the carrier transport characteristics of the device. The thin-film transistor of this invention exhibits advantages such as high mobility, low threshold voltage, and low subthreshold swing. It also possesses advantages such as good electrical stability, high on / off current ratio, and simple fabrication method.

The invention relates to a (6, 5) chiral carbon nanotube field effect transistor for inhibiting interband tunneling and a preparation method thereof, and belongs to the technical field of semiconductors. According to the method, a (6, 5) chiral carbon nanotube dispersion liquid with high purity (greater than 95%) and high concentration (increased to 3 times) is prepared in a single toluene solvent on the basis of a PFO-BPy polymer oriented coating and multi-stage circulating centrifugal separation strategy; a uniform and compact film is formed on a substrate with a gate dielectric layer in a self-assembly mode, and an isolation channel is defined through photoetching and etching processes; and finally preparing a source electrode and a drain electrode to complete device construction. The obtained transistor shows excellent electrical properties, the inter-band tunneling effect of the transistor is remarkably suppressed, the off-state current is lower than 10 <-11 > A, the switching ratio is higher than 106, the sub-threshold swing is kept stable under different voltages, the transistor is remarkably superior to a traditional device, and the transistor is suitable for an ultra-low power consumption integrated circuit.

The present application belongs to the technical field of display, and discloses a driving backplane, a display panel, and a display apparatus. The driving backplane comprises a substrate, a first transistor, and a second transistor. The first transistor comprises a first gate, a first active layer, and a first auxiliary electrode, and the second transistor comprises a second gate, a second active layer, and a third gate. The distance between the first active layer and the first auxiliary electrode is less than the distance between the second active layer and the third gate. The distance between the first active layer and the first auxiliary electrode is small, and the subthreshold swing of the first transistor is large, so that the voltage of the first active layer can reach a threshold voltage over a relatively long time, and sufficient grayscale can be expressed even at a low grayscale, thereby effectively reducing the possibility of screen contamination in low grayscale. The distance between the second active layer and the third gate is large, and the subthreshold swing of the second transistor is small, so that switching characteristics thereof are good. A display panel in which such a driving backplane is used has a good display effect.

This application provides a semiconductor device and its fabrication method, as well as an electronic device, relating to the field of semiconductor technology, capable of reducing the subthreshold swing of transistors. The semiconductor device includes a transistor. The transistor includes a channel, a source, and a drain; the source and drain are disposed at opposite ends of the channel; a first intercalation layer is disposed between the source and the channel, and the first intercalation layer is in contact with both the source and the channel. The channel is made of a lightly doped semiconductor or an intrinsic semiconductor. The drain is made of a heavily doped semiconductor. The source is made of a P-type heavily doped semiconductor; wherein, the first intercalation layer is made of a high work function material, and the Fermi level of the high work function material is no more than 1 / 3 of the band gap of the channel semiconductor; or, the source is made of an N-type heavily doped semiconductor; the first intercalation layer is made of a low work function material, and the Fermi level of the low work function material is no more than 1 / 3 of the band gap of the channel semiconductor.

The embodiment of the present application discloses a memory and a preparation method thereof. The memory comprises a plurality of memory cells, each of which comprises a charge storage region and a vertical transfer transistor located on the charge storage region. By controlling the doping concentration of the source end, the drain end and the channel region of the vertical transfer transistor, the interface between the source end and the channel region is prone to band-to-band tunneling, so as to realize lower subthreshold swing and larger on-state current, thereby improving the read-write speed. Further, a light doping concentration region including light doping and having a doping type opposite to that of the drain end is formed between the drain end and the channel region, so as to reduce the leakage current, reduce the refresh frequency and reduce the power consumption. The preparation method of the memory only needs simple doping concentration control, is compatible with the manufacturing of a CMOS image sensor, and can reduce the process manufacturing difficulty.

This application discloses a thin-film transistor (TFT), its fabrication method, and a display device. The TFT fabrication method includes: providing a pre-fabricated TFT; and sequentially subjecting the pre-fabricated TFT to a first thermal annealing treatment and an ultraviolet radiation treatment to obtain the TFT. The TFT fabricated by the method described in this application has a steeper subthreshold swing and lower power consumption.

The application belongs to the technical field of field effect transistor devices, and discloses a preparation method of a dielectric layer of a field effect transistor device and a method for preparing a field effect transistor device by using the same. The preparation method of the dielectric layer of the field effect transistor device is as follows: stripping hafnium sulfide to obtain a thin layer of hafnium sulfide; then transferring the thin layer of hafnium sulfide to a polydimethylsiloxane stamp, and performing thermal oxidation treatment to obtain a hafnium oxide dielectric layer. The dielectric layer of the field effect transistor device prepared by the application has the characteristics of no wrinkle on the surface, uniform distribution and atomic-level flatness, is a high-k dielectric layer with good natural oxide contact, is used as a high-k dielectric layer, and can significantly improve the subthreshold swing and other performances of the field effect transistor device. The structure of the field effect transistor device prepared by the application is simple, the performance is excellent, and the preparation method is simple.

The application relates to a high-performance double-gate junction field effect transistor and a preparation method thereof, which comprises a double P-N junction composed of two-dimensional Te and two-dimensional MoS2 in a preferred embodiment, and is composed of a three-layer structure, the upper and lower layers are two-dimensional MoS2 layers, and the middle layer is a two-dimensional Te layer; the layers are in a cross structure, and the electrodes shared by the MoS2 layers are used as the gate; the Te layer is used as a carrier channel layer, and the two electrodes are used as the source and the drain. The device structure realizes the opening and closing of the JFET by regulating the positive and negative bias of the P-N junction and the width of the depletion region of the Te channel layer. Since the structure does not have a dielectric layer, an ideal subthreshold swing is realized, and the carrier concentration of the two-dimensional Te is high, so that a large current response can be realized under a small source-drain voltage. The JFET designed in the application has a small subthreshold swing and a large on-state current, and is crucial for devices requiring low power consumption and large current design.

The present disclosure provides a kind of drive backboard and its manufacturing method, display panel, display device, it is related to display technical field.The drive backboard includes: substrate, active layer, first gate insulating layer, first gate metal layer, dielectric layer, source-drain metal layer, active layer includes the drive channel region of drive transistor, first gate metal layer includes first conductive part, and first conductive part and drive channel region exist overlapping area;Dielectric layer has first via, and the spacing between the orthographic projection of first via and the orthographic projection of drive channel region is less than or equal to 0.5 microns;Source-drain metal layer includes first connecting piece, and first connecting piece is connected with first conductive part by first via.In the embodiment of the present disclosure, by adjusting the planar spacing between the first via connected with first conductive part and the drive channel region of drive transistor, the subthreshold swing of drive transistor can be increased, so as to improve the gray scale control ability of pixel circuit.

This application provides a semiconductor device and a method for manufacturing the same. The semiconductor device includes a substrate, a source electrode, a drain electrode, and a channel structure disposed on one side of the substrate. The channel structure is located between the source electrode and the drain electrode. The channel structure includes a stack of multiple nanosheets, a gate electrode surrounding the nanosheets, and a cavity. The cavity is located at least between the channel structure and the substrate. The cavity is formed by the channel structure, the source electrode, the drain electrode, and the substrate surrounding the cavity. In other words, the cavity is located below the channel structure, the source electrode, and the drain electrode, without any contacting film layers, thus forming a fully floating structure. This can significantly improve the gate control performance of the semiconductor device, reduce the subthreshold swing of the semiconductor device, reduce leakage current and parasitic capacitance, increase the drive current, and improve the performance of the semiconductor device.

The invention is suitable for the technical field of display, and provides a display panel, a manufacturing method and a display device.The display panel comprises a substrate, a first active part, a second active part and a gate insulating layer, the gate insulating layer comprises a first part arranged on the side, away from the substrate, of the first active part and a second part arranged on the side, away from the substrate, of the second active part, and the first part is arranged on the first part; an interface state density between the first portion and the first active portion is lower than an interface state density between the second portion and the second active portion. The interface state density between the gate insulation layer and the first active part and the interface state density between the gate insulation layer and the second active part are different, so that the first thin film transistor corresponding to the first active part has a small sub-threshold swing, and the second thin film transistor corresponding to the second active part has a large sub-threshold swing. The first thin film transistor and the second thin film transistor can be used for different circuit functions, the second thin film transistor does not need to be provided with a large channel, the area of the second thin film transistor can be reduced, and the resolution of the display panel can be improved.

The application discloses a MOSFET structure and a preparation method thereof, and belongs to the technical field of semiconductors; the MOSFET structure is composed of a plurality of mutually-parallel MOS cells, and a single MOS cell comprises a drain, a semiconductor epitaxial layer, a source and a gate; the application sets a lightly-doped N layer in the middle of an N drift layer, and cooperates with the design of arc-shaped side-symmetrical P-layers on both sides, so that the electric field distribution in the device is effectively optimized; the lightly-doped N layer widens the depletion region between the channel and the drain, weakens the penetration of the drain electric field to the channel, the arc-shaped side-symmetrical P-layers are in direct contact with the N substrate layer to form a lateral field limiting ring, the electric field concentration is further dispersed, the drain-induced barrier lowering effect and the hot carrier effect are reduced, the control ability of the gate to the channel is enhanced, and thus the problems of the increase of subthreshold swing and the threshold voltage drift are inhibited, and the switch controllability of the device is improved.

This invention provides a hybrid conduction mechanism gate-all-around transistor, comprising: a gate-all-around MOSFET device, including a substrate, a first source region, a first drain region, a first gate dielectric layer, and a gate-all-around channel control gate; wherein the first source region and the first drain region are doped with first ions; a second source region is formed between the substrate and the first source region, and a second drain region is formed between the substrate and the first drain region, and the height of the second source region and the second drain region is not less than the height of the substrate between the first source region and the first drain region; wherein the second drain region is doped with first ions, and the second source region is doped with second ions; a bottom control gate; the bottom control gate covers the surface of the gate dielectric layer on the substrate; the gate-all-around channel control gate covers the surface of the bottom control gate, and the difference in work function between the bottom control gate and the gate-all-around channel control gate is greater than 0.5 eV. This technical solution solves the problem that the ultra-steep subthreshold swing characteristic of less than 60 mV / dec in the bottom subthreshold region cannot be highlighted.

The application discloses a transistor, a transistor preparation method, a pixel circuit and a display panel. The transistor comprises a substrate, a first gate arranged on one side of the substrate, an active layer arranged on the side, away from the substrate, of the first gate, and partially overlapping the first gate in the thickness direction of the transistor, and a second gate arranged on the side, away from the substrate, of the active layer, partially overlapping the active layer in the thickness direction of the transistor, and not overlapping the projection of the first gate on the active layer, and the second gate and the first gate are electrically connected. By arranging the first gate and the second gate in the transistor and electrically connecting the second gate and the first gate, the requirements of high current output capability and large subthreshold swing can be met simultaneously on the same transistor, thereby solving the problem of uneven brightness display and improving the use performance of the transistor.

Disclosed in the present invention are a two-dimensional semiconductor device and a manufacturing method therefor. The device comprises a substrate, a two-dimensional semiconductor material layer and a gate structure, wherein the gate structure comprises a gate dielectric layer and a gate electrode layer; the gate dielectric layer comprises a portion covered by the bottom of a gate electrode and portions not covered by the bottom of the gate electrode; the portions not covered by the bottom of the gate electrode each extend outward along the surface of the semiconductor layer; the portions of the gate dielectric layer that are not covered by the bottom of the gate electrode and two sides of the gate electrode are covered with sidewalls; a support layer is arranged on the surface of each sidewall; and source-drain metal contact layers penetrate, from top to bottom, the support layers, the sidewalls located on the surface of the gate dielectric layer, the two-dimensional semiconductor material layer and the substrate. In the present invention, metallic yttrium is deposited on a two-dimensional semiconductor material layer, and cleaning is performed to leave yttrium seeds, such that the metal yttrium is used as seeds to obtain a high-performance gate structure, thereby significantly reducing the subthreshold swing and contact resistance of a device, effectively inhibiting the short-channel effect, and reducing channel defects. Therefore, the overall performance, yield and reliability of the device are significantly improved.