70 results about "Subthreshold swing" patented technology

The invention relates to the technical field of kits, in particular to a MoS2 back gate field effect transistor based on a wet transfer process and a preparation method of the MoS2 back gate field effect transistor. The MoS2 back gate field effect transistor is formed by sequentially arranging a silicon-based substrate, a SiO2 insulating layer, a MoS2 conducting channel layer and an Ag source drain electrode from bottom to top; a high-quality single-layer MoS2 thin film is prepared through a chemical vapor deposition (CVD) method, PMMA is adopted as a supporting layer, clean Van der Waals contact of the MoS2 thin film and a SiO2 / Si substrate is achieved through a wet transfer process of NaOH solution etching, deionized water cleaning and acetone stripping of the supporting layer, and finally a source electrode and a drain electrode are prepared by combining photoetching and thermal evaporation processes. According to the method, the problems of pollutant residues and traps of an interface between MoS2 and the substrate in the traditional process are effectively solved, the carrier mobility, transconductance and on-state current of the device are remarkably improved, the sub-threshold swing is reduced, and the method is suitable for manufacturing a two-dimensional material integrated circuit device with low power consumption and high performance.

The present invention discloses a steep subthreshold swing bipolar transistor based on ferroelectric nanogaps and a preparation method thereof. The transistor comprises, arranged from bottom to top, a substrate, a buffer layer, a conductive film layer, a ferroelectric dielectric film layer, and a gate, as well as a top gate control signal unit and a source-drain signal input unit. One end of the top gate control signal unit is connected to the gate, and the other end is connected to a series branch. The two ends of the source-drain signal input unit are respectively connected to the source and drain of the conductive film layer to form a series branch. The source-drain signal input unit is used to read the current of the steep subthreshold swing bipolar transistor. The top gate control signal unit is used to output a voltage to generate a vertical electric field to control the opening and closing of the nanogaps in the conductive film layer. The steep subthreshold swing bipolar transistor proposed in the present invention has the advantages of near-zero off-current, large on-current, steep subthreshold swing, low power consumption, and compatibility with traditional CMOS processes.

Various embodiments disclosed presents pixel driver circuits that utilize integrated diode structures to enhance sub-threshold swing and modulate threshold voltage. Conventional transistor-only designs often encounter challenges in achieving precise control and efficiency, limited by their sub-threshold swing and voltage modulation capabilities. Various embodiments incorporate advanced MOSFETs in series with diodes without an additional mask and process knob, enabling advanced control over the LED current without a larger area penalty and less process variation with device sub-threshold engineering. Such transistor-diode configuration improves brightness, gray-scale accuracy, and overall display performance, leading to improved power efficiency, advanced display uniformity, and improved reliability for LED devices.

The invention discloses an undoped tunneling junction line tunneling field effect transistor and a preparation method thereof. The line tunneling field effect transistor comprises a substrate, a drain electrode, an N + Si layer, SiO2 isolation, intrinsic Si, an L-shaped metal structure, intrinsic Ge, a grid electrode, a first oxide layer and a second oxide layer, stacking drain electrodes on the two sides of the N + Si layer on the substrate; intrinsic Si is stacked on the N + Si layer, and SiO2 isolation is stacked on the two sides of the intrinsic Si; intrinsic Ge is stacked on the two sides of the upper portion of the intrinsic Si, and a grid electrode is arranged between the intrinsic Ge; a second oxide layer covers the upper part of the SiO2 isolator and the outer side of the intrinsic Ge; high-work-function metal is stacked on the outer side of the second oxide layer and above the intrinsic Ge to form an L-shaped metal structure; a source electrode is formed above the intrinsic Ge, and a back gate is formed on the outer side of the second oxide layer. According to the invention, the line tunnel junction is formed on the intrinsic Ge, so that the on-state current of the transistor is improved, the sub-threshold swing is reduced, and the switching performance is improved.

The invention relates to the field of semiconductor devices, in particular to an ultra-low sub-threshold swing transistor based on a hafnium-aluminum-oxygen ultra-thin matching layer film and a preparation method of the ultra-low sub-threshold swing transistor based on the hafnium-aluminum-oxygen ultra-thin matching layer film. And the driving capability and switching speed of the device are further improved. On the premise of ensuring stable characteristics of the ferroelectric film, a proper matching layer medium is introduced to achieve the purpose of reducing clockwise hysteresis caused by an interface state so as to further reduce total hysteresis, the introduced new matching layer Hf1-aAlaOb is compared with a common Al2O3 matching layer, nitridation process research is carried out, a capacitance matching medium most suitable for Zr1-xAlxOy is explored, and the performance of the ferroelectric film is improved. And the driving capability and switching speed of the device are further improved.

The embodiment of the invention provides a semiconductor device, a preparation method, a packaging structure and electronic equipment, relates to the technical field of semiconductors, and is used for reducing the sub-threshold swing of the semiconductor device and the power consumption of the semiconductor device. The semiconductor device includes: a substrate; the semiconductor layer is arranged on the substrate, and the semiconductor layer comprises a source electrode region, an ionization region and a channel region arranged between the source electrode region and the ionization region; the gate metal layer is arranged on the channel region; and a first insulating layer and a first metal layer are laminated on the ionization region.

The present disclosure relates to a transistor structure and a method for forming the same. The transistor structure comprises: a first dielectric layer, the first dielectric layer comprising passivating oxygen vacancies; an active layer located on the surface of the first dielectric layer, the active layer comprising a channel region and a source / drain region located outside the channel region; a gate layer located on the side of the channel region facing away from the first dielectric layer; and a barrier layer located between the first dielectric layer and the source / drain region, the barrier layer being used to block oxygen from entering the source / drain region. The present disclosure enables a positive shift in the threshold voltage of the transistor structure and reduces the subthreshold swing of the transistor structure, thereby improving the response speed of the transistor structure and preventing an increase in RC delay.

The invention relates to a display panel and a display terminal. The display panel comprises a plurality of sub-pixels, at least one sub-pixel comprises a pixel circuit, and the pixel circuit comprises a driving transistor and a switching transistor which are connected. Wherein the sub-threshold swing of the driving transistor is greater than that of the switching transistor. In the display panel provided by the embodiment of the invention, the sub-threshold swing of the driving transistor is set to be greater than the sub-threshold swing of the switching transistor, and when the display panel displays a low-gray-scale picture, the sub-threshold swing of the driving transistor is relatively large, so that small change of grid voltage does not cause great change of current, the current can be accurately controlled, and the display effect is improved. And the phenomenon of non-uniform brightness of a low-gray-scale picture is improved.

The invention provides a novel field effect transistor fused with a memristor and a preparation method of the novel field effect transistor, and belongs to the technical field of integrated circuit micro-nano electronic devices. A gate electrode on the substrate; the gate dielectric layer is located on the gate electrode; the drain electrode is located on the gate dielectric layer; the channel layer is located on the drain electrode; a source electrode and a first memristive electrode, wherein the source electrode and the first memristive electrode are both located on the channel layer; wherein the drain electrode is multiplexed as a second memristive electrode, the vertical projection of the first memristive electrode and the vertical projection of the drain electrode are at least partially overlapped, and the channel layer is arranged between the source electrode and the drain electrode and between the first memristive electrode and the drain electrode. The subthreshold swing limit of a traditional transistor is broken through, the power consumption of a device is effectively reduced, and the switching performance is improved.

A high-voltage transistor may include a composite gate dielectric layer having multiple regions with different dielectric constant values and / or a composite gate structure having multiple regions of different work function values. The composite dielectric layer having multiple regions with different dielectric constant values and / or the composite gate structure having multiple regions with different work functions increases the threshold voltage uniformity across a channel region of the high-voltage transistor. The increased threshold voltage uniformity may enable a low subthreshold swing and a low subthreshold off-stage current leakage to be achieved for the high-voltage transistor, which increases the operating efficiency of the high-voltage transistor and enables the size of the high-voltage transistor to be reduced without increasing (or with minimal increase to) the subthreshold swing and and / or the subthreshold off-stage current leakage of the high-voltage transistor.

The application discloses an equivalent sub-threshold swing regulation method of a single-gate transistor and a pixel circuit. The method comprises the following steps: obtaining a coupling control voltage based on a preset linear function relationship and a data voltage; coupling the coupling control voltage and the data voltage to obtain a coupling result; and providing the coupling result to a gate node of the single-gate transistor. The preset linear function relationship comprises a gain coefficient, and the gain coefficient is configured to program and regulate the equivalent sub-threshold swing of the single-gate transistor. Through the design of the preset linear function relationship between the data voltage and the coupling control voltage and the synergistic effect of circuit compensation, the high-precision uniformity control of the current under the low gray scale condition and the improvement of the high-resolution electroluminescent display quality are realized.

A semiconductor device and a method of manufacturing the same are disclosed. The semiconductor device includes: a substrate and a channel portion. The channel portion includes a first portion including a fin-shaped structure protruding with respect to the substrate and a second portion located above the first portion and spaced apart from the first portion. The second portion includes one or more nanowires or nanosheets spaced apart from each other. Source / drain portions are arranged on two opposite sides of the channel portion in a first direction and in contact with the channel portion. A gate stack extends on the substrate in a second direction intersecting with the first direction, so as to intersect with the channel portion.

To provide a device, a system, and a method for determining an expected number of SSPC (selective slow programming convergence) cells for a page of cells for specific conditions of the page for non-volatile (NV) storage media such as NAND media written by a program and program verification operation.SOLUTION: A method performs program verify with a first word line (WL) select voltage for SSPC cell detection for a first write of a page to detect an expected number of SSPC cells. Based on the determined expected number of SSPC cells, the method sets a boost voltage to capture the expected number of SSPC cells during the program verify operation. The method performs program verify for subsequent writes to the page with a higher WL select voltage, to perform program verify for standard cells and then SSPC program verify with the boost voltage determined from the first write.SELECTED DRAWING: Figure 8

The invention discloses a high-performance two-dimensional transistor and a preparation method and application thereof, and relates to the technical field of semiconductor material manufacturing, and the structure of the transistor comprises a channel layer, a gate dielectric layer and an electrode assembly. Wherein the channel layer is made of a two-dimensional semiconductor material; the gate dielectric layer is made of a layered phosphorus gallium sulfide material; the electrode assembly comprises a grid electrode, a source electrode and a drain electrode; the channel layer and the gate dielectric layer are combined through Van der Waals force. The preparation method comprises the following steps: obtaining a two-dimensional material sheet through mechanical stripping, and sequentially stacking the two-dimensional semiconductor material channel, the layered phosphorus gallium sulfide dielectric layer and the graphite grid electrode by adopting a dry transfer technology. The obtained transistor shows excellent electrical properties: the current on-off ratio is greater than or equal to 3 * 10 < 8 >, the gate leakage current is less than or equal to 1 * 10 <-13 > A, the subthreshold swing is about 85 mV / dec, and the interface hysteresis voltage is as low as 20 mV. The method is suitable for low-power-consumption and high-performance integrated circuits, logic electronic devices and optoelectronic devices.

The invention relates to the technical field of electronic devices, and particularly discloses a method for improving the subthreshold swing of a molecular transistor device, which comprises the following steps of: 1, spin-coating a molecular A solution on a sink containing an electrode array to obtain the molecular transistor device; 2, controlling the on-off state of the molecular transistor device through voltage, and calculating the sub-threshold swing in the molecular transistor device; according to the invention, based on the molecular design, the interference effect between electronic states is constructed, so that the switching state of the molecular transistor device can be controlled under a smaller voltage, and the improvement of the subthreshold swing in the molecular transistor device is calculated; the invention provides a molecular structure design-based method for improving the sub-threshold swing of a molecular transistor device, which has important significance for future electronic components.

This invention provides a method for fabricating a field-effect transistor (FET), relating to the field of semiconductor electronic device technology. The invention uses an epitaxially grown SrTiO3 thin film as the gate dielectric layer, which has the advantage of low roughness. Furthermore, PPC is used as a support layer to achieve the transfer of the SrTiO3 thin film, which greatly reduces the introduction of residues during the fabrication process, resulting in a clean and smooth SrTiO3 film surface. After depositing a two-dimensional layered semiconductor material as the channel material, the interface between the SrTiO3 thin film and the two-dimensional material is effectively optimized, forming a quasi-van der Waals contact. This yields a high-quality gate dielectric and channel material interface, significantly improving device performance. Example results show that the FET fabricated by this invention exhibits a 10-1 8 High on / off ratio, ultra-low subthreshold swing of 69.2mV / dec, and up to 230cm 2 The mobility of a field-effect transistor is 1 / (V·s).

The application provides a numerical simulation method of a short channel negative capacitance surrounding gate field effect transistor, constructs a source-drain current model of a short channel negative capacitance surrounding gate field effect transistor NC-GAAFET with the structure of MFIS; the source-drain current model of a conventional GAAFET is analyzed, the electrostatic potential obtained by solving a cylindrical two-dimensional Poisson equation is obtained; the source-drain current I ds is obtained according to the boundary conditions near the source region and the drain region, and the drain-induced barrier lowering effect parameter is calculated; the source-drain current model of the conventional short channel GAAFET is coupled, and the source-drain current model of the NC-GAAFET is obtained by combining the flexoelectric effect; the subthreshold swing of the NC-GAAFET is calculated; step 6: repeating steps 2 to 5, adjusting different ferroelectric layer thicknesses, structure parameters and flexoelectric coefficients, and obtaining electrical properties under different conditions.

According to the transistor and the electronic equipment, the GaAsSb / InGaAs heterojunction material is adopted, adjustment of GaAsSb / InGaAs on an energy band structure and a device structure can be more flexible by adjusting parameters such as the doping concentration of the P + type GaAsSb layer, the In component in the InGaAs layer and the side face inclination angles of the InGaAs layer and the P + type GaAsSb layer, the tunneling probability of carriers can be effectively increased, the grid control capacity can be enhanced, and the device performance can be improved. Therefore, the subthreshold swing of the tunneling field effect transistor can be reduced and the conduction current can be increased, so that the device performance of the GaAsSb / InGaAs tunneling field effect transistor can be remarkably improved on the premise that the preparation complexity of the device is not increased.

The invention belongs to the technical field of semiconductor devices, and particularly relates to a low-temperature preparation method for improving performance and stability of a metal oxide thin film transistor. According to the preparation method disclosed by the invention, the thin film transistor is firstly subjected to fluorine plasma treatment and then subjected to low-temperature annealing treatment, so that the electrical property and the stability of the thin film transistor are effectively improved, and compared with a traditional high-temperature annealing technology, the temperature thermal budget is reduced, and the flexible application of the device is expanded. The metal oxide thin film transistor prepared by the invention comprises a substrate, a bottom gate electrode, a gate dielectric layer, a channel layer, a first source electrode, a first drain electrode, a second source electrode and a second drain electrode. In the preparation process, reasonable plasma processing sputtering power and time are set, metal hydroxyl defects existing on the surface of the active channel layer are reduced under the condition that a channel layer material is not damaged, and therefore the performance such as the switching ratio and the subthreshold swing of the thin film transistor is improved.

The invention discloses a display substrate and a preparation method thereof, a display panel and a display device. The display substrate comprises a substrate and at least one first transistor, and the first transistor is located on one side of the substrate; the first transistor comprises a first active layer, a first grid electrode and a second grid electrode; the first grid electrode is located on one side, away from the substrate, of the first active layer; the second grid electrode is located on the side, close to the substrate, of the first active layer, is coupled with the first grid electrode and the first active layer and is used for controlling on-off of the first active layer based on an electric signal provided by the first grid electrode. Under the condition that on-off of the first active layer is controlled based on an electric signal provided by the first grid electrode, capacitance of a control end formed by connecting the two capacitors in series is smaller, so that the size of the first active layer and the thickness of the first insulating layer and the thickness of the second insulating layer are not increased, the sub-threshold swing of the first transistor is increased, and gray scale expansion under low brightness is improved.

The invention discloses a MoS2-based thin film transistor MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) structure and a preparation method thereof, and belongs to the technical field of semiconductors. Comprising a drain electrode, a semiconductor epitaxial layer, a source electrode and a grid electrode; by arranging the lightly doped N layer in the middle of the N drift layer and cooperating with the design of the arc-shaped side-symmetric P-layers on the two sides, the electric field distribution in the device is effectively optimized, the lightly doped N layer widens a depletion region between a channel and a drain electrode and weakens the permeation of a drain electrode electric field to the channel, and the arc-shaped side-symmetric P-layers and the N substrate layer are in direct contact to form a transverse field limiting ring, so that the device performance is improved. And electric field concentration is further dispersed, the induced barrier lowering effect and the hot carrier effect of the drain electrode are reduced, and the control capability of the grid electrode on the channel is enhanced, so that the problems of subthreshold swing increase, threshold voltage drift and the like are inhibited, and the switching controllability of the device is improved.

The invention relates to the field of research, development and application of multifunctional device logic circuits, in particular to a multi-valued logic circuit based on a multifunctional thermal emitter transistor and a construction method. The circuit is formed by connecting three parallel multifunctional thermal emitter transistors in parallel, and comprises a graphene channel with a gap in the top, a hafnium oxide insulating layer, a germanium substrate, a base electrode and an emitter metal electrode from top to bottom, wherein the base electrode and the emitter metal electrode are located on the two sides of the graphene channel and make contact with the graphene channel. According to the multi-valued logic circuit, the multi-valued logic circuit of the multifunctional thermal emitter transistor is realized by constructing the parallel circuit of the multifunctional thermal emitter transistor. The quaternary digital logic phase inverter with high gain is realized by utilizing the ultralow subthreshold swing in the transfer characteristic of the multifunctional thermal emitter transistor. A high negative differential resistance peak-valley current ratio in the output characteristics of the multifunctional thermal emitter transistor is utilized to realize an inverter, a follower and an adder under different base bias voltages.

This invention belongs to the field of semiconductor technology, specifically disclosing an Al-ITZO target material, its preparation method, and its applications. The raw materials for preparing the Al-ITZO target material of this invention include indium oxide, tin oxide, zinc oxide, and aluminum oxide, as well as binders and plasticizers. The Al-ITZO target material of this invention exhibits high ion mobility when used as a channel layer material in thin-film transistor (TFT) devices, with a maximum mobility reaching 38 cm⁻¹. 2 ·V ‑1 ·S ‑1 Compared to IGZO, the Al-ITZO target exhibits significant improvements, with an extremely low subthreshold swing (SS) value, demonstrating high stability. Furthermore, the Al-ITZO target of this invention has lower cost and a wider range of raw material sources. This invention also provides a method for preparing the Al-ITZO target and its applications.

The present disclosure provides a transistor and an electronic device, adopts GaAsSb / InGaAs heterojunction material, can adjust the doping concentration of the P+ type GaAsSb layer, the In component in the InGaAs layer, and the side inclination angle of the InGaAs layer and the P+ type GaAsSb layer and other parameters, so that GaAsSb / InGaAs is more flexible in the adjustment of the energy band structure and the device structure, can effectively increase the tunneling probability of the carrier, enhance the gate control ability, so as to reduce the subthreshold swing of the tunneling field effect transistor and increase the on-current, therefore, the present disclosure can realize the significant improvement of the device performance of the GaAsSb / InGaAs tunneling field effect transistor without increasing the complexity of the device preparation.

A thin film transistor is provided. The thin film transistor may comprise a stacked channel structure in which a first material layer including an oxide semiconductor and a second material layer including a metal oxide insulator are stacked, wherein the channel structure forms a multi-channel by stacking a plurality of stacks each having the first material layer and the second material layer stacked, and as the number of the stacks stacked increases, mobility and subthreshold swing may increase.

This application provides a display panel, a method for manufacturing the display panel, and a display device. The display panel includes a substrate, a buffer layer, an active layer, a gate insulating layer, and a gate layer. By having at least one of the buffer layer and the gate insulating layer have a stacked structure composed of two layers of the same material, the hydrogen content in the film layer near the active layer in the stacked structure is lower than that in the film layer far from the active layer. This can improve the uniformity of the thin-film transistors in the display area. By setting the active layer as a stacked structure formed by a first sub-active layer and a second sub-active layer, and making the mobility of the first sub-active layer greater than that of the second sub-active layer, the subthreshold swing of the thin-film transistors can be increased without affecting the initial threshold voltage of the thin-film transistors. This can improve the uniformity of the thin-film transistors in the display area while increasing the limit of the thin-film transistors in the non-display area.

This invention relates to the field of electric double-layer transistor technology, specifically to a TENG-based ultra-steep subthreshold swing field transistor, its fabrication method, and its applications. The TENG-based ultra-steep subthreshold swing field transistor of this invention includes: a transistor assembly and a TENG assembly. This invention utilizes the TENG assembly to generate a voltage V applied to the gate. G This replaces the supply voltage applied to the gate of existing field-effect transistors; V G It can vary with the adjustment of the TENG component and make the current I flowing from the source through the semiconductor layer to the drain. DS During the process of gradually changing from a positive voltage to a negative voltage, the negative voltage threshold V is reached. 负 The invention addresses the issue of ultra-steep subthreshold swing field transistors exhibiting abrupt changes near the time threshold. It facilitates gate self-powering and direct interaction between external motion and electronic components, simplifying structural integration. This invention solves the integration difficulty inherent in existing ultra-steep subthreshold swing field transistors that rely on external power supplies as gate voltages.

The present application relates to Si 1‑x Ge x / Si heterojunction gate oxide layer ladder channel double gate tunnel field effect transistor; the purpose is to further improve the on-state current and on-off current ratio of double gate TFET (DGTFET) and reduce the subthreshold swing on the basis of relieving the bipolar effect problem of double gate TFET (DGTFET); it comprises a drain region, a channel region and a source region, the channel region is a ladder structure, the thin end of the channel region is connected with the source region, and the thick end of the channel region is connected with the drain region; both sides of the channel region are provided with ladder structure low-k gate oxide layers matched with the shape of the channel region, the step surface of the low-k gate oxide layer is located on the left side of the step surface of the channel region, and the thickness of the thin end of the low-k gate oxide layer is smaller than the thickness of the thick end of the low-k gate oxide layer; both sides of the thin end of the low-k gate oxide layer are provided with high-k gate oxide layers with the same length; the low-k gate oxide layer is prepared by using low-k dielectric material, and the high-k gate oxide layer is prepared by using high-k dielectric material; the source region is prepared by using Si 1‑x Ge x , the channel region and the drain region are prepared by using silicon.

This invention relates to a fully two-dimensional ferroelectric ultra-steep slope transistor, its fabrication method, and its applications. The transistor comprises a three-layer fully two-dimensional heterostructure consisting of a few-layer two-dimensional conductive layer, a few-layer two-dimensional ferroelectric AgInP2Se6 layer, and a few-layer two-dimensional semiconductor channel layer stacked sequentially. The source and drain are located on the two-dimensional conductive layer; the gate is located on the two-dimensional conductive layer and is not in contact with the two-dimensional ferroelectric AgInP2Se6 layer or the channel layer. This fully two-dimensional ferroelectric ultra-steep slope transistor exhibits an ultra-steep subthreshold swing, extremely low operating voltage, and ultra-fast operating frequency, providing a new path for the development of future large-scale integrated circuits. In one embodiment, the transistor's subthreshold swing at room temperature can reach as low as 10 mV / decade, breaking the theoretical limit of traditional field-effect transistors (60 mV / decade), and its operating voltage can reach as low as 0.1 V.

This invention belongs to the field of oxide target technology, specifically disclosing a multi-element doped indium oxide (IGTO) target, its preparation method, and its applications. The raw material components of the multi-element doped IGTO target of this invention include indium oxide, gallium oxide, titanium dioxide, and zirconium oxide. The zirconium-doped IGTO target of this invention has a lower sintering temperature, higher density, and lower resistivity, enabling the preparation of high-performance IGTO thin films with high transmittance and low subthreshold swing, thus improving the stability of thin-film devices and showing great promise for applications in perovskite solar cells. This invention also provides a preparation method and applications for the multi-element doped IGTO target.