5results about How to "Reduced subthreshold swing" patented technology

The invention discloses a manufacturing method of a two-dimensional semiconductor field effect transistor based on a high-k gate dielectric integration technology capable of eliminating a buffer layer. The manufacturing method comprises the following steps: depositing a back gate electrode and a back gate dielectric on a substrate in sequence; transferring the channel layer to the back gate medium; sequentially forming a buffer layer, a source electrode, a drain electrode, a top gate dielectric layer formed by a high-k dielectric material and a top gate electrode on the channel layer; and annealing treatment is carried out in a vacuum environment, and the buffer layer sublimates, so that Van der Waals interfaces are formed between the channel layer and the top gate dielectric layer and between the channel layer and the source electrode as well as between the channel layer and the drain electrode. According to the high-k gate dielectric integration technology based on the erasable buffer layer, the erasable buffer layer after vacuum annealing is utilized, damage to a two-dimensional material is avoided, a high-quality high-k gate dielectric is deposited, interface regulation and control between a channel layer and a top gate dielectric are achieved, and the equivalent oxide thickness is reduced; and good contact between the channel layer and source and drain metal is realized, the contact resistance of the transistor is reduced, and the electrical performance of the transistor is improved.

The application provides a laminated dielectric material and a preparation method and application thereof, and belongs to the technical field of organic electronic devices. The material has a three-layer or multi-layer hafnium oxide (H) / zirconium oxide (Z) / hafnium oxide (H) laminated dielectric structure; the method comprises sequentially sputtering and depositing a hafnium oxide film and a zirconium oxide film, and repeatedly sputtering and depositing in this way; in addition, the material is applied to an organic transistor, and the organic transistor comprises, from bottom to top, a substrate, a dielectric layer (the material), an organic semiconductor layer and source and drain electrodes. The organic transistor has a low working voltage, can reduce the subthreshold swing of the organic transistor to a theoretical physical limit value (even break through the theoretical physical limit value), and the prepared stacked gate dielectric has a high-K dielectric constant and excellent insulation.

This application provides a semiconductor device and a method for manufacturing the same. The semiconductor device includes a substrate, a source electrode, a drain electrode, and a channel structure disposed on one side of the substrate. The channel structure is located between the source electrode and the drain electrode. The channel structure includes a stack of multiple nanosheets, a gate electrode surrounding the nanosheets, and a cavity. The cavity is located at least between the channel structure and the substrate. The cavity is formed by the channel structure, the source electrode, the drain electrode, and the substrate surrounding the cavity. In other words, the cavity is located below the channel structure, the source electrode, and the drain electrode, without any contacting film layers, thus forming a fully floating structure. This can significantly improve the gate control performance of the semiconductor device, reduce the subthreshold swing of the semiconductor device, reduce leakage current and parasitic capacitance, increase the drive current, and improve the performance of the semiconductor device.

The invention discloses a variable-width negative capacitance layer double-gate fin type field effect transistor and a preparation method thereof. The variable-width negative capacitance layer double-gate fin type field effect transistor comprises a semiconductor substrate, a buried oxide layer, a fin type active region, a gate oxide layer, a variable-width negative capacitance layer, an isolation oxide layer, a metal gate and a side wall, the fin type active region comprises a source region, a channel region and a drain region which are sequentially arranged along the length direction; the variable-width negative capacitance layer is symmetrically arranged outside the gate oxide layer, and the widths of the two ends of the variable-width negative capacitance layer are unequal. The two sides of the gate oxide layer are covered with the negative capacitance layer with the width changing along the channel, and the gate voltage is variably amplified and then applied to the two sides of the gate oxide layer by means of the variable voltage amplification effect and the gate-drain coupling effect of the variable width negative capacitance layer, so that the channel control capacity of the fin field effect transistor is improved, and the reliability of the fin field effect transistor is improved. The subthreshold swing of the transistor is reduced, the saturation region current of the transistor is improved, and the common negative differential resistance phenomenon in the negative capacitance field effect transistor is weakened, so that the power consumption of the transistor is reduced, and the performance of the transistor and the performance in a logic circuit are improved.

This invention provides a low-voltage, high-linearity heterojunction HEMT device based on junction field-effect modulation, comprising a substrate, a buffer layer, and a multilayer heterostructure of at least two alternating layers of barrier and channel layers. Source and drain electrodes are located on either side of the barrier layer and extend into the buffer layer. A passivation layer is formed on the upper surface of the barrier layer. A gate trench is formed in the middle region of the passivation layer, extending through the passivation layer to the upper surface of the barrier layer. The gate electrode includes multiple discrete gate pillars and a gate cap. The multiple discrete gate pillars are periodically arranged along the gate width direction, located within the gate trench, and extend through at least two alternating layers of barrier and channel layers into the buffer layer. The gate cap is located on the upper surface of the multiple discrete gate pillars, supported by the pillars, and has no contact with the passivation and barrier layers. A metal interconnect layer is electrically connected to the source and drain electrodes. This design achieves both low subthreshold swing and meets the application requirements of low power consumption and high linearity.