168results about How to "Reduced subthreshold swing" patented technology

The invention provides a heterojunction carbon nano-tube field effect transistor of which a subthreshold swing is smaller than 60 millivolt/magnitude in the room temperature and a preparation method thereof. The device uses the semiconductor carbon nano-tube as the active layer, the heterojunction formed by the graphene layer and the semiconductor carbon nano-tube is used as the source end of the device, the gate medium and the gate electrode modulate the carbon nano-tube channel and the graphene/carbon nano-tube junction at the same time, so that the turn-off of the transistor is accelerated by using the character that the graphene/carbon nano-tube junction barrier is modulated by the gate voltage. The transistor can control the polarity through the selection of the source-drain metal, namely the metal of high power function is used as the source-drain electrode for realizing the p-type field effect transistor, and the metal of low power function is used as the source-drain electrode for realizing the n-type field effect transistor.

The invention belongs to the technical field of preparation of semiconductor thin films, and particularly relates to a low-temperature treatment method for producing an indium gallium zinc oxide (IGZO) semiconductor thin film by using a sol-gel method. The method comprises the following steps of: dissolving In(NO3)3.4*5H2O, Ga(NO3)3.4*5H2O and Zn(C2H3O2)2*5H2O into ethylene glycol monomethyl ether serving as a solvent and monoethanolamine serving as a stabilization agent to form a clear stable precursor solution; and coating the precursor solution on a glass substrate in a rotatable manner, and irradiating by using an infrared heating lamp to obtain the flat and transparent IGZO semiconductor thin film. Compared with the conventional method for preparing the IGZO thin film through annealing of a heat plate by using the sol-gel method, the method has the advantages that the IGZO thin film irradiated by the infrared heating lamp is relatively high in semiconductor and optical properties, and the process temperature is relatively low and lower than 250 DEG C; the IGZO thin film is used as a thin film transistor with a trench layer material; the switch current ratio is more than 5*10<6>; the saturated migration rate is more than 1.8 cm<2>/Vs; and the subthreshold amplitude is less than 2.2 V/dec.

The invention provides an inorganic metal oxide semiconductor film of a perovskite structure and a metallic oxide thin film transistor. The inorganic metal oxide semiconductor film of the perovskite structure is used as an active layer. The inorganic metal oxide semiconductor film of the perovskite structure is expressed as the chemical expression: MxA1-xBo3, wherein 0.01<=x<=0.5, A is at least one chemical element of Ca, Sr and Ba, B is a chemical element of Ti and Sn, and M is at least one chemical element of Sc, Y, rare earth elements, Al and In. The inorganic metal oxide semiconductor film of the perovskite structure is composed of crystal particles of the perovskite structure, and sizes of the crystal particles vary from 2mm to 900mm. The thickness of the inorganic metal oxide semiconductor film of the perovskite structure varies from 10nm to 500nm. When the inorganic metal oxide semiconductor film of the perovskite structure is used as the active layer, electronic mobility is high, and the metallic oxide thin film transistor prepared by using the inorganic metal oxide semiconductor film of the perovskite structure is good in light stability, low in sub-threshold swing amplitude, simple in preparation technology and low in cost.

The invention discloses an aluminum zinc oxide amorphous semiconductor film material and a preparation method and application thereof and belongs to the technical field of semiconductor integrated circuits and manufacture thereof. The amorphous semiconductor film comprises, by mole percent content, 85-98% of zinc element, 1-10% of aluminum element and 1-14% of rare earth element, wherein the rare earth element is at least one of Gd, Lu, Y and Sc. A radio frequency magnetron sputtering method is adopted to prepare the aluminum zinc oxide film material doped with the rare earth element, the voltage division ratio of oxygen atmosphere is adjusted in the sputtering process to form a channel material which has amorphous characteristics and is high in migration rate. The preparation method is compatible with a traditional complementary metal oxide semiconductor (CMOS) process, and a rare earth doped oxide semiconductor film transistor can be prepared, is high in practical value and can be applied to future thin film transistor (TFT) integrated circuits.

The invention provides a display panel and a display device, and relates to the technical field of display. The display substrate comprises a switch transistor and a drive transistor. The switch transistor and the drive transistor comprise active layers which comprise a first active layer in the switch transistor and a second active layer in the drive transistor gate insulating layers which are disposed on the active layers and comprise a first gate insulating layer in the switch transistor and a second gate insulating layer in the drive transistor. The first gate insulating layer comprises afirst silicon nitride layer and a first silicon oxide layer. The second gate insulating layer just comprises a second silicon oxide layer, and the thickness of the second silicon oxide layer is greater than the thickness of the first silicon oxide layer; or the second gate insulating layer comprises a second silicon nitride layer and a second silicon oxide layer, wherein the thickness of the second silicon oxide layer is greater than the thickness of the first silicon oxide layer, and the thickness of the second silicon nitride layer is less than the thickness of the first silicon nitride layer. The display panel can meet the quick start demands of the switch transistor while achieving the better definition of gray scale.

The invention provides a dual-gate field-effect transistor which comprises a device layer, a source, a drain, a channel region positioned between the source and the drain, a first gate structure and a second gate structure, wherein the device layer comprises a first surface and a second surface which are opposite to each other; the source and the drain are positioned in the device layer, isolated mutually and have different conduction types; the channel region sequentially comprises a first pocket injection region, a source connection region and a second pocket injection region from the first surface to the second surface of the device layer, the first and the second pocket injection regions are electrically connected with the drain, and the source connection region is electrically connected with the source; the first gate structure is positioned on the first surface of the device layer and corresponds to the position of the first pocket injection region; and the second gate structure is positioned on the second surface of the device layer and corresponds to the position of the second pocket injection region. The dual-gate field-effect transistor has high response speed and sensitive switching property, and can meet the demand of reducing the energy consumption after scaling down a device under small size and avoid the production of a series of secondary effects.

The invention provides a method for manufacturing a flexible IGZO (In-Ga-Zn-O) thin film transistor. The method comprises the following steps: step one, cleaning a flexible substrate; step two, depositing SiNx isolating layer by using PECVD (Plasma Enhanced Chemical Vapor Deposition); step three, preparing a gate electrode pattern; step four, preparing a gate insulating layer; step five, preparing an IGZO semiconductor layer; step six, preparing a source drain electrode; and step seven, preparing a protection layer. As the deposition temperature is reduced, and the deposition power of the protection layer and the thickness of a silicon nitride insulating layer are optimized, a flexible IGZO-TFT (Thin Film Transistor) device is manufactured successfully, the performances of the flexible IGZO-TFT are as follows: the threshold voltage is 8V, the switching ratio is 5*107, the saturated migration rate is 7.8cm2/V.s, and the subthreshold slope factor is 0.9V/dec; the device is arranged on a cylinder with the curvature radius being 10mm is bent for 3 minutes, and the performances can not be changed basically; and the protection layer plays an important role in the stability of the device.

The invention discloses a low temperature poly silicon thin film transistor and a fabrication method thereof. The low temperature poly silicon thin film comprises a substrate, a shading layer, a buffer layer, a poly silicon layer, a gate insulation layer, a gate and at least gate surrounding channel. With the design of the gate surrounding channel, the leakage current generated by the thin film transistor can be effectively reduced.

The embodiment of the invention provides an array substrate, a manufacturing method of the array substrate and a display device, relates to the technical field of display. The number of sensor drivingcircuits per unit area is increased. The array substrate comprises a sensor driving circuit, and the sensor driving circuit comprises a first transistor which comprises a first active layer, a firstgrid electrode connected with a first control signal line, a first source electrode and a first drain electrode; a second transistor which comprises a second active layer, a second grid electrode connected with the first drain electrode, a second source electrode and a second drain electrode; a third transistor which comprises a third active layer, and a third grid electrode, a third source electrode and a third drain electrode which are connected with the second control signal line; wherein the first control signal line, the second control signal line, the first gate and the third gate are positioned on the first film layer; the first source electrode, the second source electrode, the second drain electrode, the third source electrode and the third drain electrode are located on the second film layer, the first drain electrode and the second grid electrode are located on the third film layer, the first film layer, the second film layer and the third film layer are located on differentlayers, and the first drain electrode is connected with the first active layer through a via hole.

The invention belongs to the technical field of preparation of transistors, and in particular relates to a titanium aluminum oxide thin film and a preparation method and application thereof. The aluminum oxide titanium thin film is prepared by a sol-gel method. The method comprises the following steps of: with ethylene glycol monomethyl ether as a solvent and concentrated hydrochloric acid as an additive, dissolving Al(C4H9O)3 and Ti(C4H9O)4 in the solvent to form a clear and stable precursor solution; and spirally coating the precursor solution on a glass substrate, and obtaining the aluminum oxide titanium thin film after thermal pretreatment and subsequent high-temperature heat treatment. The invention further relates to a preparation method of a thin film transistor by using titanium aluminum oxide as a gate dielectric layer. According to the IZO thin film transistor with the titanium aluminum oxide as the gate dielectric layer, the switching current ratio is greater than 1*10<6>, the saturation migration rate is greater than 1.1cm<2>/Vs, and the subthreshold amplitude is less than 1.5V/dec.

The invention belongs to the technical field of thin film transistors and particularly relates to a manufacture method of a thin film transistor and with indium zinc aluminum oxide as a channel layer. The method utilizes aluminum to be mingled with indium zinc aluminum oxide to obtain an indium zinc aluminum oxide semiconductor film and improve performance of the channel layer of an indium zinc aluminum oxide semiconductor. The manufacture method utilizes the impregnation pulling method process which is low in cost, simple in process, easy to prepare in large area to prepare an indium zinc aluminum oxide thin film which is smooth in surface and even and compact in thickness, and the indium zinc aluminum oxide thin film is applied to manufacture of oxide thin film transistors. A manufactured thin film transistor device is good in comprehensive performance and has high saturation migration rate which is 26.8cm<2>/Vs and low subthreshold amplitude which is 0.24V/decade. The switch ratio is larger than 104.

The invention discloses a semiconductor device having a back gate connected with a negative capacitor, a manufacturing method for the semiconductor device, and electronic equipment including the semiconductor device. According to embodiments, the semiconductor device can comprise a transistor and the negative capacitor, wherein the transistor can comprise a control gate and the back gate, and the negative capacitor is connected with the back gate in series.

The invention discloses a semiconductor device and a manufacturing method thereof and electronic equipment comprising the semiconductor device. The semiconductor device comprises multi-gate FinFETs, wherein one of gates of the multi-gate FinFETs is connected to a negative capacitor. According to the embodiment, the semiconductor device can comprise the first FinFET, the second FinFET and the negative capacitor; the first FinFET can comprise first fins and gates; the first fins are formed on a substrate; the gates are formed on the substrate and are intersected with the first fins; the second FinFET can comprise second fins, first gates and second gates; the second fins are formed on the substrate; each first gate is formed at the first side of the corresponding second fin on the substrate and is intersected with the corresponding second fin; each second gate is formed at the second side, opposite to the first side, of the corresponding second fin on the substrate, is intersected with the corresponding second fin and is opposite to the corresponding first gate; and the negative capacitor is connected to the second gates of the second FinFET.

The present invention discloses an organic light-emitting display device and a manufacturing method thereof. The organic light-emitting display device includes a switching thin film field effect transistor, a driving thin film field effect transistor, and a storage capacitor connected with the switching thin film field effect transistor and the driving thin film field effect transistor; the switching thin film field effect transistor is provided with a first active layer for reducing the subthreshold swing of the transfer characteristic curve of the switching film field effect transistor; and the driving thin film field effect transistor is provided with a second active layer for increasing the subthreshold swing of the transfer characteristic curve of the driving thin film field effect transistor. According to the organic light-emitting display device of the invention, fast switching on and switching off of the switching thin film field effect transistor and slow debugging of the grayscale of an OLED (Organic Light Emitting Diode) by the driving thin film field effect transistor can be simultaneously realized.

The embodiment of the invention discloses an array substrate, a preparation method thereof and a display panel, the array substrate comprises a thin film transistor array layer, and the thin film transistor array layer comprises a driving transistor, a switching transistor and a capacitor; wherein the driving transistor comprises a first active layer, a first gate insulating layer, a first gate and an insulating dielectric layer which are stacked in sequence; the switching transistor comprises a second active layer, a second gate insulating layer and a second gate which are sequentially stacked; wherein the insulating dielectric layer and the second gate insulating layer are the same layer; the thickness of the first gate insulating layer is larger than that of the second gate insulating layer, so that the sub-threshold swing of the driving transistor is large, meanwhile, the sub-threshold swing of the switching transistor is small, and the driving capacity of the driving transistor and the switching control capacity of the switching transistor can be guaranteed at the same time.

The invention discloses an array substrate, a preparation method thereof, a display panel and a device. The array substrate comprises a pixel circuit, the pixel circuit comprises a first transistor and a second transistor, the first transistor comprises a first active layer, the second transistor comprises a second active layer, and both the first active layer and the second active layer comprisesilicon; the array substrate further comprises a first type inorganic layer, a second type inorganic layer and a first via hole, the first via hole is located above the first active layer and at leastpenetrates through the second type inorganic layer, and the hydrogen ion concentration in the first active layer is smaller than that in the second active layer. The first active layer is subjected to high-temperature processing through the first via hole, so that the hydrogen ion concentration in the first active layer is smaller than that in the second active layer, the high-temperature processing frequency of the second transistor is reduced while good performance of the first transistor is guaranteed, and it is guaranteed that the second transistor is small in sub-threshold swing, good inturn-off characteristic and small in leakage current; and good overall characteristics of the pixel circuit are ensured.

The invention provides a preparation method for a low-temperature film transistor. A large-area uniform film transistor with the excellent performances can be prepared without annealing, and the method comprises the following steps: 1, placing a substrate provided with a conductive film in a deposited manner into an ALD reaction cavity, and then carrying out the vacuum pumping and heating processing; 2, growing a high-k material under the temperature from the room temperature to 120 DEG C as a grid insulating layer, wherein k is 7-170, and the thickness of the grid insulating layer is 15-150nm; 3, carrying out the direct in-situ growing of a ZnO trench layer under the temperature from the room temperature to 120 DEG C, wherein the thickness of the ZnO trench layer is 10-50nm; 4, carrying out the ultraviolet exposure of the device obtained at step 3, carrying out the secondary photoetching after the trench etching, carrying out the evaporation of the source and drain electrodes, and preparing a bottom-grid low-temperature film transistor without annealing.