Negative capacitance-based surrounding gate field effect transistor and manufacturing method thereof

A technology of a field effect transistor and a manufacturing method, which is applied in the field of gate-around field effect transistors based on negative capacitance and its manufacturing field, can solve the problems of complex manufacturing process and high sub-threshold swing of field effect transistors, achieve simple manufacturing process, and reduce production cost effect

Inactive Publication Date: 2018-03-27
ZING SEMICON CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0013] In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide a negative capacitance-based gate-all-round field effect transistor and its manufacturing method, which are used to solve the problem of high subthreshold swing and manufacturing process of field effect transistors in the prior art. complicated question

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  • Negative capacitance-based surrounding gate field effect transistor and manufacturing method thereof
  • Negative capacitance-based surrounding gate field effect transistor and manufacturing method thereof
  • Negative capacitance-based surrounding gate field effect transistor and manufacturing method thereof

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Embodiment 1

[0074] The present invention provides a gate-all-around field effect transistor based on negative capacitance, wherein a ferroelectric material layer is formed between the high-K dielectric layer and the metal gate layer of the gate structure of the gate-all-around field effect transistor based on negative capacitance; The layer of ferroelectric material has a negative capacitance.

[0075] Specifically, a ferroelectric material refers to a dielectric material that has spontaneous polarization within a certain temperature range, and the direction of the spontaneous polarization can be changed by changing the direction of an applied electric field.

[0076] As an example, the material of the ferroelectric material layer includes HfZrO 2 (zirconium hafnium oxide), PZT (lead zirconate titanate, the chemical formula is Pb(Zr,Ti)O 3 ), SBT (strontium bismuth tantalate, the chemical formula is SrBi 2 TaO 9 ), BRT ((Bi,R) obtained by doping rare earth elements R such as La, Nd, et...

Embodiment 2

[0087] The present invention also provides a method for manufacturing a gate-all-around field effect transistor based on negative capacitance, comprising the following steps:

[0088] First execute step S1: Figure 8 As shown, an SOI substrate including a Si substrate 1 , an insulating buried layer 2 and a top layer of silicon 3 is provided sequentially from bottom to top.

[0089] As an example, the insulating buried layer 2 is made of silicon oxide, and its thickness ranges from 150-350 nm. The thickness range of the top layer silicon 3 is 50-90nm.

[0090] Then execute step S2: as Figure 9-Figure 11 As shown, the top layer of silicon 3 is patterned, and at least one Si nanowire 4 is formed in the top layer of silicon 3 . in, Figure 9 Shown as a top view of the structure obtained in this step, Figure 10 shown as Figure 9 The A-A' direction sectional view of the structure shown, Figure 11 shown as Figure 9 B-B' sectional view of the structure shown.

[0091] Sp...

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Abstract

The invention provides a negative capacitance-based surrounding gate field effect transistor and a manufacturing method thereof. A ferroelectric material layer is formed between a high-K dielectric layer and a metal gate layer of a gate region structure of the negative capacitance-based surrounding gate field effect transistor; and the ferroelectric material layer has negative capacitance. The ferroelectric material layer with negative capacitance is used as a built-in voltage amplifier, so that the subthreshold range of oscillation of the device can be lowered to be 60mV / decade or below. Thetransistor adopts Si nanowires as a channel material, and the high-K metal gate fully surrounds the Si nanowires, so that higher gate control capability can be obtained and a short channel effect canbe avoided. The manufacturing method of the negative capacitance-based surrounding gate field effect transistor is simple in manufacturing process, and lowering of production cost can be facilitated.

Description

technical field [0001] The invention belongs to the field of semiconductor manufacturing, and relates to a ring gate field effect transistor based on negative capacitance and a manufacturing method thereof. Background technique [0002] Conventional FETs require at least a 60mV change in gate voltage at 300K to produce a 10-fold (an order of magnitude) change in current. The minimum subthreshold slope determines the basic lower operating voltage. [0003] figure 1 A schematic diagram of the structure of an existing field effect transistor is shown in , where S represents the source region, D represents the drain region, Channel represents the channel region, oxide represents the gate oxide layer, G represents the gate, and V gs represents the gate-source voltage, V ds represents the source-drain voltage, t ox Represents the thickness of the gate oxide layer. [0004] figure 2 show figure 1 Longitudinal circuit schematic diagram of the structure shown, where C ox rep...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/78H01L21/336
CPCH01L29/6684H01L29/78391B82Y10/00H01L29/513H01L29/516H01L29/775H01L29/0673H01L29/66439H01L29/42392H01L29/78696
Inventor 刘源保罗·邦凡蒂
Owner ZING SEMICON CORP
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