12 results about "Subthreshold slope" patented technology

The invention provides a TFET device and a forming method thereof, and the TFET device comprises a semiconductor substrate, a gate structure is formed on the surface of the semiconductor substrate, and the gate structure comprises a first side and a second side which are opposite to each other; the source electrode is located in the semiconductor substrate on the first side of the gate structure; and the tunneling dielectric layer is positioned on the side wall of the first side of the gate structure, and the source electrode is close to the side wall of the gate structure. According to the TFET device, the source electrode and the channel are isolated through the tunneling dielectric layer, a traditional BTB-tunneling mechanism is replaced with an FN-tunneling mechanism, the bipolar effect of the TFET device can be weakened, the subthreshold slope of the TFET device is steeper, meanwhile, leakage current is reduced, and therefore the performance of the device is improved.

The invention relates to the technical field of semiconductor devices, in particular to a GaN HEMT device and a manufacturing method thereof. According to the invention, a multi-channel heterojunction epitaxial structure is adopted to prepare the device, current coupling among multiple channels is realized by forming a gate structure and a GaN secondary epitaxial technology, the on-resistance of the device is remarkably reduced, and meanwhile, the turn-off / turn-on voltage of a side wall channel and a bottom groove channel is unified through an n-type GaN intermediate layer formed by secondary epitaxy, so that the on-resistance of the device is improved. The problem of asynchronous turn-off / turn-on of the gate region is avoided, and the gate control capability of the device is effectively improved. In addition, by changing the doping concentration of the n-type GaN intermediate layer, the threshold voltage of the device can be regulated and controlled in a large range. According to the characteristics, the GaN HEMT transistor with high conduction current density, low subthreshold slope and adjustable threshold voltage can be realized.

Device structures and related fabrication methods for asymmetric MOSFETs that exhibit high BVDSS and low HCl characteristics while substantially improving the poor sub-threshold slope and output resistance ROUT characteristics common to conventional asymmetric MOSFET devices. Embodiments are fabricated by implanting halo and / or LDD dopants on the source-side of an asymmetric MOSFET using at least two different non-90° twist angles, each in a different quadrant. By implanting dopant at different twist angles, dopant is implanted within otherwise shadowed corners, thus essentially eliminating the parasitic transistors within such corners. Optionally, an extra implantation of halo / LDD dopants may be performed at a 90° twist angle. As a result, a non-90°, multi-twist implanted asymmetric MOSFET exhibits improved linearity and an essentially equivalent gain characteristic compared to conventional asymmetric MOSFETs. Optionally, thick spacers may be used. The asymmetric MOSFETs are quite suitable for applications, such as power amplifiers, which require good linearity and gain characteristics.

This invention relates to the field of semiconductor device technology, specifically to a gallium nitride (GaN) P-MOSFET transistor structure and its manufacturing method. The invention employs a double heterojunction epitaxial structure for device fabrication, utilizing grooved gate technology to realize an enhancement-mode GaN P-MOSFET transistor while restoring the two-dimensional electron gas (2DEG) channel in the gate region. Based on this, an electrical connection is established between the 2DEG channel and the device gate, introducing a back gate. Furthermore, by inserting an AlN layer on the upper or lower side of the AlGaN barrier layer, leakage current from the source to the gate is suppressed, ensuring the back gate's control over the P-type conductive channel. This invention fully utilizes the characteristics of the double heterojunction channel, realizing a back gate structure without using back-side processing, providing an effective solution for achieving P-type channel GaN transistor devices with low subthreshold slope and high on-current density.

The invention relates to the technical field of MOS (metal oxide semiconductor), and discloses a terminal structure with lateral variable doping, which comprises a metal drain, a semiconductor epitaxial layer and source metal, and is characterized in that the semiconductor epitaxial layer comprises a substrate layer and a diffusion layer, and the diffusion layer comprises an active region, a main junction and a multi-region junction terminal expansion structure; the source electrode metal comprises a left section and a right section, polycrystalline silicon is deposited in the left section of the source electrode metal and between the left section of the source electrode metal and the right section of the source electrode metal, an interlayer medium is deposited on the surface of the polycrystalline silicon, gate electrode metal is arranged between the left section of the source electrode metal and the right section of the source electrode metal, and the gate electrode metal is in ohmic contact with the polycrystalline silicon. According to the method, the device performance and the device reliability after ion implantation are subjected to sampling detection, and the sampling detection needs to be carried out according to the subthreshold slope of the semiconductor device, the difference value of the threshold voltage and the source-drain breakdown voltage, so that the electrical performance and the reliability of the sampled semiconductor device can be quickly judged.

This application provides a semiconductor device and its fabrication method. The device includes: a second substrate; a void layer located on one side of the second substrate; a nanosheet stack layer located on the side of the void layer away from the second substrate; the nanosheet stack layer comprises a stack of multiple nanosheets; the nanosheets are formed of a semiconductor material; the nanosheet stack layer constitutes multiple conductive channels; a surrounding gate surrounds the nanosheet stack layer; and source and drain electrodes located at both ends of the nanosheet stack layer; the source and drain electrodes are made of semiconductor materials doped with conductive elements. Therefore, by setting the void layer, this application can avoid the influence of the bottom parasitic channel effect, thereby reducing the influence of leakage current and gate capacitance, and further improving the electrical performance of the device. It can effectively solve the influence of the self-heating effect in the stacked nanosheets. It effectively reduces the drain-induced barrier reduction effect and improves parameters such as subthreshold slope and on / off ratio.

The invention discloses a method, a device, equipment and a medium for predicting the service life of a device, relates to the technical field of reliability engineering, accelerated service life testing and data modeling of semiconductor devices, and aims to accurately and efficiently predict the service life of the device. The device life prediction method comprises the following steps: carrying out a stress test on a target device, and determining a first degradation factor of the target device; the first degradation factor is determined at least based on the threshold voltage, the sub-threshold slope and the conduction current of the target device in the stress test process; determining a first degradation rate of the target device according to the first degradation factor; and performing life prediction on the target device by using a pre-constructed life prediction model in combination with the first degradation rate, and determining the predicted life of the target device. The method is beneficial to improving the accuracy of predicting the service life of the target device, and solves the problem that the predicted service life of the device is greatly different from the actual service life of the device due to the fact that only a single degradation parameter is used in the traditional device service life prediction process.

In one embodiment, a transistor includes a substrate, a buffer layer on the substrate a channel layer on the buffer layer, and one or more polarization layers on the channel layer. The one or more polarization layers include a group III-N material comprising a first group III constituent and a second group III constituent. The transistor further includes a plurality of p-type doped layers on the one or more polarization layers. Each of the plurality of p-type doped layers includes a first p-type dopant and the III-N material, wherein each successive layer of the first p-type doped layers has a lower proportion of the first group III constituent to the second group III constituent relative to a layer below it. The transistor also includes a p-type doped layer on the plurality of p-type doped layers comprising a second p-type dopant and a group III-N material.

Device structures and related fabrication methods for asymmetric MOSFETs that exhibit high BVDSS and low HCI characteristics while substantially improving the poor sub-threshold slope and output resistance ROUT characteristics common to conventional asymmetric MOSFET devices. Embodiments are fabricated by implanting halo and / or LDD dopants on the source-side of an asymmetric MOSFET using at least two different non-90° twist angles, each in a different quadrant. By implanting dopant at different twist angles, dopant is implanted within otherwise shadowed corners, thus essentially eliminating the parasitic transistors within such corners. Optionally, an extra implantation of halo / LDD dopants may be performed at a 90° twist angle. As a result, a non-90°, multi-twist implanted asymmetric MOSFET exhibits improved linearity and an essentially equivalent gain characteristic compared to conventional asymmetric MOSFETs. The novel asymmetric MOSFETs are quite suitable for applications, such as power amplifiers, which require good linearity and gain characteristics.

Device structures and related fabrication methods for asymmetric MOSFETs that exhibit high BVDSS and low HCI characteristics while substantially improving the poor sub-threshold slope and output resistance ROUT characteristics common to conventional asymmetric MOSFET devices. Embodiments are fabricated by implanting halo and / or LDD dopants on the source-side of an asymmetric MOSFET using at least two different non-90° twist angles, each in a different quadrant. By implanting dopant at different twist angles, dopant is implanted within otherwise shadowed corners, thus essentially eliminating the parasitic transistors within such corners. Optionally, an extra implantation of halo / LDD dopants may be performed at a 90° twist angle. As a result, a non-90°, multi-twist implanted asymmetric MOSFET exhibits improved linearity and an essentially equivalent gain characteristic compared to conventional asymmetric MOSFETs. Optionally, thick spacers may be used. The asymmetric MOSFETs are quite suitable for applications, such as power amplifiers, which require good linearity and gain characteristics.

Negative capacitance field-effect transistor (NCFET) and ferroelectric field-effect transistor (FE-FET) devices and methods of forming are provided. The gate dielectric stack of the NCFET and FE-FET devices includes a non-ferroelectric interfacial layer formed over the semiconductor channel, and a ferroelectric gate dielectric layer formed over the interfacial layer. The ferroelectric gate dielectric layer is formed by inserting dopant-source layers in between amorphous high-k dielectric layers and then converting the alternating sequence of dielectric layers to a ferroelectric gate dielectric layer by a post-deposition anneal (PDA). The ferroelectric gate dielectric layer has adjustable ferroelectric properties that may be varied by altering the precisely-controlled locations of the dopant-source layers using ALD / PEALD techniques. Accordingly, the methods described herein enable fabrication of stable NCFET and FE-FET FinFET devices that exhibit steep subthreshold slopes.

The present application relates to the technical field of electronic products, and provides a transistor, a driving backplane, a display screen, and an electronic device, configured to solve the difficulty in ensuring a large on-state current for transistors, and to avoid brightness jumps and uneven brightness in display screens at low grayscale and low brightness levels. Specifically, the transistor comprises a gate, an insulating layer, a source, a drain, and a plurality of channels. The insulating layer is connected onto the gate. The source and the drain are spaced apart. The plurality of channels are spaced apart, and each channel is connected to the side of the insulating layer facing away from the gate and is connected between the source and the drain. The plurality of channels comprise a first channel and a second channel. A subthreshold slope of the first channel is greater than a subthreshold slope of the second channel, and a threshold voltage of the first channel is less than a threshold voltage of the second channel.