4 results about "Subthreshold slope" patented technology

The invention relates to the technical field of semiconductor devices, in particular to a GaN HEMT device and a manufacturing method thereof. According to the invention, a multi-channel heterojunction epitaxial structure is adopted to prepare the device, current coupling among multiple channels is realized by forming a gate structure and a GaN secondary epitaxial technology, the on-resistance of the device is remarkably reduced, and meanwhile, the turn-off / turn-on voltage of a side wall channel and a bottom groove channel is unified through an n-type GaN intermediate layer formed by secondary epitaxy, so that the on-resistance of the device is improved. The problem of asynchronous turn-off / turn-on of the gate region is avoided, and the gate control capability of the device is effectively improved. In addition, by changing the doping concentration of the n-type GaN intermediate layer, the threshold voltage of the device can be regulated and controlled in a large range. According to the characteristics, the GaN HEMT transistor with high conduction current density, low subthreshold slope and adjustable threshold voltage can be realized.

This application provides a semiconductor device and its fabrication method. The device includes: a second substrate; a void layer located on one side of the second substrate; a nanosheet stack layer located on the side of the void layer away from the second substrate; the nanosheet stack layer comprises a stack of multiple nanosheets; the nanosheets are formed of a semiconductor material; the nanosheet stack layer constitutes multiple conductive channels; a surrounding gate surrounds the nanosheet stack layer; and source and drain electrodes located at both ends of the nanosheet stack layer; the source and drain electrodes are made of semiconductor materials doped with conductive elements. Therefore, by setting the void layer, this application can avoid the influence of the bottom parasitic channel effect, thereby reducing the influence of leakage current and gate capacitance, and further improving the electrical performance of the device. It can effectively solve the influence of the self-heating effect in the stacked nanosheets. It effectively reduces the drain-induced barrier reduction effect and improves parameters such as subthreshold slope and on / off ratio.

The invention discloses a method, a device, equipment and a medium for predicting the service life of a device, relates to the technical field of reliability engineering, accelerated service life testing and data modeling of semiconductor devices, and aims to accurately and efficiently predict the service life of the device. The device life prediction method comprises the following steps: carrying out a stress test on a target device, and determining a first degradation factor of the target device; the first degradation factor is determined at least based on the threshold voltage, the sub-threshold slope and the conduction current of the target device in the stress test process; determining a first degradation rate of the target device according to the first degradation factor; and performing life prediction on the target device by using a pre-constructed life prediction model in combination with the first degradation rate, and determining the predicted life of the target device. The method is beneficial to improving the accuracy of predicting the service life of the target device, and solves the problem that the predicted service life of the device is greatly different from the actual service life of the device due to the fact that only a single degradation parameter is used in the traditional device service life prediction process.

The present application relates to the technical field of electronic products, and provides a transistor, a driving backplane, a display screen, and an electronic device, configured to solve the difficulty in ensuring a large on-state current for transistors, and to avoid brightness jumps and uneven brightness in display screens at low grayscale and low brightness levels. Specifically, the transistor comprises a gate, an insulating layer, a source, a drain, and a plurality of channels. The insulating layer is connected onto the gate. The source and the drain are spaced apart. The plurality of channels are spaced apart, and each channel is connected to the side of the insulating layer facing away from the gate and is connected between the source and the drain. The plurality of channels comprise a first channel and a second channel. A subthreshold slope of the first channel is greater than a subthreshold slope of the second channel, and a threshold voltage of the first channel is less than a threshold voltage of the second channel.