41results about How to "Steep subthreshold slope" patented technology

The invention discloses a tunneling field effect transistor based on a two-dimensional material/semiconductor hetero-junction and a preparation method thereof. A device forms an interleaved energy band structure in the off state through the energy band design, namely, a tunneling window is inexistent between the two-dimensional material and the semiconductor material, and the ultra-low off-state current can be acquired; the grid voltage can be applied to regulate an energy band alignment way at the two-dimensional material/semiconductor hetero-junction so that the device can form the staggered energy band structure in the on-state, and the effective tunneling barrier height is a negative value; and meanwhile, the current carrier tunnels to a channel region from a source region to realize the direct tunneling, thereby acquiring large on-state current. The device adopts the highly-doped three-dimensional semiconductor material as the source region material, and the three-dimensional semiconductor material and the metal source electrode are unipotential; since the thickness of the two-dimensional material is ultra-thin, the grid voltage can regulate the two-dimensional material and the energy band at the two-dimensional material/semiconductor hetero-junction interface, thereby acquiring an ideal grid control capacity. The tunneling field effect transistor disclosed by the invention is simple in process, and large in compatibility with the traditional semiconductor process.

The invention provides a tunneling field effect transistor (TFET) with a T-shaped grid structure and low power consumption, and belongs to the field of field effect transistor logic devices and circuits in complementary metal oxide semiconductor (CMOS) ultra large scale integrated circuits (ULSI). The TFET comprises a source electrode, a drain electrode and a control grid, wherein the control grid extends toward the end of the source electrode to form a T shape; the T-shaped control grid consists of an extending grid region and the original control grid region; and an active region covered below the extending grid region is a channel region and is made of a substrate material. By using the T-shaped grid structure, the source region of the TFET encircles a channel, so that the conduction current of a device is improved. Compared with the conventional planar TFET, the TFET can achieve higher conduction current and steeper subthreshold slope under the same process conditions and the same size of the active region.

The invention provides a tunneling field effect transistor inhibiting output non-linear opening. The tunneling field effect transistor comprises a tunneling source region, a channel region, a drain region, a semiconductor substrate region, a gate dielectric layer and a control gate, wherein the gate dielectric layer is positioned above the channel region, the control gate is positioned above the gate dielectric layer, the channel region is positioned above the channel source region, in addition, the position of the channel region is partially overlapped with the tunneling source region, a tunneling junction is formed at the interface part of the channel region and the tunneling source region, the drain region is parallel to the channel region and is positioned at the other side of the channel region, the control gate is positioned above the overlapping part of the channel region and the tunneling source region, a control-gate-free region is arranged in the channel region near the drain region, and in addition, the channel region adopts semiconductor materials with the energy state density being lower than 1E18cm<-3>. The tunneling field effect transistor has the advantages that the nonlinear opening phenomenon in the device output characteristics can be effectively inhabited, and in addition, the steeper and straighter sub-threshold slope is maintained.

The invention discloses a tunneling field effect transistor (TFET) and a manufacturing method thereof, which belong to the fields of logic devices and circuits of field effect transistors. A high-doping source region of the TFET consists of a P<+> high-doping region and an N<+> high-doping region, and threshold values of a metal-oxide semiconductor field effect transistor (MOSFET) part and a TFET part of a device can be adjusted through ingenious layout variation, so that the performance of a TFET device is improved, and the manufacturing method is simple. Compared with the conventional TFET, the TFET has the advantages that: higher switch-on current can be obtained and a steep subthreshold gradient can be kept by the device under the condition of the same process and the same active region size, so that the TFET is expected to be used in a low power consumption field and has higher practical value.

The invention discloses a two-dimensional semiconductor material negative capacitance field effect transistor and a preparation method thereof; a two-dimensional alloy semiconductor material HfZrSe2 is adopted as a channel material, and the surface of the channel material is oxidized in air to generate HfZrO2, and then annealing is carried out to obtain an HfZrO2 dielectric layer with a ferroelectric property; a high-k gate dielectric layer is deposited on the dielectric layer, and a gate dielectric with a mixed structure is formed. By means of the device structure, high gate dielectric and channel two-dimensional semiconductor material interfaces can be obtained, the deterioration of the interface state on the sub-threshold characteristic is reduced, and the super-steep sub-threshold slope is easily obtained; meanwhile, the high-k gate dielectric on the upper layer can protect the HfZrO2 dielectric of the ferroelectric characteristics below, so that the dielectric is isolated from theair, and the stability of the device is greatly improved. The device is simple in preparation process and large-scale production can be realized.

The invention provides a composite source MOS (Metal Oxide Semiconductor) transistor with schottky barrier and comb-shaped gate structures and a manufacturing method thereof. The composite source MOS transistor comprises a control gate electrode layer, a gate dielectric layer, a semiconductor substrate, a high doped source region and a high doped drain region, wherein one side far away from the channel direction of the high doped source region is connected with a schottky source region; one end of a control gate extends towards the high doped source region; the extended gate region is an extension gate shaped like a comb; the original control gate region is a main gate; the active region covered by the extension gate is likewise a channel region with the substrate material; the high doped source region is formed by the high doping of semiconductor and is located on the two sides of each comb of the extension gate; and a schottky junction is formed at the channel under the schottky source region and the extension gate. Compared with the traditional MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), the composite source MOS transistor can obtain a higher conduction current, a lower leakage current and a steeper subthreshold slope under a same technological condition and a same active region size.

The present invention discloses a tunneling current amplification transistor, which relates to an area of field effect transistor logic devices in CMOS ultra large scale semiconductor integrated circuits (ULSI). The tunneling current amplification transistor includes a semiconductor substrate, a gate dielectric layer, an emitter, a drain, a floating tunneling base and a control gate, wherein the drain, the floating tunneling base and the control gate forms a conventional TFET structure, and a doping type of the emitter is opposite to that of the floating tunneling base. A position of the emitter is at the other side of the floating tunneling base with respect to the drain. A type of the semiconductor between the emitter and the floating tunneling base is the same as that of the floating tunneling base. As compared with the conventional TFET, the tunneling current amplification transistor of the present invention can increase the on-current of the device effectively and increase the driving capability of the device.

The invention provides a biosensor based on a vertical-structure tunneling field effect transistor and a preparation method thereof. The preparation method at least comprises the following steps: step one, preparing the vertical-structure tunneling field effect transistor as a converter, wherein a channel inside the tunneling field effect transistor is suspended, and a vertical structure is formed by the channel, a source electrode and a drain electrode; and step two, carrying out surface activation modification on the surface of the channel by a surface modifying agent. According to the biosensor provided by the invention, the source electrode, the channel and the drain electrode inside the tunneling field effect transistor as the converter adopt the vertical structure, and the channel is in a suspended structure, so that the subthreshold slope of the device is steep; therefore, the induction of the device to the change of surface charges of the channel is sensitive, and the working performance of the biosensor is further improved.

The invention relates to an insulated gate tunneling bipolar transistor with a U-shaped tunneling insulating layer. A gate electrode tunneling current is generated by the U-shaped tunneling insulating layer, and the very sensitive mutual relation between impedance of the tunneling insulating layer and intensity of an internal electric field of the tunneling insulating layer is utilized to enable the U-shaped tunneling insulating layer to implement conversion between a high impedance state and a low impedance state in a very short electric potential change interval of a gate electrode, and thus, compared with the prior art, the insulated gate tunneling bipolar transistor can realize a better switching characteristic; by bipolar amplification, the positive conduction characteristic of a nanoscale insulated gate transistor is obviously improved. The invention also discloses a specific manufacturing method of the insulated gate tunneling bipolar transistor with the U-shaped tunneling insulating layer. Therefore, the working characteristic of a nanoscale integrated circuit unit is obviously improved, and the insulated gate tunneling bipolar transistor and the manufacturing method are suitable for being popularized and applied.

The invention discloses a two-dimensional heterojunction tunneling field effect transistor immunosensor and a preparation method thereof. A two-dimensional material with a specific band gap is selected and stacked into a vertical heterojunction as a channel layer, and the energy band structures of the device in an on state and an off state are respectively in staggered arrangement and staggered arrangement through gate voltage control, low current in the off state is realized, and in an on state, large current is obtained due to inter-band tunneling. A buried gate structure is used, and specific antibody protein molecules are used for surface modification on the surface of the heterojunction modulated by gate voltage. A heterojunction is used as an effective detection area and has ideal grid control capability. The dielectric regulation and control of a detection area is detected along with a detection sample by utilizing a plurality of electrical parameters. The sensor provided by theinvention has a steeper subthreshold slope, can realize ultra-high sensitivity detection of biomolecules and save precious clinical specimens, and meanwhile, because the thickness of a two-dimensional material is ultra-thin, the sensor has great advantages in size reduction and is convenient for energy band regulation and control.

The invention relates to a high-integration-level H-shaped source, drain and gate auxiliary control U-shaped channel high-mobility-ratio junction-free transistor. Two independently-controlled gate electrodes including the H-shaped auxiliary control gate electrode and the gate electrode are adopted, the doping concentration of a device is guaranteed to improve the mobility ratio, the device mobility ratio reduction and the device stability reduction caused by strengthening of the random scattering effect under the high doping concentration is avoided, and meanwhile the resistance of source and drain areas is effectively reduced through the H-shaped auxiliary control gate electrode, so that the contradictions that the source and drain resistance will be increased if the doping concentration of a channel of a common junction-free transistor is excessively low, and the device mobility ratio reduction and the device stability reduction will be caused if the doping concentration is excessively high are overcome; meanwhile, U-shaped monocrystalline silicon serves a channel part of the device; compared with a common plane structure, on the premise that the chip area is not increased additionally, the effective channel length is obviously increased to reduce the short channel effect of the device under the deep nanoscale, and therefore the high-integration-level H-shaped source, drain and gate auxiliary control U-shaped channel high-mobility-ratio junction-free transistor is suitable for application and popularization.