42results about How to "Steep subthreshold slope" patented technology

The invention discloses a junction-modulated type tunneling field effect transistor and a manufacturing method of the junction-modulated type tunneling field effect transistor, and belongs to the field of field effect transistor logic devices and circuits in CMOS ultra large scale integration (ULSI) circuits. According to the junction-modulated type tunneling field effect transistor, a PN junction provided by a highly-doped source region enclosed on three sides in a vertical channel region is utilized so that the channel region can be effectively used up, a surface channel energy band below a grid can be increased, a device can obtain a steeper energy band and a smaller tunneling barrier width compared with a traditional TFET when subjected to band-band tunneling, the effect of a steep tunnel junction doping density gradient is achieved equivalently, as a result, the subthreshold property of the traditional TFET is improved substantially, and breakover currents of the device are increased at the same time. According to the junction-modulated type tunneling field effect transistor and the manufacturing method of the junction-modulated type tunneling field effect transistor, under the condition that the junction-modulated type tunneling field effect transistor is compatible with an existing CMOS process, the bipolar breakover effect of the device is restrained effectively, parasitic tunneling currents at corners of a source junction with a small size also can be restrained, and the effect of steep source junction doping density can be achieved equivalently.

The invention discloses a tunneling field-effect transistor with a composite-mechanism strip-type grid and a preparation method of the tunneling field-effect transistor and belongs to the field of logic devices and circuits of field-effect transistors in CMOS (Complementary Metal Oxide Semiconductor) ultra-large-scale integrated (ULSI) circuits. The tunneling field-effect transistor has the advantages that the energy band of surface channels under the grid can be improved by changing the shape of the grid and utilizing a depletion effect of PN nodes on the two sides of the strip-type grid, and the subthreshold characteristic of the device is improved; since a composite mechanism is introduced into double-doped source areas, an ON state current of the device is improved; due to an I-shaped design of an active area, body leakage currents, including a source-drain direct tunneling current and a punching current, between the two doped source areas to a doped drain area can be greatly inhibited, and a short-channel effect is inhibited, so that the device with small size can be applied.

The invention provides a tunneling field effect transistor inhibiting output non-linear opening. The tunneling field effect transistor comprises a tunneling source region, a channel region, a drain region, a semiconductor substrate region, a gate dielectric layer and a control gate, wherein the gate dielectric layer is positioned above the channel region, the control gate is positioned above the gate dielectric layer, the channel region is positioned above the channel source region, in addition, the position of the channel region is partially overlapped with the tunneling source region, a tunneling junction is formed at the interface part of the channel region and the tunneling source region, the drain region is parallel to the channel region and is positioned at the other side of the channel region, the control gate is positioned above the overlapping part of the channel region and the tunneling source region, a control-gate-free region is arranged in the channel region near the drain region, and in addition, the channel region adopts semiconductor materials with the energy state density being lower than 1E18cm<-3>. The tunneling field effect transistor has the advantages that the nonlinear opening phenomenon in the device output characteristics can be effectively inhabited, and in addition, the steeper and straighter sub-threshold slope is maintained.

The device structure of a double-gate double-strained channel fully depleted SOI MOSFETs disclosed by the present invention includes Si3N4 sidewalls on both sides of the top gate, an active region on one side of the Si3N4 sidewalls, and a drain on the other side of the Si3N4 sidewalls. STI shallow trench isolation regions are set outside the source and drain regions. There is a top gate oxide layer under the top gate and Si3N4 sidewalls. There is a layer of strained Si layer under the top gate oxide layer. There is a strained Si layer under the strained Si layer. A layer of strained SiGe layer, under the strained SiGe layer, there is a layer of bottom gate oxide layer, under the bottom gate oxide layer, there is a bottom gate, on both sides of the bottom gate, there are Si3N4 sidewalls, and the bottom gate is placed in the buried oxide layer. Below the layer is the silicon substrate layer. In the present invention, regardless of the single-gate or double-gate working mode, the driving current of the device when the strained channel is used is higher than that of the bulk silicon channel device; the double-gate mode has a more ideal sub-threshold slope and stronger drive capability than the single-gate mode , higher transconductance and stronger ability to suppress short channel effects.

The invention provides a tunneling field effect transistor (TFET) with a T-shaped grid structure and low power consumption, and belongs to the field of field effect transistor logic devices and circuits in complementary metal oxide semiconductor (CMOS) ultra large scale integrated circuits (ULSI). The TFET comprises a source electrode, a drain electrode and a control grid, wherein the control grid extends toward the end of the source electrode to form a T shape; the T-shaped control grid consists of an extending grid region and the original control grid region; and an active region covered below the extending grid region is a channel region and is made of a substrate material. By using the T-shaped grid structure, the source region of the TFET encircles a channel, so that the conduction current of a device is improved. Compared with the conventional planar TFET, the TFET can achieve higher conduction current and steeper subthreshold slope under the same process conditions and the samesize of the active region.

The invention discloses a two-dimensional heterojunction tunneling field effect transistor immunosensor and a preparation method thereof. A two-dimensional material with a specific band gap is selected to be stacked into a vertical heterojunction as a channel layer. The energy band structures in the on-state and off-state are staggered arrangement and staggered arrangement respectively, achieving low current in the off-state and high current due to inter-band tunneling in the on-state. Using buried gate structure, surface modification with specific antibody protein molecules on the heterojunction surface modulated by gate voltage. As an effective detection area, the heterojunction has the ability to obtain ideal gate control. The detection is realized by using multiple electrical parameters to control the dielectric of the detection area along with the detection sample. The sensor of the present invention has a steeper sub-threshold slope, which can realize ultra-high sensitivity detection of biomolecules and save precious clinical specimens. At the same time, due to the ultra-thin thickness of the two-dimensional material, the device has a great advantage in size reduction, which is convenient for energy saving. With regulation.

The invention provides a low-power consumption tunneling field effect transistor (TFET), belonging to the field of a field effect transistor logic device and a circuit of CMOS (complementary metal oxide semiconductors) ultra large scale integrated circuit (ULSI). The TFET provided by the invention comprises a source, a drain and a control grid, wherein the control grid extends towards a source electrode end into a fork structure, and the fork-structure control grid is composed of an extended grid region and an original control grid region; and the active region which is covered below the extended grid region is similarly a channel region and is made of a substrate material. According to the invention, the channel is enclosed by the source region of the TFET, and the conduction current of the device is improved; and compared with the existing panel TFET, the TFET has provided by the invention has the advantage that under the conditions of the same technology and the same active region size, higher conduction current and a steep subthreshold gradient can be obtained.

The present invention discloses a method for preparing a tunneling field effect transistor, belonging to the field of field effect transistor logic devices in a CMOS super-large-scale integration (ULSI) circuit. The tunneling field effect transistor of an ultra-steep source junction is realized through preparation process design. The device characteristic can be improved significantly, at the same time, the preparation method is compatible with standard CMOS IC technology, TFET devices can be effectively integrated in a CMOS integrated circuit, a low power consumption integrated circuit formed by TFET can be prepared by using standard process, the production cost is greatly reduced, and the process flow is simplified.

The invention provides a vertical-channel double-mechanism conduction nano-wire tunneling transistor and a preparation method. The tunneling transistor comprises a hot electron emission source region, a tunneling source region, a channel region, a tunneling drain region and a gate of a nano-wire. The gate is controlled to encircle the channel; band-to-band tunneling happens at the interface of the tunneling source region and the channel region; the hot electron emission source region, the doping type of which is opposite to that of the tunneling source region, is arranged under the tunneling source region; and the electric potential of the tunneling source region is in floating arrangement, and the source terminal potential of a device is added to the hot electron emission source region. Compared with a conventional TFET, the vertical-channel double-mechanism conduction nano-wire tunneling transistor introduces a hot electron emission mechanism besides a tunneling mechanism through the structure design of the device, thereby enlarging the conduction current of the device effectively, meanwhile, keeping steep subthreshold slope, and improving the characteristics of the device substantially. The vertical-channel double-mechanism conduction nano-wire tunneling transistor is simple in preparation process, reduces the production cost greatly, and simplifies the process flow.

The invention discloses a two-dimensional semiconductor material negative capacitance field effect transistor and a preparation method thereof; a two-dimensional alloy semiconductor material HfZrSe2 is adopted as a channel material, and the surface of the channel material is oxidized in air to generate HfZrO2, and then annealing is carried out to obtain an HfZrO2 dielectric layer with a ferroelectric property; a high-k gate dielectric layer is deposited on the dielectric layer, and a gate dielectric with a mixed structure is formed. By means of the device structure, high gate dielectric and channel two-dimensional semiconductor material interfaces can be obtained, the deterioration of the interface state on the sub-threshold characteristic is reduced, and the super-steep sub-threshold slope is easily obtained; meanwhile, the high-k gate dielectric on the upper layer can protect the HfZrO2 dielectric of the ferroelectric characteristics below, so that the dielectric is isolated from theair, and the stability of the device is greatly improved. The device is simple in preparation process and large-scale production can be realized.