Dual bar and dual stress channel-changing full consumption SOI MOSFETs part structure

Abstract

The device structure of a double-gate double-strained channel fully depleted SOI MOSFETs disclosed by the present invention includes Si3N4 sidewalls on both sides of the top gate, an active region on one side of the Si3N4 sidewalls, and a drain on the other side of the Si3N4 sidewalls. STI shallow trench isolation regions are set outside the source and drain regions. There is a top gate oxide layer under the top gate and Si3N4 sidewalls. There is a layer of strained Si layer under the top gate oxide layer. There is a strained Si layer under the strained Si layer. A layer of strained SiGe layer, under the strained SiGe layer, there is a layer of bottom gate oxide layer, under the bottom gate oxide layer, there is a bottom gate, on both sides of the bottom gate, there are Si3N4 sidewalls, and the bottom gate is placed in the buried oxide layer. Below the layer is the silicon substrate layer. In the present invention, regardless of the single-gate or double-gate working mode, the driving current of the device when the strained channel is used is higher than that of the bulk silicon channel device; the double-gate mode has a more ideal sub-threshold slope and stronger drive capability than the single-gate mode , higher transconductance and stronger ability to suppress short channel effects.

Description

technical field [0001] The invention belongs to the technical field of microelectronics and solid electronics, and relates to a basic unit MOSFET of an integrated circuit, in particular to a fully depleted SOI MOSFETs device structure with double gates and double strained channels. Background technique [0002] The development of integrated circuits has entered the Sub-100nm era. As the channel length of devices continues to shrink, the short channel effects (Short Channel Effects) of conventional single-gate MOS devices are becoming more and more serious. drift, the subthreshold slope increases, and the device leakage current increases, which has a serious impact on device performance. In recent years, channel band engineering has become a research hotspot, and it is considered to be one of the effective measures to promote the continuous reduction of device feature size. For NMOS devices, strained Si is introduced as the conduction channel for electrons, and for PMOS devi...

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Problems solved by technology

[0003] The purpose of the present invention is to provide a fully depleted SOI MOSFETs device structure with double gates and double strained channels, so as to solve the problem that the short channel effect of existing single gate bulk silicon channel MOS devices becomes more and more serious as the feature size decreases. Increased subthreshold slope; and process incompatibility due to the application of different strained materials for NMOS and PMOS

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