657results about How to "Suppression of short channel effects" patented technology

A FinFET device and method for fabricating a FinFET device is disclosed. An exemplary method includes forming a fin structure on a semiconductor substrate and forming a gate structure on the fin structure. A capping layer is then formed over the semiconductor substrate, fin structure, and gate structure. The capping layer is patterned to form an opening exposing a second portion of the fin structure. An epitaxial layer is grown in the opening and on the second portion of the fin structure. At least one of a source region and a drain region is provided in the epitaxial layer. The method may continue to remove the capping layer.

The present disclosure discloses a method of forming a semiconductor layer on a substrate. The method includes patterning the semiconductor layer into a fin structure. The method includes forming a gate dielectric layer and a gate electrode layer over the fin structure. The method includes patterning the gate dielectric layer and the gate electrode layer to form a gate structure in a manner so that the gate structure wraps around a portion of the fin structure. The method includes performing a plurality of implantation processes to form source / drain regions in the fin structure. The plurality of implantation processes are carried out in a manner so that a doping profile across the fin structure is non-uniform, and a first region of the portion of the fin structure that is wrapped around by the gate structure has a lower doping concentration level than other regions of the fin structure.

The invention is related to a MOS transistor and its fabrication method to reduce short-channel effects. Existing process has the problem of high complexity and high cost to reduce short-channel effects by using epitaxial technique to produce an elevated source and drain structure. In the invention, the MOS transistor, fabricated on a silicon substrate after an isolation module is finished, includes a gate stack, a gate sidewall spacer, and source and drain areas. The silicon substrate has a groove and the gate stack is formed in the groove. And the process for the MOS transistor includes the following steps: forming the groove; carrying out well implantation, anti-punchthrough implantation and threshold-voltage adjustment implantation; forming the gate stack in the groove which comprising patterning the gate electrode; carrying lightly doped drain implantation and halo implantation; forming the gate sidewall spacer; carrying source and drain implantation to get the source and drain areas; forming a metal silicide layer on the source and drain areas.

In a metal-oxide semiconductor (MOS) transistor with an elevated source / drain structure and in a method of fabricating the MOS transistor with the elevated source / drain structure using a selective epitaxy growth (SEG) process, a source / drain extension junction is formed after an epi-layer is formed, thereby preventing degradation of the source / drain junction region. In addition, the source / drain extension junction is partially overlapped by a lower portion of the gate layer, since two gate spacers are formed and two elevated source / drain layers are formed in accordance with the SEG process. This mitigates the short channel effect and reduces sheet resistance in the source / drain layers and the gate layer.

The present invention relates to a flash memory cell comprising a silicon substrate having an active region comprising a channel region and source- / drain-regions, the active region comprising a projecting portion, which projecting portion at least comprising said channel region; a tunneling dielectric layer formed on the surface of said active region; a floating gate formed on the surface of said tunneling dielectric layer for storing electric charges; an inter-gates coupling dielectric layer formed on the surface of said floating gate, and a control gate formed on the surface of said inter-gates coupling dielectric layer, wherein said floating gate is formed to have a groove-like shape for at least partly encompassing said projecting portion of said active region. This invention further relates to a flash memory device comprising such flash memory cells, as well as a manufacturing method thereof.

An integrated circuit device having vias having good resistance to migration causing the breaking of a wiring line, or an integrated circuit device having a wiring structure that is fined by breaking the limit of lithography technique is provided. The former device comprises a plurality of elements fabricated on a semiconductor substrate, wiring lines for making the elements and the integrated circuit device function, and vias for interconnecting wiring lines in separate layers, the via being formed of one or more cylindrical structures made up of carbon atoms. The latter device comprises a plurality of elements fabricated on a semiconductor substrate and wiring members for making the elements and the integrated circuit device function, at least part of the wiring members being formed of one or more cylindrical structures made up of carbon atoms. The latter device is preferably manufactured by a method comprising using a CVD process for the formation of the cylindrical structures, while applying a direct current electric field so as to grow the cylindrical structures in one direction, or applying an alternating current electric field so as to grow the cylindrical structures in two directions. A semiconductor device using a carbon nanotube and a method of forming a pattern using a carbon nanotube as a mask are also disclosed.