Semiconductor device and method of manufacturing same

Abstract

A semiconductor device and related method of manufacture are disclosed. The semiconductor device comprises a gate electrode formed on a semiconductor substrate, an active region containing spaces formed below the gate electrode, a channel region formed between the gate electrode and the spaces, and source and drain regions formed on opposite sides of the gate electrode within the active region. The spaces are formed by etching a semiconductor layer formed below the gate electrode in the active region.

Description

BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention relates generally to a semiconductor device and a method of manufacturing the same. More particularly, the invention relates to a semiconductor device comprising a metal oxide semiconductor (MOS) transistor and a method of manufacturing the same. [0003] A claim of priority is made to Korean Patent Application No. 10-2004-0049004 filed on Jun. 28, 2004, the disclosure of which is hereby incorporated by reference in its entirety. [0004] 2. Description of the Related Art [0005] Fully depleted silicon-on-insulator (FD-SOI) technology has been widely used to create high speed, low power logic circuits. Using FD-SOI technology reduces parasitic capacitances associated with source, drain, and channel regions of semiconductor circuits, thereby allowing the circuits to operate at higher speeds. In addition, FD-SOI technology reduces the amount of leakage current occurring at source and drain junctions o...

AI Technical Summary

Benefits of technology

[0009] The present invention provides a semiconductor device capable of improving carrier mobility by applying a local stress to a channel region while maintaining advantages of an SOI device, such as the ability to constrain short channel effects and reduce junction resistance.

[0010] In addition, the present invention provides a method of manufacturing a semiconductor device in which a highly integrated semiconductor device having an improved short channel effect and reduced junction capacitance, as well as a device being capable of constraining a substrate floating effect may be implemented at a relatively low cost.

[0013] According to the present invention, the short channel effect is constrained and junction resistance is reduced by forming the spaces in the active region below the gate electrode. Furthermore, it effectively addresses the substrate floating effect which occurs in devices using SOI technology. Furthermore, the invention makes it possible to implement the mechanical stress engineering technique to the channel region to increase carrier mobility.

Problems solved by technology

Unfortunately, however, a substrate floating effect may occur in MOS transistors formed on an SOI substrate where an element in a channel region assumes a floating state electric potential.

Furthermore, where a buried oxide layer (BOX) is formed below a silicon substrate, a self-heating problem often occurs in devices formed on the silicon layer.

As a result, the range of applications where SOI technology can be used is restricted by the kinds of circuits to be formed.

Unfortunately, it is difficult to apply local stress to SOI devices because the silicon layer formed on the buried oxide layer (BOX) is too thin.

In addition, cost poses an obstacle to the manufacture of devices using SOI technology because SOI wafers are extremely expensive.

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