Semiconductor device and method of manufacturing same

a semiconductor and semiconductor technology, applied in the direction of semiconductor devices, electrical devices, transistors, etc., can solve the problems of difficult local stress application to soi devices, limited application range of soi technology, and self-heating problems of devices formed on silicon layers, etc., to achieve effective address the floating effect of substrates, reduce junction resistance, and increase carrier mobility
US20050285193A1Inactive Publication Date: 2005-12-29SAMSUNG ELECTRONICS CO LTD
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Patent Information

Authority / Receiving Office
US · United States
Current Assignee / Owner
SAMSUNG ELECTRONICS CO LTD
Publication Date
2005-12-29
Estimated Expiration
Not applicable · inactive patent

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Abstract

A semiconductor device and related method of manufacture are disclosed. The semiconductor device comprises a gate electrode formed on a semiconductor substrate, an active region containing spaces formed below the gate electrode, a channel region formed between the gate electrode and the spaces, and source and drain regions formed on opposite sides of the gate electrode within the active region. The spaces are formed by etching a semiconductor layer formed below the gate electrode in the active region.
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Description

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates generally to a semiconductor device and a method of manufacturing the same. More particularly, the invention relates to a semiconductor device comprising a metal oxide semiconductor (MOS) transistor and a method of manufacturing the same.

[0003] A claim of priority is made to Korean Patent Application No. 10-2004-0049004 filed on Jun. 28, 2004, the disclosure of which is hereby incorporated by reference in its entirety.

[0004] 2. Description of the Related Art

[0005] Fully depleted silicon-on-insulator (FD-SOI) technology has been widely used to create high speed, low power logic circuits. Using FD-SOI technology reduces parasitic capacitances associated with source, drain, and channel regions of semiconductor circuits, thereby allowing the circuits to operate at higher speeds. In addition, FD-SOI technology reduces the amount of leakage current occurring at source and drain junctions o...

Claims

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