2 results about "Stress engineering" patented technology

Devices, integrated circuit transistor structures, systems, and techniques are described herein related to gate all around field effect transistor circuits having an n-type transistor integrated with a p-type transistor such that each has stress engineering in the channel material thereof. The nanowires of the p-type transistor are released and surrounded by a sacrificial flowable oxide structure during source and drain material growth to apply compressive stress to the channel material. The n-type transistor source and drain are grown in the presence of a sacrificial lattice matched material to apply tensile stress to the channel material, and the nanowires are subsequently released. After removal of the sacrificial flowable oxide structure, gate structures are coupled to the n-type and p-type transistors.

This document describes devices, transistor structures, systems, and techniques for integrated circuits relating to gate-all-around field-effect transistor circuits, in which an n-type transistor is integrated with a p-type transistor such that each exhibits a voltage technique within its channel material. The nanowires of the p-type transistor are released during the growth of the source and drain material and surrounded by a flowable sacrificial oxide structure to exert compressive stresses on the channel material. The source and drain of the n-type transistor are grown in the presence of a grid-matched sacrificial material to place the channel material under tensile stress, and the nanowires are subsequently released. After removal of the flowable sacrificial oxide structure, gate structures are coupled to the n- and p-type transistors.