6 results about "Stress engineering" patented technology

The invention discloses a pressure stress passivation method, which is applied to a thin barrier gallium nitride millimeter wave device, and is characterized in that a laminated silicon nitride passivation layer with pressure stress is formed on the surface of the device through the synergistic effect of interface passivation and stress engineering, so that device passivation is realized; wherein the laminated silicon nitride passivation layer comprises an interface function layer positioned on the bottom layer and a stress modulation layer positioned on the interface function layer; the method comprises the following steps of: depositing a first layer of silicon nitride film on a barrier layer of the gallium nitride millimeter wave device under the conditions of a high-frequency source and rich silicon to form an interface function layer; and depositing a second layer of silicon nitride film on the interface function layer, and carrying out stress regulation and control in the deposition process to form a stress modulation layer with compression stress. According to the method, current collapse can be effectively suppressed, meanwhile, the breakdown voltage is remarkably improved, and finally the thin-barrier gallium nitride millimeter wave device is enabled, so that the thin-barrier gallium nitride millimeter wave device has excellent performance of high power output and high stability in a high-frequency working mode.

Devices, integrated circuit transistor structures, systems, and techniques are described herein related to gate all around field effect transistor circuits having an n-type transistor integrated with a p-type transistor such that each has stress engineering in the channel material thereof. The nanowires of the p-type transistor are released and surrounded by a sacrificial flowable oxide structure during source and drain material growth to apply compressive stress to the channel material. The n-type transistor source and drain are grown in the presence of a sacrificial lattice matched material to apply tensile stress to the channel material, and the nanowires are subsequently released. After removal of the sacrificial flowable oxide structure, gate structures are coupled to the n-type and p-type transistors.

The application belongs to the field of advanced material technology, and relates to a method for preparing large-size room-temperature ferromagnetic graphene based on stress engineering, ferromagnetic graphene and application thereof. The method is as follows: 3 or more layers of copper-based graphene are folded densely by a mechanical method, and then at least 10 cycles of rapid cooling and heating are performed, and the ferromagnetic graphene is obtained; the process of rapid cooling and heating is as follows: the copper-based graphene after being folded densely is placed in a cold trap environment of 70-120K for cooling, and then is rapidly placed in an environment of room temperature and above for heating. Through the pretreatment method of mechanical folding and continuous rapid cooling and heating, strong and tough ferromagnetic property is observed in large-size graphene (centimeter scale), and the Curie temperature is 100K to room temperature and above. The ferromagnetic graphene in the application is applied to the fields of flexible electronic devices and wearable artificial intelligence.

A method for preparing a strain channel FinFET, which method belongs to the technical field of integrated circuit manufacturing. After the manufacturing of a fin line is completed, amorphous silicon is generated by means of an amorphization implantation method; after being covered by a strain dielectric layer and annealed at a high temperature, the amorphous silicon is recrystallized, and in this case, tensile stress / compressive stress required by an N / PMOS can be formed between the crystalline silicon and a strain dielectric; and a strain dielectric material is then selectively removed to implement the preparation of a strain channel FinFET. In the method, the lattice mismatch between the strain dielectric material and the crystalline silicon is used to generate tensile stress or compressive stress required by a FinFET device. A single strain material is used to realize N / PMOS channel strain, so that the flow of channel stress engineering is simplified, the process complexity is reduced, and the method has the potential to be applied to technology nodes of 14 nm and above.

This document describes devices, transistor structures, systems, and techniques for integrated circuits relating to gate-all-around field-effect transistor circuits, in which an n-type transistor is integrated with a p-type transistor such that each exhibits a voltage technique within its channel material. The nanowires of the p-type transistor are released during the growth of the source and drain material and surrounded by a flowable sacrificial oxide structure to exert compressive stresses on the channel material. The source and drain of the n-type transistor are grown in the presence of a grid-matched sacrificial material to place the channel material under tensile stress, and the nanowires are subsequently released. After removal of the flowable sacrificial oxide structure, gate structures are coupled to the n- and p-type transistors.

The invention discloses a surface gain slab laser medium preparation method based on reverse stress engineering, and relates to the technical field of solid laser manufacturing. Through a reverse strategy of doping a seed crystal long pure layer, protective pressure stress is introduced into a growth layer, crack initiation is successfully inhibited, and a composite crystal blank is obtained; cutting the blank along the center of the seed crystal layer to obtain two semi-finished products; after the pure YAG growth face of the semi-finished product is polished, the two pure YAG faces are in butt joint through the homogeneous thermal diffusion bonding technology, and the Yb: YAG / YAG / Yb: YAG sandwich structure batten is manufactured. According to the invention, crystal growth cracks are effectively inhibited, reliable interface bonding is realized, and color center and impure phase defects are eliminated.