43results about How to "Increase junction depth" patented technology

A semiconductor device is formed by performing an amorphizing ion implantation to implant dopants of a first conductivity type into a semiconductor body. The first ion implantation causes a defect area (e.g., end-of-range defects) within the semiconductor body at a depth. A non-amorphizing implantation implants dopants of the same conductivity type into the semiconductor body. This ion implantation step implants dopants throughout the defect area. The dopants can then be activated by heating the semiconductor body for less than 10 ms, e.g., using a flash anneal or a laser anneal.

A SiGe HBT is disclosed. A collector region consists of a first ion implantation region in an active area as well as second and third ion implantation regions respectively at bottom of field oxide regions. Each third ion implantation region has a width smaller than that of the field oxide region, has one side connected to first ion implantation region and has second side connected to a pseudo buried layer; each second ion implantation region located at bottom of the third ion implantation region and pseudo buried layer is connected to them and has a width equal to that of the field oxide region. Third ion implantation region has a higher doping concentration and a smaller junction depth than those of first and second ion implantation regions. Deep hole contacts are formed on top of pseudo buried layers in field oxide regions to pick up collector region.

The invention relates to diffusion technology for manufacturing solar cells, in particular to phosphoric diffusion technology for metallurgical-grade polysilicon solar cells. The technology comprises the following steps: firstly, performing high temperature grain boundary gettering, wherein high temperature is used to make impurity atoms released at the prior settling position and simultaneously diffused and move to the position of a grain boundary defect to settle to form a clean area near the grain boundary; secondly, performing medium-low temperature phosphoric deposition, wherein diffusion deposition of fresh phosphorus is performed for a short time at a medium low diffusion temperature to finish surface low concentration phosphorus deposition to prepare for long time high temperaturedrive-in in a next step; thirdly, performing diffusion passivation of high temperature deep grain boundary, wherein high temperature long time phosphoric source drive-in is performed to form deep PNjunction at the position of the grain boundary so as to make phosphor generate phosphoric gettering and passivation of phosphoric drift field at the position of the grain boundary; and finally, performing the diffusion again for adjusting to a needed sheet resistance value. The technology greatly reduces the composite of minority carrier originally happening in the position of the grain boundary by utilizing the properties of the diffusion of impurities in the polycrystalline silicon; and after the process is finished, the minority carrier lifetime of a silicon chip is improved compared with that of a silicon clip produced by a normal process, which has an active effect on the final performance of the cells.

The invention relates to a three-step variable-temperature diffusion process for a silicon cell, which is realized by the following procedures: placing a silicon chip after etching into a boat, then rising the temperature to be 700-810 DEG C, and introducing large nitrogen, small nitrogen and oxygen to conduct low-temperature pre-deposition diffusion; subsequently rising the temperature to be 810-830 DEG C, and introducing large nitrogen to conduct knot thrusting; and then introducing large nitrogen, small nitrogen and oxygen, and rising the furnace temperature to be 830-870 DEG C to conduct secondary deposition diffusion. A multi-level PN knot structure formed after diffusion can ensure good ohmic contact with a metal gate wire on the one hand, and can have good blue response on the other hand; in addition, a PN knot formed by the method has great knot depth, and the possibility that the PN knot is burnt through, subjected to leakage of electricity and composited can be reduced.

The invention discloses a switching LDMOS device. According to the invention, an LDD region of the switching LDMOS device and a first bulk-doped region of a second conduction type are arranged in a first trap in a semiconductor substrate; a first heavily-doped region serving as a source region is arranged in the LDD region, and a second heavily-doped region serving as a drain region is arranged inthe first bulk-doped region; in a gate structure, a channel of the switching LDMOS device is formed on the surface layer of the part, located between the LDD region and the bulk-doped region, of thesemiconductor substrate, and when a voltage applied to a gate exceeds the threshold voltage of the LDMOS device, the channel is inverted, so the source region and the drain region are conducted; and one side, far away from the gate structure, of each of the LDD region and the bulk-doped region is provided with field oxygen or STI, and one side of the field oxygen or STI is connected with the firstheavily-doped region in the LDD or the second heavily-doped region in the first bulk-doped region. With the bulk-doped region having higher ion implantation energy and ion implantation dosage, the purposes of improving the breakdown voltage (BV) of the device and reducing the size of the device are achieved.

The invention discloses a solar cell emitter doping distribution method. The solar cell emitter doping distribution method includes the steps of pre-oxidation, two times of source communication diffusion and two times of junction pushing for cooling and boat discharging. solar cell emitter doping distribution is realized through multiple times of source communication and multiple times of junction pushing, the time, temperature and source communication amount of multiple times of diffusion and the time and temperature of multiple times of junction pushing are adjusted, a solar cell emitter is made to have a lower surface doping concentration, and therefore the influences of a 'dead layer' are obviously weakened, and the short wave response of a solar cell is improved. The process of multiple times of source communication and multiple times of junction pushing further improves the doping concentration in a silicon wafer body, the silicon wafer surface doping concentration and the doping concentration inside the silicon wafer body are uniform, diffusion uniformity is good, and therefore the diffusion sheet resistance uniformity is improved. The process of multiple times of junction pushing improves the junction depth and increases blue light response of the solar cell, and finally the purpose of improving the conversion efficiency of the crystalline silicon solar cell is realized.

The invention provides a composite high voltage semiconductor device; a layout comprises a straight edge portion arranged in a straight line; the straight edge portion comprises enhanced devices including the following: a semiconductor substrate; a first high voltage trap and a second high voltage trap arranged in parallel in the semiconductor substrate; a first field oxide layer arranged in the first high voltage trap; a first drain electrode ohmic contact zone arranged in the first high voltage trap of a first side of the first field oxide layer; a first source electrode ohmic contact zone arranged in the second high voltage trap; a first grid electrode at least covering the semiconductor substrate between the first source electrode ohmic contact zone and a second side of the first field oxide layer, wherein the first side of the first field oxide layer is far away from the second high voltage trap, and the second side of the first field oxide layer is close to the second high voltage trap. The doped concentration of the second high voltage trap is smaller than that of the first high voltage trap. The reliability of the device can be improved.