43results about How to "Increase junction depth" patented technology

A process is disclosed which incorporates implantation of a carbon cluster into a substrate to improve the characteristics of transistor junctions when the substrates are doped with Boron and Phosphorous in the manufacturing of PMOS transistor structures in integrated circuits. There are two processes which result from this novel approach: (1) diffusion control for USJ formation; and (2) high dose carbon implantation for stress engineering. Diffusion control for USJ formation is demonstrated in conjunction with a boron or shallow boron cluster implant of the source/drain structures in PMOS. More particularly, first, a cluster carbon ion, such as C₁₆H_x⁺, is implanted into the source/drain region at approximately the same dose as the subsequent boron implant; followed by a shallow boron, boron cluster, phosphorous or phosphorous cluster ion implant to form the source/drain extensions, preferably using a borohydride cluster, such as B₁₈H_x⁺ or B₁₀H_x⁺. Upon subsequent annealing and activation, the boron diffusion is reduced, due to the gettering of interstitial defects by the carbon atoms.

A semiconductor device is formed by performing an amorphizing ion implantation to implant dopants of a first conductivity type into a semiconductor body. The first ion implantation causes a defect area (e.g., end-of-range defects) within the semiconductor body at a depth. A non-amorphizing implantation implants dopants of the same conductivity type into the semiconductor body. This ion implantation step implants dopants throughout the defect area. The dopants can then be activated by heating the semiconductor body for less than 10 ms, e.g., using a flash anneal or a laser anneal.

The present invention relates to a diffusion technique of a crystal-silicon efficient high-sheet-resistance battery piece. The diffusion technique comprises the steps of furnace entering, low-temperature oxidation, low temperature gas reaction deposition, low temperature dopant redistribution, high temperature gas reaction deposition, cooling dopant redistribution, low temperature gas reaction deposition, low temperature dopant redistribution and discharge. With adoption of the diffusion technique provided by the present invention, photoelectric conversion efficiency of the battery pieces can be raised, the production time is shortened, and the production efficiency is raised.

The invention discloses a polycrystalline black silicon wafer diffusion method through MCCE etching, which is applicable to a black silicon diffusion process prepared by adopting a metal catalytic chemical etching method. A process of first deposition-first propulsion-second deposition-second propulsion is adopted. The oxygen flow rate in the first deposition process is larger than the nitrogen flow rate with a phosphorus source; the first propulsion is anaerobic propulsion, and the pure nitrogen flow rate in the first propulsion process is larger than that in the first deposition process; thenitrogen flow rate with a phosphorus source in the second deposition process is larger than that in the first deposition process; the pure nitrogen flow rate in the second deposition process is smaller than that in the first deposition process; the temperature of the second deposition process is larger than that of the first deposition process; the second propulsion is oxygen-enriched propulsion;the first propulsion time is smaller than the first deposition time; and the second propulsion time is larger than the second deposition time. Photocarrier recombination can be effectively reduced, the silicon wafer diffusion uniformity is enhanced, and the black silicon cell efficiency is enhanced.

The invention relates to a formation method for a side wall, which comprises: providing a semiconductor basement, forming a grid on the semiconductor basement; using the grid as a mask to form a ultra-shallow junction on the semiconductor basement and using disilane as reaction gas to form an insulation layer on the semiconductor basement with the formed ultra-shallow junction; etching the insulation layer to form the side wall surrounding the grid. The formation method for the side wall can reduce the diffusion of doping material in the ultra-shallow junction, thereby reducing the increasing of junction depth.

The invention relates to the field of solar cell production, and discloses a phosphorus doping control method for an emitter of a crystalline silicon solar cell. The method is carried out according tothe following steps of (1) first low-temperature oxidation; (2) first deposition; (3) second low-temperature oxidation; (4) second deposition and first propulsion; and (5) third deposition and secondpropulsion. According to the phosphorus doping control method, the peak concentration is improved through low-temperature oxidation, deposition and low-temperature oxidation, meanwhile, lattice dislocation is not caused, and then the surface of the cell is passivated through double deposition and propulsion, thereby obtaining better photoelectric conversion efficiency.

The invention belongs to the field of power semiconductor devices, and particularly relates to a low-power-consumption high-performance super-junction JBS diode and a manufacturing method thereof. Thelow-power-consumption high-performance super-junction JBS diode is manufactured by using a traditional silicon-based process technology, so that the manufacturing cost is low; a P heavily doped cylindrical region and an N cylindrical drift region which have the characteristics of large area, high concentration and large junction depth are adopted, so that the forward conduction resistance is reduced; a super junction is formed, and good reverse blocking characteristics are achieved by optimizing electric field distribution; by optimizing parameters of the super junction, higher blocking withstand voltage can be realized, and the on-state and off-state power consumption of the device is reduced; and optimal two-dimensional electric field distribution is obtained by optimizing the doping concentration and width of the P column region and the N column region, unification of high blocking voltage and low on-resistance and unification of high blocking voltage and rapid switching are achieved, compromise between forward on-state voltage drop and reverse blocking characteristics and compromise between reverse recovery characteristics and reverse blocking voltage are optimized, and the limit of a traditional silicon material is broken through.

The invention provides a process for improving the static electricity of a 100V Schottky diode. 4.5E+15-6.5E+15 high dose ion implantation is adopted, so that the impurity concentration of a PN junction is increased, besides, a high annealing temperature is adopted, so that the junction depth and the homogeneity of devices are improved. The Schottky diode is a device with a surface shallow junction, the larger the doping concentration is, the deeper the junction depth is, and the pressure resistance of the device is stronger. The junction depth of the 100V Schottky diode, prepared by the process disclosed by the invention, is 1.8 mum to 2.2 mum, and the static electricity of the Schottky diode is 18KV. The extension thickness is thick, the poured doping concentration is high, the annealing temperature is high, the junction is deep, and the homogeneity is good. The static electricity is greatly improved, and the stability of static electricity batches is consistent. The static electricity is high, so that in a use process of the device, the probability of static shock is low.

The invention provides a transient voltage suppressor and a manufacturing method thereof, the transient voltage suppressor comprising: a substrate of a first conductivity type; a first epitaxial layerof a first conductivity type grown on an upper surface of the substrate; a buried layer of a second conductivity type extending downward from an upper surface of the first epitaxial layer to the first epitaxial layer; a second epitaxial layer of a second conductivity type grown on an upper surface of the first epitaxial layer and the buried layer; extending downward from an upper surface of the second epitaxial layer to a first doped region of a first conductivity type within the second epitaxial layer; a second doped region of the second conductivity type and a third doped region of the second conductivity type; a dielectric layer located on an upper surface of the second epitaxial layer; a first electrode electrically connected to the second epitaxial layer; and a second electrode electrically connected to the lower surface of the substrate. The transient voltage suppressor has the characteristics of low capacitance, high integration level and simple manufacturing process.

The invention relates to the field of solar cell production. The invention discloses a method for preparing a solar cell diffusion deep junction. The method comprises the following steps of: 1, preparing a SiO2 layer; 2, preparing a constant impurity phosphorus source on the surface of the silicon wafer through twice deposition; 3, pushing phosphorus atoms into the silicon wafer to form a PN junction; 4, carrying out supplementary diffusion; 5, preparing a rear oxide layer; and 6, depositing an impurity phosphorus source on the surface of the silicon wafer again. The antireflection suede is prepared before the first step. The method has the beneficial effects that under the condition of not changing the overall sheet resistance and the process time, the PN junction depth and the junction region phosphorus concentration difference are effectively increased, and the Uoc and the FF of the battery piece are improved, so that the battery conversion efficiency is improved.

The invention provides a 40 V Schottky diode manufacturing process capable of reducing the secondary breakdown ratio. The Schottky diode manufacturing process includes the main step of setting epitaxy parameters of a silicon wafer, wherein the epitaxy thickness is 5.2-5.4 micrometers, the resistivity is 0.84-0.92 omega. cm, the initial oxidation parameter is 5000-7000 a, the implantation dose is 2E-3E+15, and the annealing temperature is 1070-1080 DEG C. According to the 40 V Schottky diode manufacturing process, the high ion implantation dose of 2E-3E+15 is adopted, so that the impurity concentration of PN junctions is increased; meanwhile, the high annealing temperature is adopted, so that the junction depth of a device is increased, and the uniformity of the device is improved; the larger the dosage concentration and the junction depth are, the stronger the voltage withstanding capability of the device will be. The Schottky diode is a surface shallow junction device, the secondary breakdown ratio is reduced to 5% or below, a Schottky breakdown curve is good, and the device has high reliability in the use process.

The invention discloses a Si-GeSn-Si heterogeneous GeSn-based solid-state plasma PiN diode and a preparation method thereof, and the preparation method comprises the steps: selecting a GeOI substrate, and carrying out the doping in the GeOI substrate, so as to form a top layer GeSn region; arranging a deep groove isolating region in the GeSn region on the top layer of the substrate; etching the GeSn region to form a P-type groove and an N-type groove, wherein the depths of the P-type groove and the N-type groove are smaller than the thickness of the top-layer GeSn region; forming a P-type active region and an N-type active region in the P-type groove and the N-type groove by adopting ion implantation; and forming a GeSn alloy lead on the substrate. According to the invention, the top GeSn region is introduced to dynamically control the content of the Sn component in the top Ge, so that the forbidden band width of the intrinsic region is reduced. Due to the existence of the Si-GeSn-Si heterostructure, the forbidden band width difference can reach 0.7 eV, the carrier injection ratio is improved, and the solid-state plasma concentration and distribution uniformity are improved. The GeSn alloy lead is formed by adopting the RPCVD technology, a metal electrode in a traditional diode is replaced, and the integration level and the stealth performance of an antenna system are greatly improved.