145 results about "Junction area" patented technology

The invention provides a manufacturing method of a sigma trench, which comprises the following steps: providing a substrate, forming a gate oxide layer and a gate structure on the substrate, the gate structure comprising a gate, a first mask layer and a second mask layer which are sequentially formed on the gate oxide layer; etching for the first time by taking the second mask layer as a mask until the second mask layer is removed, forming a first groove in the substrate on two sides of the gate structure, and gathering polymers generated by etching the second mask layer in the etching process on the gate oxide layer on the side wall of the first groove and a junction area of the gate oxide layer, the gate and the substrate as an etching protection layer; and performing second etching by taking the first mask layer as a mask, protecting the substrate covered by the etching protection layer from lateral etching by the etching protection layer, and forming a sigma-like groove in the first groove. According to the method, the etching protection layer is formed on the side wall of the first groove through the polymer generated by the second mask layer in the first etching process, the area is prevented from being excessively etched, serious lateral pushing of the area is avoided, and therefore the shape of the groove can be adjusted and controlled more easily.

The present application relates to a kind of low scattering carriers for RCS test, including carrier body, carrier body includes first surface and second surface, first surface and second surface are connected to form hollow cavity, hollow cavity is used to accommodate cylindrical target component;One end of hollow cavity is tip, the other end is open end, open end is circular, cylindrical target component is installed in hollow cavity through open end;Horizontal plane is formed at the junction of first surface and second surface, the height of first surface beyond horizontal plane is less than the height of second surface beyond horizontal plane, the radius of curvature of first surface gradually increases from tip to open end direction, the radius of curvature of second surface increases first and then decreases from tip to open end direction.The low scattering carrier in the present application can simulate the installation state of cylindrical target component, realize the accurate evaluation of the RCS of cylindrical target component.

According to the coil component and the electric valve provided by the utility model, the limiting structure is arranged in the coil component, and at least one part of the limiting structure is arranged at the junction of the insulating layer and the free section, so that one side, at least close to the insulating layer, of the free section can be limited and supported through the limiting structure. Through the scheme, the movement range of the part, close to the insulating layer, of the free section of the wire (namely the junction of the free section and the insulating layer) is limited, namely the movement range of the part, exposed out of the insulating layer, of the wire relative to the part, fixed in the insulating layer, of the wire is limited at least from one direction; in this way, large stress concentration caused by large-angle bending of the position where the wire penetrates out of the insulating layer is prevented at least from one direction, so that the risk that the wire is bent to be damaged or broken at the position is reduced or avoided, and the product reliability is improved.

A foldable display device includes a reflective display panel, a light guide layer, and at least one light source. The light guide layer is located on the reflective display panel and includes a non-bending area, a bending area, and a junction area. The bending area is located in the middle of the light guide layer. The junction area is located between the bending area and the non-bending area. The light source is located on the reflective display panel and faces the sidewall of the non-bending area, and is configured to emit light to the light guide layer. Because the thickness of the non-bending area is greater than the thickness of the bending area, sufficient light input to the light guide layer is ensured. The smaller thickness of the bending area reduces the material rigidity of the bending area, allowing the foldable display device to fold at the bending area. The thickness of the junction area is between the non-bending area and the bending area, thus enabling total internal reflection of light from the light guide layer to the bending area. This ensures sufficient light input without requiring an additional light source and also improves the power efficiency of the foldable display device.

A method for forming a semiconductor structure, the method comprising: providing a substrate, the substrate having a source region and a drain region formed therein, a drift region formed in the substrate between the source region and the drain region, the drift region being in contact with the drain region, a gate structure formed on a top of the substrate at an interface of the source region and the drift region; forming a first dielectric layer on the top of the substrate at the source region, the drain region and the drift region, the first dielectric layer also covering sidewalls of the gate structure; forming a recess in a middle region of a top surface of the first dielectric layer at the drift region; after forming the recess, forming a first trench in a portion of the first dielectric layer at the drift region, the first trench being in communication with the recess, forming a second trench through the first dielectric layer at the source region and the drain region; forming a field plate contact hole in the first trench, the field plate contact hole covering the first dielectric layer at a bottom of the first trench, forming an interconnection via structure in the second trench, the interconnection via structure being in electrical connection with the source region and the drain region. The thickness uniformity of the first dielectric layer below the bottom of the first trench is improved.

Embodiments of the present application provide a pin grid array structure, comprising: a package lead frame; and a moisture barrier layer disposed on an upper surface of the package lead frame and covering an intersection of a package compound and the lead frame of the package lead frame. The purpose of the present application is to provide a pin grid array structure and a semiconductor structure to improve yield.

This invention provides a bass reflex port that can effectively suppress port noise, and a speaker system equipped therewith. [Solution] The inner circumferential surface 50 of the bass reflex port 40 comprises a straight pipe section 51 having a constant diameter d0 along the axial direction, and an enlarged diameter section 52 whose diameter gradually increases as it moves away from the straight pipe section 51 along the axial direction. The enlarged diameter section 52 has a first enlarged diameter section 53 and a second enlarged diameter section 54. The axial length L1 of the first enlarged diameter section 53 is 15% or more of the diameter d0 of the straight pipe section 51, and the enlargement ratio d1 / d0 in the first enlarged diameter section 53 is 125% or less. An angle section 55 with a locally smaller radius of curvature is formed at the boundary between the first enlarged diameter section 53 and the second enlarged diameter section 54.

A tiled display device with improved staining at the junction and a sub-display panel employed therein are disclosed. The tiled display device comprises: a first sub-display panel having a plurality of unit pixels formed therein; and a second sub-display panel disposed adjacent to the first sub-display panel and having a plurality of unit pixels formed therein, wherein each of the unit pixels comprises a plurality of sub-pixels having a display element that emits color light and a pixel circuit that drives the display element, and wherein the arrangement order of sub-pixels within the unit pixels corresponding to the current row and the arrangement order of sub-pixels within the unit pixels corresponding to the previous row or the next row are different from each other. Accordingly, by configuring the arrangement order of sub-pixels within the unit pixels corresponding to the current row and the arrangement order of sub-pixels within the unit pixels corresponding to the previous row or the next row differently from each other, the visibility of staining caused by the sub-pixel arrangement near the junction area can be improved.

The utility model discloses a silicon carbide MOSFET junction terminal structure, and belongs to the technical field of semiconductor devices. Comprising a first passivation layer, an N-drift region, an N + substrate, a cathode metal electrode layer, a Pwell cellular transition region, a Pplus main junction region, a Pplus field limiting ring region, a Pwell main junction region, a Pwell field limiting ring region, a JTE main junction region, a JTE field limiting ring region, an anode metal electrode layer and a second passivation layer. And the Pwell cell transition region, the Pplus main junction region, the Pplus field limiting ring region, the Pwell main junction region, the Pwell field limiting ring region, the JTE main junction region and the JTE field limiting ring region are sequentially manufactured on the N-drift region from left to right. And the junction area of every two junction termination extension structures is a field limiting ring. The problems that a field limiting ring structure of an existing silicon carbide MOSFET is large in occupied area, and a junction terminal expansion structure is complex in process are solved. The method is widely applied to the silicon carbide MOSFET design and manufacturing technology.

This invention discloses a stepped P-well high-voltage shielded gate MOSFET, relating to the field of power electronics technology. The stepped P-well high-voltage shielded gate MOSFET includes a device housing with a voltage-resistant shielding component installed inside. The voltage-resistant shielding component comprises an N-type substrate, an N-type drift region, and a stepped P-well region. The stepped P-well region extends in a multi-step manner along the source-to-drain direction, with the doping concentration decreasing gradually along the source-drain direction. A trench is provided at the boundary between the P-well region and the N-type drift region, and a shielding gate is embedded in the trench. A gate dielectric layer is provided on the surface of each key structure. The source is electrically connected to the stepped P-well region and the shielding gate and is diagonally positioned opposite the drain. This invention optimizes the electric field distribution and weakens the electric field concentration through the synergistic effect of the stepped P-well gradient doping and the shielding gate, significantly improving the device's voltage withstand performance while reducing conduction and switching losses. It is compatible with existing fabrication processes and can be widely applied in high-power scenarios such as new energy and power electronics.

The application discloses a kind of slice switching section structures, it is related to wind power facilities field.Slicing switching section structure includes angle column, inner steel cylinder and box type combined beam;Each angle column is fixed with inner steel cylinder by a box type combined beam;Slicing switching section structure is fixed by at least two rotationally symmetrical splicing structures by connecting mechanism;Switching section structure also includes bottom reinforcing component, top reinforcing component and vertical reinforcing component.The application solves the problem of transportation size limit by splicing design, meets the requirements of transportation limit;Bottom reinforcing component strengthens the shear capacity of the junction of angle column and inner steel cylinder, top reinforcing component improves load transfer path, vertical reinforcing component suppresses lateral deformation, reduces stress concentration phenomenon together, greatly optimizes the stress distribution of the junction area of angle column, inner steel cylinder and box type combined beam;Under the premise of guaranteeing structure safety, avoid the problem of excessive use of material for traditional reinforcement structure, improve material utilization efficiency, reduce construction cost.

The invention discloses a device and method for synchronously eliminating depressed layer lines in the metal additive manufacturing process. The device comprises a rotatable support, an adjustable clamp and a swing laser head. In the metal wire feeding additive manufacturing process, the rotatable support is connected with a machining head of additive manufacturing equipment, the rotation angle of the rotatable support is adjusted in real time according to an additive manufacturing path, and the focus of the laser head is aligned with the layer grain depression slightly falling behind a forming molten pool by adjusting the adjustable clamp so that the layer grain depression can be eliminated. And melting the metal material near the junction of the current layer and the previous layer, and filling the layer grain depressions after the material is molten and solidified, so as to realize synchronous elimination or reduction of the layer grain depressions in the material adding process. According to the method, on the premise that the manufacturing time and the material cost are not obviously increased, the part surface quality, the forming precision and the material utilization rate are obviously improved, the post-treatment complexity is reduced, meanwhile, the process layer high selection space is expanded, and the process flexibility is improved.

This light-condensing structure (12) for optical elements is formed on a surface of a semiconductor substrate (11) of an optical element (10), said light-condensing structure comprising: a spherical lens (121) that is convex in a direction perpendicular to the surface of the semiconductor substrate; a base part (122) that is disposed in the periphery of the lens (121); and a recess (124) that is formed in a side wall of the base part in the vicinity of the border between the side wall of the base part and the surface of the semiconductor substrate.　Thus, the present invention can provide a light-condensing structure for optical elements that has a lens with excellent light condensing efficiency.

The invention discloses a stamping connection terminal and a preparation method thereof, and relates to the technical field of electric appliance connection terminals. The stamping connection terminal is integrally formed by continuously stamping a high-precision phosphor copper strip, and comprises a contact end and a connection end. The contact end comprises a pair of elastic contact arms which are oppositely arranged, the free end of each elastic contact arm is bent to form a guide flange with a guide surface, and a plurality of hemispherical contact salient points are arranged at the junction of the guide surface and the elastic contact arms. The connecting end is provided with a clamping structure, and the clamping structure is provided with at least two rows of antiskid teeth which are distributed in a staggered mode. And a transition region between the contact end and the connection end. The surface of the contact end is provided with a gold-plated layer, and the surfaces of the connecting end and the transition area are provided with a mist tin-plated layer. The purity of the high-precision phosphorus copper strip is larger than or equal to 99.95%, the content of phosphorus is 0.03-0.08 wt%, the tensile strength is 350-400 MPa, and the ductility is larger than or equal to 15%. According to the invention, the problems that the connection is not tight enough, the conductive performance is not stable and the preparation cost is high in the actual use process of the current connection terminal can be effectively improved.

The invention provides a grating-integrated semiconductor light-emitting structure and a preparation method thereof, the grating-integrated semiconductor light-emitting structure comprises a semiconductor substrate layer, a gain structure and a grating waveguide dielectric structure, and the junction of the grating waveguide dielectric structure and the gain structure is provided with an anti-reflection structure; the gain structure is located on one side of a part of the semiconductor substrate layer in the fast axis direction, and the gain structure comprises a first semiconductor limiting layer, a first semiconductor waveguide layer, an active layer, a second semiconductor waveguide layer and a second semiconductor limiting layer which are sequentially arranged in the fast axis direction; the grating waveguide dielectric structure is located on one side of a part of the semiconductor substrate layer in the fast axis direction and located on one side of the gain structure in the cavity length direction, and a grating is integrated in the grating waveguide dielectric structure. And the wavelength temperature drift coefficient of the semiconductor light-emitting structure of the integrated grating is reduced.

The application provides a semiconductor structure manufacturing method, which comprises the following steps: providing a substrate; forming a first electrode layer on one side of the substrate; forming a dielectric layer on the surface of the first electrode layer far from the substrate; forming a second electrode layer on the surface of the dielectric layer far from the first electrode layer; performing chlorine removal pretreatment on the second electrode layer; and forming a third electrode layer on the surface of the second electrode layer far from the dielectric layer. The method solves the problem that chlorine ions at the junction of a silicon germanium layer in the prior art affect the interface reliability.

The application relates to a semiconductor structure and a preparation method thereof. The preparation method of the semiconductor structure comprises the following steps: a shallow trench isolation structure is formed in a substrate, the shallow trench isolation structure extends upward from the substrate and has a first protruding part protruding from the substrate; a local oxidation material layer is located at the junction of an active region and the shallow trench isolation structure and has a second protruding part protruding from the upper surface of the active region; a sacrificial oxide layer is located on the upper surface of the active region and is in contact with the local oxidation material layer; the sacrificial oxide layer and the second protruding part are removed to form a local oxidation layer and form a groove on the side wall of the first protruding part towards the local oxidation layer; a gate oxide layer is located on the upper surface of the active region and is in contact with the local oxidation layer; and a gate electrode is located at least on the upper surface of the gate oxide layer and fills the groove. The preparation method of the semiconductor structure optimizes the semiconductor structure, improves the reliability of the semiconductor device, and reduces the failure rate of the semiconductor device.

The invention discloses a Ga2O3 diode adopting an inclined field plate and a NiO heterojunction and a preparation method of the Ga2O3 diode, and the diode sequentially comprises a cathode ohmic contact electrode, an n-type Ga2O3 substrate, an n-type Ga2O3 epitaxial layer, a composite dielectric layer, and an anode ohmic contact electrode located on a p-type oxide layer and a part of the surface of the inclined field plate from bottom to top, the composite dielectric layer comprises a p-type oxide layer and an inclined field plate, the orthographic projection of the inclined field plate surrounds the orthographic projection of the p-type oxide layer in the direction perpendicular to the plane where the n-type Ga2O3 substrate is located, the cross section of the p-type oxide layer is in an inverted trapezoid shape, and the side wall of the junction of the inclined field plate and the p-type oxide layer has an inclined angle. According to the invention, surface leakage current is inhibited by using a depletion region of a pn junction formed by the P-type oxide layer and the n-type Ga2O3 epitaxial layer, and an edge electric field of the anode ohmic contact electrode is dispersed by using the inclined field plate, so that dual homogenization of a bulk electric field and a surface electric field is realized.

The invention discloses a chip module cutting method, and relates to the technical field of semiconductor manufacturing. The chip module cutting method comprises the steps that a wafer to be cut is cut, independent chip modules are obtained, the wafer to be cut comprises a plurality of chip modules, each chip module comprises an intermediary layer and crystal grains, and the crystal grains are arranged on the surface of the intermediary layer; and chamfering the chip module to obtain the chamfered chip module. By implementing the chip module cutting method provided by the embodiment of the invention, chamfering processing is performed on the four corners of the interposer of the chip module, stress concentration points are eliminated, the mechanical stress problem of the large-size expensive interposer is improved, and the product manufacturing yield is improved; furthermore, a silicon interposer with a larger size can be manufactured to carry a high-performance processor and more high-bandwidth memories, so that the computing power is further improved; and a secondary cutting process is adopted in the cutting process, so that damage to the silicon interposer caused by non-uniform stress at a medium junction can be avoided.

The application provides a preparation method of a semiconductor structure and the semiconductor structure, and relates to the technical field of semiconductors. The preparation method comprises the following steps: providing a metal interconnection semi-finished product, which comprises a first dielectric layer, a metal layer arranged in the first dielectric layer and on the surface of the first dielectric layer, and a barrier layer for isolating the metal layer from the first dielectric layer; performing first planarization treatment on the metal layer with the barrier layer as a stop layer; forming a photosensitive dielectric layer on the surface of the barrier layer and the metal layer; performing second planarization treatment on the photosensitive dielectric layer under first light conditions with the barrier layer as the stop layer; performing third planarization treatment on the barrier layer under light-shielding conditions to remove the barrier layer on the surface of the first dielectric layer; performing fourth planarization treatment on the remaining photosensitive dielectric layer under second light conditions until the photosensitive dielectric layer is completely removed; and performing fifth planarization treatment on the remaining metal layer. The preparation method can reduce the notch depression of the junction area between the metal layer and the barrier layer, and is beneficial to the stability of subsequent electrical properties.

Disclosed are a semiconductor device and a manufacturing method thereof. The manufacturing method comprises: providing a semiconductor substrate; etching the substrate to form a trench in the substrate; filling the trench with insulating material; etching the insulating material to expose a sharp corner at the intersection of the trench sidewall and the upper surface of the substrate; and forming a field oxide layer on part of the upper surface of the substrate and the insulating material, wherein the sharp corner at the intersection of the trench sidewall and the upper surface of the substrate is oxidized in the step of forming the field oxide layer. The method exposes a sharp corner at the intersection of the shallow trench isolation structure and the substrate surface by etching back the shallow trench isolation structure, and eliminates the sharp corner in the step of forming the field oxide layer, thereby avoiding charge accumulation at the sharp corner and improving the breakdown voltage and reliability of the device.

The application relates to a semiconductor chip and a manufacturing method thereof, which comprises a chip substrate 1 and an electro-absorption modulator EAM 2 arranged on the chip substrate 1; the electro-absorption modulator EAM 2 comprises a first substrate 201, a support column 202, a first active region 203 and a first upper waveguide region 204 arranged in sequence from bottom to top; the width of the support column 202 and the width of the first upper waveguide region 204 are both smaller than the width of the first active region 203. The application can effectively inhibit the deterioration of the sidewall to the electrical and optical properties, improve the bandwidth of the chip, reduce the interface dark current and defects, reduce the light loss of the chip and improve the light output power of the chip under the condition of reducing the reverse PN junction area.

A power battery module disassembly table includes a disassembly table body. A first baffle and a second baffle are arranged along the length of the upper surface of the disassembly table body, and are staggered horizontally. The upper surface of the disassembly table body includes two workstation areas located outside the first and second baffles and a junction area between them. The workstation areas are divided into a disassembly area and a placement area. A lifting groove is provided in the disassembly area, and a lifting plate is installed at the lifting groove. A drive assembly is provided at the bottom of the disassembly table body, capable of driving the lifting plate to move up and down. The ability to drive the lifting plate in the disassembly area to move up and down allows battery modules to be placed on the lifting plate, enabling workers to flexibly adjust the distance between themselves and the battery modules according to height requirements, reducing the workload of disassembly personnel and improving disassembly efficiency.

The present application relates to a kind of mould parts processing method, it relates to surface treatment technical field, comprising: control first polishing piece respectively or simultaneously on two sliders preset first polishing area is polished, and first polishing piece includes graphite structure;Control two slider assemblies are integrated slider assembly;Control second polishing piece in the preset second polishing area of the junction of two sliders is polished, to eliminate the difference of two sliders in preset second polishing area, and second polishing piece includes graphite structure;Two sliders are mirror polished, to remove the machining marks left by first polishing piece and / or second polishing piece on two sliders.In two polishing steps, tool includes graphite structure, it has the characteristics of wear resistance, can reduce the consumption speed, reduce the risk of deformation, and respectively using first and second polishing piece adaptively polishing action, can improve polishing effect, again by mirror polishing, finally reach excellent processing effect.

The invention discloses a wafer Taiko structure integrated forming method based on laser internal modification stripping, belongs to the technical field of semiconductor manufacturing, and is particularly suitable for hard and brittle wafers such as silicon carbide or diamond. The method comprises the following steps: (1) focusing an ultrafast laser beam in a wafer; (2) laser parameters are set, a three-dimensional distribution modified layer is formed in the wafer through scanning, when the wafer is made of silicon carbide, the modified layer is an amorphous or polycrystalline layer, and when the wafer is made of diamond, the modified layer is a graphite phase modified layer; (3) controlling the modified layer to keep a preset depth in the center area of the wafer, extending and penetrating towards the back surface of the wafer at the junction of the center and the edge Taiko ring, and processing a plurality of micropores or lines penetrating to the modified layer in the back waste block area; (4) chemical etching liquid is utilized to synchronously permeate through gaps at the junctions and the micropores, the modified layer is rapidly removed, and integrated separation of the center wafer main body and the back waste blocks is achieved; and (5) the separated surface is subjected to cleaning and ultra-precision polishing. According to the method, by constructing the three-dimensional modified separation interface and combining multi-channel chemical etching, efficient and stress-free forming of the Taiko structure is achieved, the machining cost is remarkably reduced, and the surface quality is improved.

This invention proposes a high-current charging device, including a charging gun body and a charging port. The charging gun body includes a plug-in post, and the charging port includes a conductive sleeve. A tripping retaining ring is provided on the inner wall of the inner sleeve facing the charging gun body, and a tapered tripping slope is provided at the junction of the end face of the tripping retaining ring facing away from the charging gun body and the outer wall. A main elastic groove is provided at the front section of the conductive sleeve, and a secondary elastic groove is provided on the outer wall from the front section to the middle section. Buffer grooves are formed on the sleeve wall between adjacent secondary elastic grooves at the middle section of the conductive sleeve. An expansion slope adapted to the tripping slope is provided at the junction of the front end face of the conductive sleeve and the inner wall. This invention has the advantages of reliable connection, effectively reducing wear and insertion / removal resistance, while ensuring connection reliability.

This invention relates to a lateral homo-heterojunction memory device and its fabrication method. The memory device includes a substrate gate layer, a first dielectric layer, a second dielectric layer, a two-dimensional semiconductor channel layer, and ohmic electrodes. The first and second dielectric layers are both located on the substrate gate layer and are in contact with each other. The two-dimensional semiconductor channel layer is located on the first and second dielectric layers. The ohmic electrodes are located at both ends of the two-dimensional semiconductor channel layer. This memory device uses a composite dielectric layer to perform dielectric modulation and electrostatic gate modulation on the two-dimensional semiconductor channel layer, thereby forming a lateral heterojunction in a homogeneous material. The cross-section of the formed lateral heterojunction is located at the junction of the first and second dielectric layers, and the interface of the formed lateral heterojunction consists of only one line, reducing defects at the interface. Furthermore, since the heterojunction is formed using the same material, there is no lattice mismatch problem between different materials, thus improving the electrical performance of the memory.

The embodiment of the present disclosure relates to the semiconductor field, and provides a manufacturing method of a semiconductor structure and the semiconductor structure, the manufacturing method of the semiconductor structure comprising: providing a substrate, forming a first groove and a second groove in the substrate, and the depth directions of both are the first direction; the first groove comprises a plurality of first sub-grooves arranged in the first direction, the second groove comprises a plurality of second sub-grooves arranged in the first direction, and the side walls of the first sub-grooves and the second sub-grooves are all convex outward; forming a word line protruding away from the first groove at the junction of adjacent first sub-grooves; forming a first source-drain layer on the side wall of the first sub-groove; forming a second source-drain layer protruding away from the second groove at the junction of adjacent second sub-grooves; the second source-drain layer and the word line are both located between the first groove and the second groove, and the second source-drain layer is oppositely arranged with the word line. The embodiment of the present disclosure can at least improve the performance of the semiconductor structure.

This invention relates to the field of semiconductor manufacturing technology, specifically disclosing a method for processing heavily doped substrate silicon wafers and the epitaxial wafers formed therefrom. This invention adjusts the process steps of traditional processing methods for heavily doped substrate silicon wafers with a composite back-sealing structure of "polysilicon + silicon dioxide". After the polysilicon layer is deposited on the substrate, edge polishing is performed first to remove polysilicon from the chamfered surface, followed by the deposition of the silicon dioxide layer. This process optimization ensures that the junction between the flat back surface and the chamfered surface of the substrate is always completely covered by the silicon dioxide layer, avoiding polysilicon deposition and protrusion formation during epitaxy caused by exposure of monocrystalline silicon. This invention effectively solves problems such as lithography machine vacuum alarms and defocus defects caused by back edge protrusions in existing processes, significantly improving the flatness of the epitaxial wafer and the manufacturing yield for end customers.

The application relates to the technical field of glass, in particular to a manufacturing method, system and application of heat-bending-free 3D cover plate glass. The method utilizes laser to construct an induced prestress field on a glass substrate to release 50%-85% of target strain; then, single-side polishing fine adjustment is carried out, the polishing surface to be polished is divided into a center, an edge and a corner area, and stepped pressure is applied to compensate for the removal rate difference; a pressure buffer zone is dynamically generated at the junction of the areas, and the pressure is adjusted based on a smoothing algorithm to ensure that the first and second derivatives are continuous and the step mutation is eliminated. Through light-mechanical coupling stress regulation and dynamic continuous control, the application completely eliminates edge collapse and vibration marks, realizes micron-level curvature shaping, improves the glass surface type precision, optical uniformity and structural strength, and efficiently manufactures high-quality 3D cover plates without high-temperature heat bending.