248 results about "Junction area" patented technology

The invention provides a color filling method and electronic equipment, a first interface is displayed, the first interface comprises a first area and a second area, the color of the first area is a first color, the color of the second area is a second color, and the junction of the first area and the second area comprises M colors, the M colors are different from the first color and the second color; determining P colors according to the second color, the third color and one or more colors in the M colors in response to an operation of filling the second area with the third color by the user; the second color is replaced by the third color, one or more colors in the M colors are replaced by the P colors, and the new color of the junction is determined according to the color to be filled, the color of the seed point and the color of the junction, so that on the basis of ensuring the filling effect, the color transition can be better performed, the sawtooth feeling is reduced, and the filling efficiency is improved. And the drawing experience of the user can be improved.

A gate structure is formed on a substrate at the junction of a well region and a drift region, the gate structure on the drift region is doped to form a first doped region and a second doped region which are adjacent to each other, the first doped region is doped with first type ions, and the second doped region is doped with second type ions; the conduction types of the second type ions and the first type ions are different, so that the first doped region and the second doped region form a reverse biased PN junction, an electric field caused by the interconnection structure can be balanced and dispersed in the direction from the drain electrode to the source electrode, and the high voltage of the interconnection structure can be effectively isolated; besides, the first doped region and the second doped region form a reverse-biased PN junction to disperse the high potential difference between the first doped region and the second doped region, so that the electric field intensity and the potential peak value on the surface of the device are effectively reduced, the segmented voltage division effect is beneficial to optimization of electric field distribution on the surface of the device, electric field concentration is reduced, and the performance of the device is improved. Therefore, the breakdown voltage of the semiconductor structure is improved.

The invention provides a manufacturing method of a sigma trench, which comprises the following steps: providing a substrate, forming a gate oxide layer and a gate structure on the substrate, the gate structure comprising a gate, a first mask layer and a second mask layer which are sequentially formed on the gate oxide layer; etching for the first time by taking the second mask layer as a mask until the second mask layer is removed, forming a first groove in the substrate on two sides of the gate structure, and gathering polymers generated by etching the second mask layer in the etching process on the gate oxide layer on the side wall of the first groove and a junction area of the gate oxide layer, the gate and the substrate as an etching protection layer; and performing second etching by taking the first mask layer as a mask, protecting the substrate covered by the etching protection layer from lateral etching by the etching protection layer, and forming a sigma-like groove in the first groove. According to the method, the etching protection layer is formed on the side wall of the first groove through the polymer generated by the second mask layer in the first etching process, the area is prevented from being excessively etched, serious lateral pushing of the area is avoided, and therefore the shape of the groove can be adjusted and controlled more easily.

The invention discloses a power module packaging structure. According to the chip, a non-linear conductive material coating is arranged at the connecting part of the edge of each metal bonding pad and a chip substrate, and the connecting part of the edge of each metal bonding pad and the chip substrate is the joint of the metal bonding pad, the chip substrate and an insulating encapsulating material, namely the three-phase point. Through the arrangement of the non-linear conductive material coating, the resistivity is high in a normal low field, and electric leakage is prevented; and when the local electric field intensity is increased sharply (terminal at the three-phase junction), the resistivity is reduced sharply, the electric field is uniformly dispersed, and the peak of the local electric field is inhibited, so that the overall dielectric strength and creepage distance of the module are improved. According to the technical scheme, the insulation reliability of the power module under high-voltage, high-frequency and high-temperature working conditions is remarkably improved, particularly, partial discharge is restrained at a three-phase point, the service life of the module is prolonged, and the production and maintenance cost is reduced.

The present application relates to a kind of low scattering carriers for RCS test, including carrier body, carrier body includes first surface and second surface, first surface and second surface are connected to form hollow cavity, hollow cavity is used to accommodate cylindrical target component;One end of hollow cavity is tip, the other end is open end, open end is circular, cylindrical target component is installed in hollow cavity through open end;Horizontal plane is formed at the junction of first surface and second surface, the height of first surface beyond horizontal plane is less than the height of second surface beyond horizontal plane, the radius of curvature of first surface gradually increases from tip to open end direction, the radius of curvature of second surface increases first and then decreases from tip to open end direction.The low scattering carrier in the present application can simulate the installation state of cylindrical target component, realize the accurate evaluation of the RCS of cylindrical target component.

The invention relates to the technical field of photovoltaic power generation, in particular to a solar cell and a photovoltaic module. The solar cell comprises a substrate, a patterned doped silicon layer, a passivation layer and an electrode, wherein the doped silicon layer is located between the substrate and the passivation layer; the doped silicon layer comprises a first sub-layer with a first thickness and a second sub-layer with a second thickness, the first sub-layer and the second sub-layer are connected along the first direction, the first thickness is greater than the second thickness, and the second thickness is greater than or equal to 0 [mu] m; the orthographic projection of the junction of the first sub-layer and the second sub-layer on the substrate is a boundary, the boundary comprises a plurality of connected units, and the units comprise convex units and / or concave units; the protruding direction of the protruding units is in the second direction, and the protruding shape of the protruding units is in a non-sharp-corner shape. The concave direction of the concave unit is in the second direction, and the concave shape of the concave unit is a non-sharp-corner shape; the second direction intersects with the length direction of the electrode; an electrode is in contact with the first sub-layer through the passivation layer.

According to the coil component and the electric valve provided by the utility model, the limiting structure is arranged in the coil component, and at least one part of the limiting structure is arranged at the junction of the insulating layer and the free section, so that one side, at least close to the insulating layer, of the free section can be limited and supported through the limiting structure. Through the scheme, the movement range of the part, close to the insulating layer, of the free section of the wire (namely the junction of the free section and the insulating layer) is limited, namely the movement range of the part, exposed out of the insulating layer, of the wire relative to the part, fixed in the insulating layer, of the wire is limited at least from one direction; in this way, large stress concentration caused by large-angle bending of the position where the wire penetrates out of the insulating layer is prevented at least from one direction, so that the risk that the wire is bent to be damaged or broken at the position is reduced or avoided, and the product reliability is improved.

The invention discloses a manufacturing method of a grinding wheel for a high-uniformity and easy-to-sharpen grinding single crystal diamond cutter, and belongs to the field of superhard materials and products in machining, the manufacturing method mainly comprises the steps of wet mixing, tape casting, laser cutting, lamination, matrix surface treatment, integrated sintering, size processing, sharpening and the like, and finally the grinding wheel with the total thickness of an abrasive layer being 7-15 mm is formed. The grinding wheel layer is formed by intersecting and laminating a piece a and a piece b, the height of diamonds at the junction of the piece a and the piece b tends to be consistent, the diamond exposure height and smoothness are better compared with direct feeding sintering, meanwhile, the piece a can be designed to be of a porous structure through proper binder selection, and therefore the dressing efficiency is further improved, and the dressing effect is better. And higher processing quality and efficiency of the diamond cutter are indirectly improved.

A foldable display device includes a reflective display panel, a light guide layer, and at least one light source. The light guide layer is located on the reflective display panel and includes a non-bending area, a bending area, and a junction area. The bending area is located in the middle of the light guide layer. The junction area is located between the bending area and the non-bending area. The light source is located on the reflective display panel and faces the sidewall of the non-bending area, and is configured to emit light to the light guide layer. Because the thickness of the non-bending area is greater than the thickness of the bending area, sufficient light input to the light guide layer is ensured. The smaller thickness of the bending area reduces the material rigidity of the bending area, allowing the foldable display device to fold at the bending area. The thickness of the junction area is between the non-bending area and the bending area, thus enabling total internal reflection of light from the light guide layer to the bending area. This ensures sufficient light input without requiring an additional light source and also improves the power efficiency of the foldable display device.

A method for forming a semiconductor structure, the method comprising: providing a substrate, the substrate having a source region and a drain region formed therein, a drift region formed in the substrate between the source region and the drain region, the drift region being in contact with the drain region, a gate structure formed on a top of the substrate at an interface of the source region and the drift region; forming a first dielectric layer on the top of the substrate at the source region, the drain region and the drift region, the first dielectric layer also covering sidewalls of the gate structure; forming a recess in a middle region of a top surface of the first dielectric layer at the drift region; after forming the recess, forming a first trench in a portion of the first dielectric layer at the drift region, the first trench being in communication with the recess, forming a second trench through the first dielectric layer at the source region and the drain region; forming a field plate contact hole in the first trench, the field plate contact hole covering the first dielectric layer at a bottom of the first trench, forming an interconnection via structure in the second trench, the interconnection via structure being in electrical connection with the source region and the drain region. The thickness uniformity of the first dielectric layer below the bottom of the first trench is improved.

Embodiments of the present application provide a pin grid array structure, comprising: a package lead frame; and a moisture barrier layer disposed on an upper surface of the package lead frame and covering an intersection of a package compound and the lead frame of the package lead frame. The purpose of the present application is to provide a pin grid array structure and a semiconductor structure to improve yield.

This invention provides a bass reflex port that can effectively suppress port noise, and a speaker system equipped therewith. [Solution] The inner circumferential surface 50 of the bass reflex port 40 comprises a straight pipe section 51 having a constant diameter d0 along the axial direction, and an enlarged diameter section 52 whose diameter gradually increases as it moves away from the straight pipe section 51 along the axial direction. The enlarged diameter section 52 has a first enlarged diameter section 53 and a second enlarged diameter section 54. The axial length L1 of the first enlarged diameter section 53 is 15% or more of the diameter d0 of the straight pipe section 51, and the enlargement ratio d1 / d0 in the first enlarged diameter section 53 is 125% or less. An angle section 55 with a locally smaller radius of curvature is formed at the boundary between the first enlarged diameter section 53 and the second enlarged diameter section 54.

The invention discloses a micro trench gate IGBT device structure and a preparation method thereof, the device structure comprises a wafer substrate, a gate oxide layer, a polycrystalline silicon layer, a dielectric layer and a metal layer, trenches are formed on the wafer substrate, and the trenches comprise a gate trench and a virtual gate trench; the gate oxide layer covers the surface of the wafer substrate; the polycrystalline silicon layer is filled in the groove; the dielectric layer covers the gate oxide layer and the polycrystalline silicon layer; a contact hole is formed in the dielectric layer and extends into the wafer substrate and the polycrystalline silicon layer; the coverage area of the contact hole comprises a part of the virtual gate trench, a part of the wafer substrate and a gate oxide layer at the junction; the metal layer is stacked on the surface of the dielectric layer and fills the contact hole. According to the invention, the short circuit of the virtual gate and the source electrode is realized through one contact hole, and the requirement on the photoetching line width is reduced, so that photoetching can be carried out by using an I-line photoetching machine, the preparation cost is reduced, and the compatibility of wafer flatness and warping degree can be improved by using the I-line photoetching machine process.

A tiled display device with improved staining at the junction and a sub-display panel employed therein are disclosed. The tiled display device comprises: a first sub-display panel having a plurality of unit pixels formed therein; and a second sub-display panel disposed adjacent to the first sub-display panel and having a plurality of unit pixels formed therein, wherein each of the unit pixels comprises a plurality of sub-pixels having a display element that emits color light and a pixel circuit that drives the display element, and wherein the arrangement order of sub-pixels within the unit pixels corresponding to the current row and the arrangement order of sub-pixels within the unit pixels corresponding to the previous row or the next row are different from each other. Accordingly, by configuring the arrangement order of sub-pixels within the unit pixels corresponding to the current row and the arrangement order of sub-pixels within the unit pixels corresponding to the previous row or the next row differently from each other, the visibility of staining caused by the sub-pixel arrangement near the junction area can be improved.

The utility model discloses a silicon carbide MOSFET junction terminal structure, and belongs to the technical field of semiconductor devices. Comprising a first passivation layer, an N-drift region, an N + substrate, a cathode metal electrode layer, a Pwell cellular transition region, a Pplus main junction region, a Pplus field limiting ring region, a Pwell main junction region, a Pwell field limiting ring region, a JTE main junction region, a JTE field limiting ring region, an anode metal electrode layer and a second passivation layer. And the Pwell cell transition region, the Pplus main junction region, the Pplus field limiting ring region, the Pwell main junction region, the Pwell field limiting ring region, the JTE main junction region and the JTE field limiting ring region are sequentially manufactured on the N-drift region from left to right. And the junction area of every two junction termination extension structures is a field limiting ring. The problems that a field limiting ring structure of an existing silicon carbide MOSFET is large in occupied area, and a junction terminal expansion structure is complex in process are solved. The method is widely applied to the silicon carbide MOSFET design and manufacturing technology.

This invention discloses a stepped P-well high-voltage shielded gate MOSFET, relating to the field of power electronics technology. The stepped P-well high-voltage shielded gate MOSFET includes a device housing with a voltage-resistant shielding component installed inside. The voltage-resistant shielding component comprises an N-type substrate, an N-type drift region, and a stepped P-well region. The stepped P-well region extends in a multi-step manner along the source-to-drain direction, with the doping concentration decreasing gradually along the source-drain direction. A trench is provided at the boundary between the P-well region and the N-type drift region, and a shielding gate is embedded in the trench. A gate dielectric layer is provided on the surface of each key structure. The source is electrically connected to the stepped P-well region and the shielding gate and is diagonally positioned opposite the drain. This invention optimizes the electric field distribution and weakens the electric field concentration through the synergistic effect of the stepped P-well gradient doping and the shielding gate, significantly improving the device's voltage withstand performance while reducing conduction and switching losses. It is compatible with existing fabrication processes and can be widely applied in high-power scenarios such as new energy and power electronics.

The embodiment of the invention provides a semiconductor device, a forming method thereof and a storage system, and the semiconductor device comprises a plurality of conductive wires which extend along a first direction and are arranged at intervals along a second direction; the first direction and the second direction intersect with each other; and a contact structure extending in the third direction and connected to at least a first conductive line of the plurality of conductive lines, the contact structure including a first sub-contact structure connected to the first conductive line and a second sub-contact structure located on the first sub-contact structure; in the second direction, the first size of the first sub-contact structure at the junction is smaller than the second size of the second sub-contact structure at the junction. Wherein the third direction is perpendicular to the first direction and the second direction.

The utility model provides a fixing frame, a backlight module and a display device.The fixing frame is applied to the backlight module, the backlight module is provided with a display area and a non-display area surrounding the display area, the fixing frame comprises a frame, the inner side of the frame is defined by the frame, the frame comprises a first supporting part and a second supporting part, and the first supporting part and the second supporting part are oppositely arranged; the first supporting part is provided with a first bearing surface; the second supporting part is connected to the first bearing surface of the first supporting part; the first supporting part is further provided with a first inclined face, the first inclined face faces the inner side of the frame, the first inclined face is connected with the first bearing face, the first inclined face inclines towards the direction close to the inner side of the frame from the first bearing face, and at least part of the first inclined face is correspondingly arranged on the non-display area and the junction of the non-display area. The fixing frame can improve the display quality of the display device.

The application discloses a kind of slice switching section structures, it is related to wind power facilities field.Slicing switching section structure includes angle column, inner steel cylinder and box type combined beam;Each angle column is fixed with inner steel cylinder by a box type combined beam;Slicing switching section structure is fixed by at least two rotationally symmetrical splicing structures by connecting mechanism;Switching section structure also includes bottom reinforcing component, top reinforcing component and vertical reinforcing component.The application solves the problem of transportation size limit by splicing design, meets the requirements of transportation limit;Bottom reinforcing component strengthens the shear capacity of the junction of angle column and inner steel cylinder, top reinforcing component improves load transfer path, vertical reinforcing component suppresses lateral deformation, reduces stress concentration phenomenon together, greatly optimizes the stress distribution of the junction area of angle column, inner steel cylinder and box type combined beam;Under the premise of guaranteeing structure safety, avoid the problem of excessive use of material for traditional reinforcement structure, improve material utilization efficiency, reduce construction cost.

The invention discloses a device and method for synchronously eliminating depressed layer lines in the metal additive manufacturing process. The device comprises a rotatable support, an adjustable clamp and a swing laser head. In the metal wire feeding additive manufacturing process, the rotatable support is connected with a machining head of additive manufacturing equipment, the rotation angle of the rotatable support is adjusted in real time according to an additive manufacturing path, and the focus of the laser head is aligned with the layer grain depression slightly falling behind a forming molten pool by adjusting the adjustable clamp so that the layer grain depression can be eliminated. And melting the metal material near the junction of the current layer and the previous layer, and filling the layer grain depressions after the material is molten and solidified, so as to realize synchronous elimination or reduction of the layer grain depressions in the material adding process. According to the method, on the premise that the manufacturing time and the material cost are not obviously increased, the part surface quality, the forming precision and the material utilization rate are obviously improved, the post-treatment complexity is reduced, meanwhile, the process layer high selection space is expanded, and the process flexibility is improved.

The utility model relates to the technical field of photovoltaic modules, in particular to a corner connector, a photovoltaic frame and a photovoltaic module. The corner connector is used for solving the problems that an existing corner connector is high in material cost, small in elasticity, free of direct observation view, prone to falling off and the like, and the yield of photovoltaic modules is affected. The corner connector comprises two connecting arms which are perpendicularly intersected and are of the same structure, each connecting arm is provided with two opposite fixing faces, a first cavity and a second cavity which are independent of each other are formed by penetrating through the fixing faces, the first cavity is far away from the joint of the connecting arms, and the second cavity is close to the joint of the connecting arms. And the cross sectional area of the first cavity is firstly increased and then decreased from the top end of the connecting arm to the direction close to the junction. The first cavity is provided with a flaring cavity section and a closing cavity section in the direction from the top end of the connecting arm to the joint, and the length of the closing cavity section is larger than that of the flaring cavity section. And the length of the closing cavity section is 3-4 times that of the expanding cavity section.

The invention relates to a mass transfer method and a micro-display device. In the mass transfer method, a target wafer is selectively stripped, a plurality of splicing blocks with intersection areas are formed on a bearing plate, and a plurality of micro light-emitting chips in the intersection areas corresponding to a plurality of subsequently spliced adjacent splicing blocks are in a random and complementary distribution state. The intersection areas of the adjacent splicing blocks are overlapped and aligned, and mutual embedding between the adjacent splicing blocks is realized based on the intersection areas, so that the boundary between the adjacent splicing blocks is not a continuous line any more, and the splicing boundary is faded; on the basis of the complementary design of a plurality of intersection regions, a regular overlapping splicing array is formed at the junction of the adjacent splicing blocks, so that the adjacent splicing blocks look like a whole, and the splicing boundary between the adjacent splicing blocks is further faded.

The invention discloses a superconducting quantum chip flip-chip bonding process, a quantum chip, a storage medium and electronic equipment. The process comprises the following steps: providing a first substrate containing a Josephson junction and a first welding spot array in a non-junction region, a corresponding second substrate and a second welding spot array; the two substrates are in inverted butt joint, so that the welding spots are matched and aligned; and carrying out local annealing and pressure welding on the aligned welding spots. According to the method, local heating is carried out on the indium column through the laser micro-area annealing technology, and the problem that a Josephson junction is heated and damaged due to the fact that traditional flip-chip bonding whole-face heating is carried out is effectively solved. And meanwhile, the shortest heating time can be shortened to 40ms, thermal stress and deformation are greatly reduced, and due to the non-contact and repeatable characteristics of laser annealing, the method is suitable for large-scale efficient production of the superconducting quantum chip, the stable performance of the device is ensured, and the manufacturing yield is improved.

This light-condensing structure (12) for optical elements is formed on a surface of a semiconductor substrate (11) of an optical element (10), said light-condensing structure comprising: a spherical lens (121) that is convex in a direction perpendicular to the surface of the semiconductor substrate; a base part (122) that is disposed in the periphery of the lens (121); and a recess (124) that is formed in a side wall of the base part in the vicinity of the border between the side wall of the base part and the surface of the semiconductor substrate.　Thus, the present invention can provide a light-condensing structure for optical elements that has a lens with excellent light condensing efficiency.

The invention discloses a stamping connection terminal and a preparation method thereof, and relates to the technical field of electric appliance connection terminals. The stamping connection terminal is integrally formed by continuously stamping a high-precision phosphor copper strip, and comprises a contact end and a connection end. The contact end comprises a pair of elastic contact arms which are oppositely arranged, the free end of each elastic contact arm is bent to form a guide flange with a guide surface, and a plurality of hemispherical contact salient points are arranged at the junction of the guide surface and the elastic contact arms. The connecting end is provided with a clamping structure, and the clamping structure is provided with at least two rows of antiskid teeth which are distributed in a staggered mode. And a transition region between the contact end and the connection end. The surface of the contact end is provided with a gold-plated layer, and the surfaces of the connecting end and the transition area are provided with a mist tin-plated layer. The purity of the high-precision phosphorus copper strip is larger than or equal to 99.95%, the content of phosphorus is 0.03-0.08 wt%, the tensile strength is 350-400 MPa, and the ductility is larger than or equal to 15%. According to the invention, the problems that the connection is not tight enough, the conductive performance is not stable and the preparation cost is high in the actual use process of the current connection terminal can be effectively improved.

The invention provides a grating-integrated semiconductor light-emitting structure and a preparation method thereof, the grating-integrated semiconductor light-emitting structure comprises a semiconductor substrate layer, a gain structure and a grating waveguide dielectric structure, and the junction of the grating waveguide dielectric structure and the gain structure is provided with an anti-reflection structure; the gain structure is located on one side of a part of the semiconductor substrate layer in the fast axis direction, and the gain structure comprises a first semiconductor limiting layer, a first semiconductor waveguide layer, an active layer, a second semiconductor waveguide layer and a second semiconductor limiting layer which are sequentially arranged in the fast axis direction; the grating waveguide dielectric structure is located on one side of a part of the semiconductor substrate layer in the fast axis direction and located on one side of the gain structure in the cavity length direction, and a grating is integrated in the grating waveguide dielectric structure. And the wavelength temperature drift coefficient of the semiconductor light-emitting structure of the integrated grating is reduced.

The application provides a semiconductor structure manufacturing method, which comprises the following steps: providing a substrate; forming a first electrode layer on one side of the substrate; forming a dielectric layer on the surface of the first electrode layer far from the substrate; forming a second electrode layer on the surface of the dielectric layer far from the first electrode layer; performing chlorine removal pretreatment on the second electrode layer; and forming a third electrode layer on the surface of the second electrode layer far from the dielectric layer. The method solves the problem that chlorine ions at the junction of a silicon germanium layer in the prior art affect the interface reliability.

The application relates to a semiconductor structure and a preparation method thereof. The preparation method of the semiconductor structure comprises the following steps: a shallow trench isolation structure is formed in a substrate, the shallow trench isolation structure extends upward from the substrate and has a first protruding part protruding from the substrate; a local oxidation material layer is located at the junction of an active region and the shallow trench isolation structure and has a second protruding part protruding from the upper surface of the active region; a sacrificial oxide layer is located on the upper surface of the active region and is in contact with the local oxidation material layer; the sacrificial oxide layer and the second protruding part are removed to form a local oxidation layer and form a groove on the side wall of the first protruding part towards the local oxidation layer; a gate oxide layer is located on the upper surface of the active region and is in contact with the local oxidation layer; and a gate electrode is located at least on the upper surface of the gate oxide layer and fills the groove. The preparation method of the semiconductor structure optimizes the semiconductor structure, improves the reliability of the semiconductor device, and reduces the failure rate of the semiconductor device.

The invention discloses a Ga2O3 diode adopting an inclined field plate and a NiO heterojunction and a preparation method of the Ga2O3 diode, and the diode sequentially comprises a cathode ohmic contact electrode, an n-type Ga2O3 substrate, an n-type Ga2O3 epitaxial layer, a composite dielectric layer, and an anode ohmic contact electrode located on a p-type oxide layer and a part of the surface of the inclined field plate from bottom to top, the composite dielectric layer comprises a p-type oxide layer and an inclined field plate, the orthographic projection of the inclined field plate surrounds the orthographic projection of the p-type oxide layer in the direction perpendicular to the plane where the n-type Ga2O3 substrate is located, the cross section of the p-type oxide layer is in an inverted trapezoid shape, and the side wall of the junction of the inclined field plate and the p-type oxide layer has an inclined angle. According to the invention, surface leakage current is inhibited by using a depletion region of a pn junction formed by the P-type oxide layer and the n-type Ga2O3 epitaxial layer, and an edge electric field of the anode ohmic contact electrode is dispersed by using the inclined field plate, so that dual homogenization of a bulk electric field and a surface electric field is realized.

The invention discloses a chip module cutting method, and relates to the technical field of semiconductor manufacturing. The chip module cutting method comprises the steps that a wafer to be cut is cut, independent chip modules are obtained, the wafer to be cut comprises a plurality of chip modules, each chip module comprises an intermediary layer and crystal grains, and the crystal grains are arranged on the surface of the intermediary layer; and chamfering the chip module to obtain the chamfered chip module. By implementing the chip module cutting method provided by the embodiment of the invention, chamfering processing is performed on the four corners of the interposer of the chip module, stress concentration points are eliminated, the mechanical stress problem of the large-size expensive interposer is improved, and the product manufacturing yield is improved; furthermore, a silicon interposer with a larger size can be manufactured to carry a high-performance processor and more high-bandwidth memories, so that the computing power is further improved; and a secondary cutting process is adopted in the cutting process, so that damage to the silicon interposer caused by non-uniform stress at a medium junction can be avoided.