67 results about "Junction diodes" patented technology

The invention discloses a semiconductor device based on two-dimensional semi-metal interface optimized contact and a preparation method thereof, which are applied to devices including a two-dimensional semiconductor-based metal-semi contact structure, such as thin film transistors, Schottky junction diodes / transistors and the like. According to the invention, the two-dimensional semi-metal interface layer is introduced between the metal electrode (source and drain electrodes) and the two-dimensional material (conductive channel) through PVD and CVD processes, so that pollution and defects caused by additional transfer steps are avoided, preparation of the interface layer with large area, high uniformity and controllable thickness can be realized, and industrial requirements are met. According to the semiconductor device provided by the invention, the two-dimensional semimetal is introduced as the interface layer, so that the contact resistance between the source and drain electrodes and the conductive channel is obviously optimized, Fermi level pinning is eliminated, and the adjustable Schottky barrier height is realized; and a brand new solution is provided for development and industrial application of a metal-semiconductor contact structure device of a high-performance two-dimensional semiconductor.

The invention relates to the technical field of semiconductors, in particular to a source heterojunction contact semiconductor structure and device and a manufacturing method, the semiconductor structure comprises a gate structure, a body region structure, a source structure and a drain structure, and the source structure comprises a polycrystalline silicon source contact layer; the semiconductor structure comprises a body region structure and a polycrystalline silicon source contact layer, the body region structure is surrounded by the gate structure, a source contact region is arranged in the body region structure, the polycrystalline silicon source contact layer is in contact with the source structure through the source contact region so as to form a heterojunction diode with the source structure, and the heterojunction diode is a freewheeling diode of the semiconductor structure. The drain electrode structure is located on one side, back to the gate electrode structure, of the body region structure; the semiconductor structure can be a SiC MOSFET structure, reverse conduction voltage drop during follow current of the SiC MOSFET can be greatly reduced, and conduction loss and loss caused during switching are reduced.

The invention discloses a Ga2O3 heterojunction beta irradiation battery with a multi-groove radioactive source, relates to the technical field of microelectronics, and solves the problems of low energy utilization rate and low energy conversion efficiency of a Ga2O3 nuclear battery radioactive source in the prior art. The battery comprises a filling type multi-groove radioactive source; the Ga2O3 heterojunction diode unit sequentially comprises a P-type ohmic contact electrode, a P-type NiO ion implantation region, an N-type Ga2O3 low-doped epitaxial layer, an N-type Ga2O3 high-doped substrate and an N-type ohmic contact electrode from top to bottom; a multi-T-type radioactive isotope source layer in the filling type multi-groove radioactive source is arranged above the P-type NiO ion implantation region and forms radiation energy coupling with the Ga2O3 heterojunction diode unit; the groove type structure is filled with the radioactive source, the energy deposition of the radioactive source entering the semiconductor conversion device is greatly increased, and the energy conversion efficiency of the Ga2O3 beta irradiation battery is improved.

A light emitting device comprising: a dual-wavelength Light Emitting Diode (LED) chip; and a manganese-activated fluoride phosphor comprising at least one of: K2SiF6:Mn4+, K2TiF6:Mn4+ and K2GeF6:Mn4+ for generating light with a peak emission wavelength from 620 nm to 660 nm; and wherein the dual-wavelength LED chip comprises a first p-n junction diode comprising a first Multiple Quantum Well structure for generating a blue light with a full width at half maximum emission intensity from 15 nm to 25 nm and a second p-n junction diode comprising a second Multiple Quantum Well structure for generating a green light with a full width at half maximum emission intensity from 15 nm to 45 nm.

The invention discloses a trench gate silicon carbide MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor). The top surface of a second conductive type doped first buried layer formed in a first conductive type doped silicon carbide epitaxial layer is lower than the bottom surface of a gate trench; and a heterojunction polycrystalline silicon layer filled in the second groove is formed on the outer side of the first side surface of the channel region. A lateral current path is made up of the silicon carbide epitaxial layer located over the top surface of the first buried layer, and a longitudinal current path is made up of the silicon carbide epitaxial layer located between the second side of the first buried layer and the bottom of the gate trench and forms a current path of the heterojunction diode together with the lateral current path. A plurality of first connecting layers are formed in a partial region where the first buried layer and the channel region are overlapped, intervals are formed between the first connecting layers in the length direction of the first buried layer, and interval regions are constituent parts of a transverse current path. The invention further discloses a manufacturing method of the trench gate silicon carbide MOSFET. According to the invention, the heterojunction diode can be integrated.

A main semiconductor device element and a temperature sensing section for sensing the temperature of the main semiconductor device element are provided on a semiconductor substrate containing SiC. The temperature sensing section (10) is a lateral pn-junction diode formed in a polysilicon layer (3) and provided on a front surface of a semiconductor substrate (101) by means of an interlayer insulating film (9). A p-type anode region (1) of the temperature sensing section (10) is formed by ion implantation of B or In into the polysilicon layer (3). The temperature sensing section and an n-type cathode region are formed by ion implantation of P or Sb into the polysilicon layer. The sheet resistance of the p-type anode region (1) at 25 °C is not less than 50 Ω / □ but not more than 170 Ω / □.The n-type cathode region (2) exhibits a surface resistance of not less than 80 Ω / □ but not more than 400 Ω / □ at 25 °C. Thus, the temperature sensing accuracy of the temperature sensing section (10) can be improved.

The invention provides a display device which comprises a display panel and a driving chip, the display panel comprises an array substrate, the array substrate comprises a semiconductor layer and a gate layer, a photosensitive diode is arranged in the array substrate and comprises a PN junction diode composed of the semiconductor layer and the gate layer, and a metal wire is electrically connected with the photosensitive diode. The driving chip is electrically connected with the metal wire, and the driving chip is used for sending a sampling signal to the photosensitive diode, receiving a sensing signal of the photosensitive diode, generating ambient light brightness information according to the sensing signal, and adjusting the brightness of the display panel according to the ambient light brightness information. According to the display panel, the photosensitive diodes are integrated into the array substrate of the display panel, independent light sensing sensors do not need to be arranged on the periphery of the front-facing camera, the peripheral space of the front-facing camera is released, a camera with a larger size can be arranged, meanwhile, the cost of photosensitive components is reduced, and the display efficiency is improved. And the sensitivity and the response speed of sensing the ambient light are improved.

This invention relates to a GaN-based pn junction diode device with a polarized beveled termination structure and its fabrication method. The device includes a cathode, a GaN substrate, an epitaxial layer, and an anode. The epitaxial layer comprises a lightly doped n-type GaN layer, an intrinsic GaN layer, and a p-type doped GaN layer grown in a single epitaxial growth process. The anode ohmic contact metal is placed on the p-type doped GaN layer, and the cathode ohmic contact metal is placed on the back side of the GaN substrate. It also includes a polarized beveled termination structure formed at the interface containing the pn junction, using inductively coupled plasma reactive ion etching (ICP-R) and a photoresist mask. The photoresist mask is formed using thick photoresist, followed by high-temperature heating and annealing to form the reflow morphology of the photoresist. Finally, wet repair and a passivation layer are applied to suppress the beveled n-type donor surface states of the polarized beveled termination structure. This invention effectively alleviates the boundary electric field concentration problem of GaN-based pn junctions and improves the breakdown voltage of GaN-based pn junctions.

A hybrid trench Schottky trench-type superbarrier diode and its fabrication method are disclosed. This relates to the field of semiconductor technology. From bottom to top, the diode comprises: a cathode electrode layer, an N+ substrate layer, an N- epitaxial layer, wherein the N- epitaxial layer has a plurality of spaced-apart P-type implantation regions; each P-type implantation region includes conductive channels and P-body regions spaced-apart from top to bottom; a dielectric layer, a silicon dioxide layer, wherein the silicon dioxide layer has a plurality of trenches extending downward from its top to the P-body regions; and an anode electrode layer, the bottom of which extends to the P-body regions through trenches. This invention improves the on-resistance characteristics of the device during forward operation, thereby enhancing the device's performance and reliability.

The invention relates to a semiconductor power device and a preparation method thereof. The semiconductor power device comprises a substrate, an epitaxial layer, a first grid electrode, a second grid electrode, a first dielectric layer, a second dielectric layer, a polycrystalline silicon region and a source electrode, wherein the material of the substrate comprises silicon carbide; the epitaxial layer comprises a drift region, a well layer, a first groove, a source region and a source contact region; the first groove extends into the drift region from the surface, far away from the substrate, of the epitaxial layer and penetrates through the well layer; the first grid electrode and the second grid electrode are located in the first groove, and the first grid electrode and the second grid electrode are arranged in an isolated mode. The first dielectric layer wraps the first grid electrode, the second dielectric layer wraps the second grid electrode, and the polycrystalline silicon region of the second conduction type is located between the first dielectric layer and the second dielectric layer and is in contact with the drift region to form a heterojunction diode; the source electrode is electrically connected with the second grid electrode to form a transistor of which the local grid electrode and the drain electrode are short-circuited, and the source electrode is also electrically connected with the polycrystalline silicon region. According to the invention, the conduction loss of the third quadrant can be reduced and the switching loss can be significantly reduced.

The invention belongs to the technical field of integrated circuits, and particularly relates to an ESD electrostatic protection structure suitable for a low-voltage circuit. The ESD electrostatic protection structure adopts a mode that an NPN triode with a floating layered base region structure is used for assisting in triggering an SCR to discharge forward ESD current and a PN junction diode to discharge negative ESD current; the NPN triode with the floating layered base region structure comprises an N + active region I, a P-type ESD injection region, a P well I and an N + active region II, the first N + active region and the second N + active region are a collector region and an emitter region of the NPN triode respectively, the base region is composed of a P-type ESD injection region and a first P well, the P-type ESD injection region is located below the first N + active region, and the base region is of a floating layered structure. The ESD protection structure is provided with a bidirectional rapid ESD current discharge path to the ground, so that the SCR trigger voltage is reduced.

Integrated circuit devices including a bipolar junction transistor (BJT) and / or a P-N junction diode are provided. The integrated circuit devices may include a first stack including first and second semiconductor regions that are spaced apart from each other in a horizontal direction and have a first conductivity type and a plurality of nano-semiconductor layers that are stacked in a vertical direction and are between the first and second semiconductor regions. The plurality of nano-semiconductor layers each have a second conductivity type, and the first semiconductor region may include a side surface facing the plurality of nano-semiconductor layers. The integrated circuit device may also include a vertical semiconductor layer having the second conductivity type and a conductive contact that contacts the plurality of nano-semiconductor layers. The vertical semiconductor layer may contact the side surface of the first semiconductor region and the plurality of nano-semiconductor layers.

The invention discloses a silicon controlled electrostatic protection device and a preparation method thereof, a metal block is arranged on the surface of a second N well and is in Schottky contact with the metal block, so that the second N well and the metal block form a Schottky diode, and an N + injection region in the second N well serves as a cathode of the silicon controlled electrostatic protection device. The P + injection region and the first N well form a PN junction diode, and the P + injection region is used as an anode of the silicon controlled electrostatic protection device, so that the PN junction diode and the Schottky diode form a trigger path of the silicon controlled electrostatic protection device, and the characteristics of low forward conduction voltage and fast conduction time and speed of the Schottky diode are utilized; the trigger voltage of the silicon controlled electrostatic protection device is effectively reduced, the failure current is improved, the latch-up effect can be effectively avoided under the ultra-low working voltage, and meanwhile the high protection level is achieved.

The invention provides a semiconductor device preparation method and a semiconductor device, and relates to the technical field of semiconductor manufacturing, and the method comprises the steps: generating an N-type injection region on a P-type substrate in a wafer marking region, forming a contact hole in the surface of the N-type injection region, and enabling the N-type injection region and the P-type substrate to form a PN junction diode; generating a first metal layer on the surface of the N-type injection region; sequentially forming metal layers of a multi-layer metal grid structure on the first metal layer according to the number of the metal layers of the chip, wherein the adjacent metal layers are electrically connected with each other through through holes; and generating a passivation layer on the surface of the outermost metal layer to obtain the semiconductor device. Wherein the metal layer, the contact hole and the N-type injection region jointly form an antenna structure, and are safely grounded through a PN junction diode. By adopting the semiconductor device preparation method and the semiconductor device, the problems that charges are easy to accumulate and destructive electric arcs are generated in the wafer marking area manufacturing process are solved, the low-resistance discharge of the charges is realized, and the electric arc damage is effectively prevented.

The application relates to a trench gate MOSFET integrated with positive and negative asymmetric gate-source ESD protection, which comprises a drain, a substrate, an epitaxial layer and a source arranged in sequence from the lower right to the upper; a plurality of first grooves and a second groove formed on the surface of the epitaxial layer, all the first grooves are distributed in the source region, and the second groove is located in the gate welding area; the surface of the epitaxial layer is formed with a P well area, a P+ area and an N+ area, the P well area is located below the P+ area and the N+ area, and the P+ area and the N+ area are in contact with the source. The application makes full use of the structural characteristics of the trench gate MOSFET device, constructs the n-polySi / p-SiC heterojunction diode and the p-SiC / n-SiCPN junction diode with asymmetric breakdown voltage between the gate and the source of the device, connects the two voltage stabilizing diodes in series, simply and efficiently realizes the ESD protection structure integrated between the gate and the source, and meets the asymmetric requirement of the SiC MOSFET device opening and closing driving protection voltage.

The invention relates to a gallium oxide MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) structure with a p-type buried layer and a preparation method of the gallium oxide MOSFET structure. The gallium oxide MOSFET structure consists of MOSFET regions and heterojunction diode regions which are alternately arranged along the transverse direction, the MOSFET region comprises a drain metal layer, a highly-doped n-type gallium oxide substrate, a lightly-doped n-type gallium oxide epitaxial layer, a current barrier layer, a highly-doped n-type gallium oxide epitaxial layer, a p-type semiconductor layer, a gate dielectric layer, a gate metal layer, an oxide dielectric layer and a source metal layer; a drain electrode metal layer, a highly-doped n-type gallium oxide substrate, a lightly-doped n-type gallium oxide epitaxial layer, a p-type semiconductor layer and a source electrode metal layer are expanded on the left side and the right side of the MOSFET region to form a drain electrode metal layer, a highly-doped n-type gallium oxide substrate, a lightly-doped n-type gallium oxide epitaxial layer, a p-type semiconductor layer and a source electrode metal layer of the heterojunction diode region. According to the gallium oxide vertical field effect transistor, advanced breakdown of a gate medium of a device can be improved, the blocking characteristic of the gallium oxide vertical field effect transistor is enhanced, and higher voltage resistance and lower reverse power consumption are achieved.

The invention discloses a PN-junction-free magnetic control one-way conduction rectifying device, aims to solve the technical problem of reducing the loss of the rectifying device, and adopts the following technical scheme that the PN-junction-free magnetic control one-way conduction rectifying device is provided with an N-type semiconductor silicon wafer, the N-type semiconductor silicon wafer is divided into three areas along the Z-axis direction: a low-resistance area, a transition area and a high-resistance area, compared with the prior art, an N-type semiconductor is divided into a high resistance area and a low resistance area to replace a traditional PN junction type diode, a manufactured rectifying device with a one-way conduction function abandons PN junctions on a main current loop, and therefore the rectifying diode does not have PN junction loss. The design of the power supply circuit does not have the scurf of a rectification part, PN junction loss, complexity of a synchronous rectification circuit and heat dissipation are not considered, the cost is reduced, the size is reduced, and the conversion efficiency of the power supply is greatly improved while the circuit is simplified.

This invention discloses a Schottky-PN junction diode based on cubic boron nitride (c-BN) single crystal material. The Schottky-PN junction diode comprises a c-BN crystal, an ITO thin film, and an Au electrode. An ITO thin film and an Au electrode are deposited on both sides of the c-BN crystal, and then the Au is soldered to In as an external conductor. The Au / c-BN / ITO Schottky-PN junction diode has an ideality factor of 25.15 and a turn-on voltage of 5V. This invention provides a framework for the fabrication and analysis of electronic devices based on c-BN single crystals.

A semiconductor structure includes a semiconductor substrate of a first conductivity type. The semiconductor substrate can have an upper surface and a bottom surface. The semiconductor substrate can be made of polycrystalline silicon carbide. The semiconductor structure can further include a drift region of the first conductivity type located on the upper surface of the semiconductor substrate. The semiconductor structure can further include a first region of the upper surface of the semiconductor substrate including a formation region of a transistor, and a second region of the upper surface of the semiconductor substrate, adjacent to the first region, including a formation region of a Schottky barrier diode.

The application discloses a kind of based on van der waals contact vertical p-n junction diode and preparation method, semiconductor device.The two-dimensional material vertical p-n junction diode includes metal top electrode, p-type two-dimensional material, n-type two-dimensional material and bottom electrode from top to bottom vertically stacked, wherein, the material between adjacent two layers is formed by van der waals force van der waals contact, so that the material of adjacent two layers mutually adhere and do not fall off.Based on the interface of vertical p-n junction diode of van der waals contact is flat and has no defect and lattice damage, avoid the damage of traditional evaporation method to two-dimensional material lattice, make that the schottky barrier and tunneling current caused by fermi pinning in device significantly reduce, to greatly improve the rectification performance of the device.The application solves the technical problem that existing two-dimensional material vertical p-n junction device has schottky barrier and larger tunneling current.

This invention provides a three-dimensional SiC superjunction diode and its fabrication method. The diode comprises a p+ type SiC epitaxial layer arranged in multiple spaced hemispheres, with an n+ type SiC epitaxial layer deposited on top. An n+ type electron transport layer is positioned between two hemispheres on the left side of the diode and located inside the n+ type SiC epitaxial layer. A field oxide passivation layer is deposited on the right side of the n+ type SiC epitaxial layer. A groove is located at the center of each hemisphere, directly opposite the anode PAD. This invention utilizes an annealing and reflow process with an alkaline earth-doped silicon oxide mask to achieve the three-dimensional structure etching mask, solving the problem of realizing a three-dimensional superjunction structure. This results in a three-dimensional superjunction structure with multiple hemispheres formed by the p+ type SiC epitaxial layer. The superjunction diode fabricated based on this structure exhibits superior voltage-resistance balance and can achieve lower resistance under the same voltage level.

A transient voltage suppression device includes a first strip of semiconductor regions and a second strip of semiconductor regions, a first portion of the semiconductor regions in the first strip and the second strip forming a thyristor, a second portion of the semiconductor regions in the first strip and the second strip forming a P-N junction diode, the first strip and the second strip defining a current conduction region between the strips; the first strip including a first doped region of a first conductivity type, and a second doped region of a second conductivity type; and the second strip including a first doped region of the second conductivity type, and a second doped region of the first conductivity type. The transient voltage suppression device of the present invention achieves low capacitance at the protected node. The transient voltage suppression device is suitable for protecting data pins of an integrated circuit, particularly when the data pins are used in high speed device applications.

The embodiment of the application provides a multifunctional diode piezoelectric sensor, a preparation method and a wearable device, which comprise a flexible substrate, a metal top electrode and a metal oxide conductive bottom electrode, the metal top electrode and the metal oxide conductive bottom electrode are made on the flexible substrate; the multifunctional diode piezoelectric sensor has a P-N junction diode structure, the P-N junction diode structure is between the metal top electrode and the metal oxide conductive bottom electrode; an N-type layer of the P-N junction diode structure is below a P-type layer of the P-N junction diode structure; the N-type layer of the P-N junction diode structure is a semiconductor piezoelectric material, the P-type layer of the P-N junction diode structure is an organic semiconductor; and a PET passivation layer is packaged on the upper surface of the P-type layer. The piezoelectric performance is good, the detection mode has high sensitivity, and the detection range is wide; energy collection can be performed at the same time of detection, and an external power supply is not needed.

A microdisplay comprising a light-emitting OLED stack on top of a silicon-based backplane having individually addressable pixels and control circuitry, wherein the light-emitting OLED stack has three or more OLED cells between a top electrode and a bottom electrode; and the control circuitry of the silicon-based backplane comprises at least two transistors, wherein the channels of the at least two transistors are connected in series to an external power supply V DD Between the bottom electrode of the OLED stack. The light-emitting OLED stack preferably has a Vth of at least 7.5 V or higher. The control circuit may include a protection circuit consisting of a p-n junction diode, preferably a bipolar junction transistor.

The present disclosure generally relates to junction diode isolation in an integrated circuit die. In an example, a semiconductor device includes a diode and a transistor. The diode is in a semiconductor substrate. The diode includes an anode region, an n-type well, a cathode region, and an n-type buried layer each in the semiconductor substrate. The cathode region is in the n-type well. The n-type buried layer extends from the n-type well laterally towards the anode region. The transistor includes a source region and a drain region in the semiconductor substrate. The source and drain regions are between the anode and cathode regions. A lateral distance is between the cathode region and a lateral edge of the n-type buried layer proximate the anode region. The lateral distance is parallel to a channel length of the transistor. The lateral distance decreases from proximate the transistor to distal from the transistor.

The invention discloses a gallium oxide heterojunction diode with a vertical structure and a preparation method. The gallium oxide heterojunction diode comprises a gallium oxide epitaxial wafer; the P-type oxide is located in the middle area of the upper surface of the gallium oxide epitaxial wafer; the two sides of the P-type oxide are of an arc-shaped structure, and the curvature radius of the arc-shaped structure is smaller than 3 microns. The SiO2 field plates are located on the two sides of the P-type oxide and make contact with the P-type oxide; the anode electrode is located on the P-type oxide and part of the SiO2 field plate; and the cathode electrode is positioned on the lower surface of the gallium oxide epitaxial wafer. According to the device structure designed by the invention, reverse leakage current is effectively inhibited, the breakdown voltage of the device is effectively improved, and the performance and reliability of the device are greatly improved.

To provide a semiconductor device that operates as a diode without being affected by negative potential.SOLUTION: A semiconductor device 1 includes a P-type substrate 10 to which a ground potential is supplied, a first PN junction diode D1, a first P-type well 31, a first N-type well 21, and an N-type well 40 for circuit elements. The first P-type well 31 is provided with a first PN junction diode D1, and the cathode of the first PN junction diode D1 is connected via a wiring layer. The first N-type well 21 is provided in the P-type substrate 10, and the first P-type well 31 is provided with a first constant potential. The N-type well 40 for circuit elements is provided in the P-type substrate 10, and a negative potential lower than the ground potential is supplied.SELECTED DRAWING: Figure 1

The invention provides a high-temperature-resistant accelerometer servo circuit which comprises a voltage stabilizer unit, an error processing unit and a power amplification unit which are integrally integrated, an SMIC180BCD process is adopted by an integrated chip, a transistor in the integrated chip is a transistor of a deep well isolation structure, and the high-temperature-resistant accelerometer servo circuit comprises a high-temperature-resistant accelerometer servo circuit and a high-temperature-resistant accelerometer servo circuit. A dynamic power consumption management module is added in the integrated chip to adapt to an extreme high-temperature environment, and all components of a servo circuit in the integrated chip are welded on a PCB (Printed Circuit Board) made of a polyimide material by utilizing high-temperature soldering tin; the resistor in the integrated chip adopts a high-temperature stable polycrystalline silicon resistor, the capacitor adopts an MIM capacitor, and the diode adopts a Schottky diode or a high-temperature optimized PN junction diode, so that the leakage current at high temperature is reduced. According to the technical scheme, the technical problem that in the prior art, a high-temperature-resistant accelerometer servo circuit in China is widely applied to the temperature within 175 DEG C and cannot meet the high-temperature working requirement of a petroleum deep well while drilling is solved.

The present disclosure presents an integrated circuit (IC) device comprising a transistor and a circuit, as well as a method for fabricating such an IC device. The transistor is constructed in layers formed in or on top of a semiconductor substrate and has a polysilicon element located near a feature of the transistor. The circuit has two connections to the polysilicon element and is designed to detect a temperature-dependent characteristic of the polysilicon element. The transistor may also, or alternatively, have oppositely doped sections of the semiconductor substrate forming a junction diode. The circuit may also, or alternatively, have connections to the oppositely doped substrate sections and may be designed to detect a temperature-dependent characteristic of the junction diode.

The invention relates to a silicon carbide MOSFET with an integrated polysilicon silicon carbide heterojunction diode. A semiconductor structure includes a semiconductor substrate of a first conductivity type. The semiconductor substrate may have an upper surface and a bottom surface. The semiconductor substrate may be made of polycrystalline silicon carbide. The semiconductor structure may also include a drift region of the first conductivity type on the upper surface of the semiconductor substrate. The semiconductor structure may further include a first region of an upper surface of the semiconductor substrate, the first region including a formation region of a transistor, and a second region of the upper surface of the semiconductor substrate, the second region being adjacent to the first region and including a formation region of a Schottky barrier diode.