1962 results about "Block layer" patented technology

An organic electroluminescent element comprising a light emission layer and a hole blocking layer adjacent to the light emission layer, wherein, (i) the light emission layer contains a compound having a specified partial structure and having a molecular weight of not more than 1700; and (ii) the hole blocking layer contains a derivative selected from the group consisting of a styryl derivative, a boron derivative and a carboline derivative.

A method for fabricating, a vertical channel type nonvolatile memory device includes: alternately forming a plurality of sacrificial layers and a plurality of interlayer dielectric layers over a semiconductor substrate; etching the sacrificial layers and the interlayer dielectric layers to form a plurality of first openings for channel each of which exposes the substrate; filling the first openings to form a plurality of channels protruding from the semiconductor substrate; etching the sacrificial layers and the interlayer dielectric layers to form second openings for removal of the sacrificial layers between the channels; exposing sidewalls of the channels by removing the sacrificial layers exposed by the second openings; and forming a tunnel insulation layer, a charge trap layer, a charge blocking layer, and a conductive layer for gate electrode on the exposed sidewalls of the channels.

A laser diode, grown on a miscut nonpolar or semipolar substrate, with lower threshold current density and longer stimulated emission wavelength, compared to conventional laser diode structures, wherein the laser diode's (1) n-type layers are grown in a nitrogen carrier gas, (2) quantum well layers and barrier layers are grown at a slower growth rate as compared to other device layers (enabling growth of the p-type layers at higher temperature), (3) high Al content electron blocking layer enables growth of layers above the active region at a higher temperature, and (4) asymmetric AlGaN SPSLS allowed growth of high Al containing p-AlGaN layers. Various other techniques were used to improve the conductivity of the p-type layers and minimize the contact resistance of the contact layer.

A group III nitride semiconductor light emitting device according to the present invention includes an immediate layer formed of Al_xGa_1-x-yIn_yN (0<x<1, 0<y<1, x+y<1) between an active layer and a cladding layer and an electron blocking layer formed of p-type group III nitride semiconductor having a smaller electron affinity than that of the intermediate layer so as to be in contact with the intermediate layer. The semiconductor light emitting layer may be a laser diode or a LED.

A semiconductor memory device includes a semiconductor substrate, a tunnel insulating layer, charge trap layer, and a blocking layer. The tunnel insulating layer is on the semiconductor substrate. The charge trap layer is on the tunnel insulating layer and includes at least one pair of a first nitride layer with a higher trap density of holes than electrons and a second nitride layer with a higher trap density of electrons than holes. The blocking layer is on the charge trap layer opposite to the tunnel insulating layer. The first nitride layer may include silicon rich nitride, which may have a ratio of silicon to nitride of greater than 1 and less than or equal to 2. The second nitride layer may include aluminum nitride which may have a hexagonal crystalline structure.

A device having thin-film transistor (TFT) floating gate memory cell structures is provided. The device includes a substrate, a dielectric layer on the substrate, and one or more source or drain regions being embedded in the dielectric layer. the dielectric layer being associated with a first surface. Each of the one or more source or drain regions includes an N⁺ polysilicon layer on a diffusion barrier layer which is on a first conductive layer. The N⁺ polysilicon layer has a second surface substantially co-planar with the first surface. Additionally, the device includes a P⁻ polysilicon layer overlying the co-planar surface and a floating gate on the P⁻ polysilicon layer. The floating gate is a low-pressure CVD-deposited silicon layer sandwiched by a bottom oxide tunnel layer and an upper oxide block layer. Moreover, the device includes at least one control gate made of a P⁺ polysilicon layer overlying the upper oxide block layer. A method of making the same memory cell structure is provided and can be repeated to integrate the structure three-dimensionally.

A non-volatile memory device includes a channel layer vertically extending from a substrate, a plurality of inter-layer dielectric layers and a plurality of gate electrodes that are alternately stacked along the channel layer, and an air gap interposed between the channel layer and each of the plurality of gate electrodes. The non-volatile memory device may improve erase operation characteristics by suppressing back tunneling of electrons by substituting a charge blocking layer interposed between a gate electrode and a charge storage layer with an air gap, and a method for fabricating the non-volatile memory device.

An implementing mode of the invention provides an improved technology for depositing materials containing tungsten. The technology utilizes an infusion technology and a gaseous phase deposition technology, such as atomic layer deposition (ALD), to provide tungsten-containing materials with obviously improved surface evenness and yield. In one implementing mode, a method for forming tungsten-containing materials on a substrate is provided. The method comprises deposing a substrate, which contains a bottom coating deposited thereon, in a technological chamber; exposing the substrate orderly in a precursor of tungsten and reducing gases so as to deposit a tungsten nucleation layer on the bottom coating, during the ALD technology; and depositing a tungsten block layer on the tungsten nucleation layer. The invention is characterized in that the reducing gases comprise a hydrogen gas/hydride flow ratio of 40:1, 100:1, 500:1, 800: 1, 1000:1 or more, and comprise hydride such as diborane, silicane or silicoethane.

A photoelectric conversion element comprises a photoelectric conversion section that includes: a pair of electrodes; and a photoelectric conversion layer disposed between the pair of electrodes, wherein the photoelectric conversion section further comprises between one of the pair of electrodes and the photoelectric conversion layer a first charge-blocking layer that restrains injection of charges from the one of the electrodes into the photoelectric conversion layer when a voltage is applied to the pair of electrodes, and the first charge-blocking layer comprises a plurality of layers.

Non-volatile memory devices and arrays are described that utilize reverse mode non-volatile memory cells that have band engineered gate-stacks and nano-crystal charge trapping in EEPROM and block erasable memory devices, such as Flash memory devices. Embodiments of the present invention allow a reverse mode gate-insulator stack memory cell that utilizes the control gate for programming and erasure through a band engineered crested tunnel barrier. Charge retention is enhanced by utilization of high work function nano-crystals in a non-conductive trapping layer and a high K dielectric charge blocking layer. The band-gap engineered gate-stack with symmetric or asymmetric crested barrier tunnel layers of the non-volatile memory cells of embodiments of the present invention allow for low voltage tunneling programming and erase with electrons and holes, while maintaining high charge blocking barriers and deep carrier trapping sites for good charge retention.

Junction diodes or MOS devices fabricated in standard FinFET technologies can be used as program selectors or One-Time Programmable (OTP) element in a programmable resistive device, such as interconnect fuse, contact/via fuse, anti-fuse, or emerging nonvolatile memory such as MRAM, PCRAM, CBRAM, or RRAM. The MOS or diode can be built on at least one fin structure or at least one active region that has at least one first active region and a second active region. The first and the second active regions can be isolated by a dummy MOS gate or silicide block layer (SBL) to construct a diode.

A non-volatile semiconductor memory device comprises a substrate including a source region, a drain region and a channel region provided between the source region and the drain region with a gate stack located above the channel region with a metal gate located above the gate stack. The metal gate is comprised of a metal having a specific metal work function relative to a composition of a layer of the gate stack that causes electrons to travel through the entire thickness of the blocking layer via direct tunneling. The gate stack preferably comprises a multiple layer stack selected from a group of multiple layer stacks consisting of: ONO, ONH, OHH, OHO, HHH, or HNH, where O is an oxide material, N is SiN, and H is a high κ material.

To increase the detection sensitivity of a touch panel, provide a thin touch panel, provide a foldable touch panel, or provide a lightweight touch panel. A display element and a capacitor forming a touch sensor are provided between a pair of substrates. Preferably, a pair of conductive layers forming the capacitor each have an opening. The opening and the display element are provided to overlap each other. A light-blocking layer is provided between a substrate on the display surface side and the pair of conductive layers forming the capacitor.

A display apparatus is provided that prevents shortening of the life of the luminescent elements and has a superior contrast ratio. The display apparatus is composed by forming a plurality of luminescent elements on a substrate and providing bank sections between each of the luminescent elements. The bank sections are formed from a first bank layer located on the side of the substrate and a second bank layer formed on the first bank layer. A light blocking layer is then provided between the first bank layer and the second bank layer.

The invention provides an organic electroluminescent material and an organic electroluminescent device containing the material. The material has a structural formula shown in the description. The material provided by the invention is used as a hole transporting layer, a hole injecting layer or an electron blocking layer of the organic electroluminescent device, so that the organic electroluminescent device has a lower driving voltage, higher luminous efficiency, and a better service life.

A method for fabricating a vertical channel type nonvolatile memory device includes forming alternately a plurality of interlayer dielectric layers and a plurality of conductive layers over a substrate, forming a trench having a plurality of recesses on a surface of the trench by etching the plurality of interlayer dielectric layers and a plurality of conductive layers, wherein the plurality of recesses are formed at a certain interval on the surface of the trench, forming a charge blocking layer over a plurality of surfaces of the plurality of recesses, forming a charge storage layer over the charge blocking layer for filling a plurality of the remaining recesses with a charge storage material, forming a tunnel dielectric layer to cover the charge storage layer, and forming a vertical channel layer by filling the remaining trench.

A band gap engineered, charge trapping memory cell includes a charge trapping element that is separated from a metal or metal compound gate, such as a platinum gate, by a blocking layer of material having a high dielectric constant, such as aluminum oxide, and separated from the semiconductor body including the channel by an engineered tunneling dielectric. Fast program and erase speeds with memory window as great as 7 V are achieved.

A laminated body is formed by alternately laminating a plurality of dielectric films and electrode films on a silicon substrate. Next, a through hole extending in the lamination direction is formed in the laminated body. Next, a selective nitridation process is performed to selectively form a charge layer made of silicon nitride in a region of an inner surface of the through hole corresponding to the electrode film. Next, a high-pressure oxidation process is performed to form a block layer made of silicon oxide between the charge layer and the electrode film. Next, a tunnel layer made of silicon oxide is formed on an inner side surface of the through hole. Thus, a flash memory can be manufactured in which the charge layer is split for each electrode film.

A solid-state imaging device includes an array of pixels, each pixel includes: a pixel electrode; an organic layer; a counter electrode; a sealing layer; a color filter; a readout circuit; and a light-collecting unit as defined herein, the photoelectric layer contains an organic p type semiconductor and an organic n type semiconductor, the organic layer further includes a charge blocking layer as defined herein, an ionization potential of the charge blocking layer and an electron affinity of the organic n type semiconductor in the photoelectric layer has a difference of at least 1 eV, and the sealing layer includes a first sealing sublayer formed by atomic layer deposition and a second sealing sublayer formed by physical vapor deposition and containing one of a metal oxide, a metal nitride, and a metal oxynitride.

An OLED device comprises, in sequence, an anode, a light-emitting layer that comprises a phosphorescent light-emitting organometallic compound, a hole-blocking layer, and a cathode, and between the hole-blocking layer and the cathode, a further layer containing: a) a first compound that has the lowest LUMO value of the compounds in the layer, the amount being greater than or equal to 10% by volume and less than 100% by volume of the layer; b) at least one second compound that is a low voltage electron transport material, exhibiting a higher LUMO value than the first compound, the total amount of said compound(s) being less than or equal to 90% by volume and more than 0% by volume of the layer. Such a device provides improved drive voltage.

A triplet light emitting device which has high efficiency and improved stability and which can be fabricated by a simpler process is provided by simplifying the device structure and avoiding use of an unstable material. In a multilayer device structure using no hole blocking layer conventionally used in a triplet light emitting device, that is, a device structure in which on a substrate, there are formed an anode, a hole transporting layer constituted by a hole transporting material, an electron transporting and light emitting layer constituted by an electron transporting material and a dopant capable of triplet light emission, and a cathode, which are laminated in the stated order, the combination of the hole transporting material and the electron transporting material and the combination of the electron transporting material and the dopant material are optimized.

An organic electroluminescence device includes an anode, an emitting layer, a blocking layer, an electron injecting layer, and a cathode in sequential order. The emitting layer includes a host and dopant. The blocking layer includes an aromatic heterocyclic derivative. A triplet energy E^T_b (eV) of the blocking layer is larger than a triplet energy E^T_h (eV) of the host. An affinity A_b (eV) of the blocking layer and an affinity A_b (eV) of the electron injecting layer satisfy a relationship of A_e−A_b<0.2.

A light source comprises an organic light-emitting device, which emits radiation having a first spectrum, and a phosphor layer, which absorbs a portion of the light emitted by the organic light-emitting layer and which emits light having a second spectrum. The organic light-emitting device comprises an organic light-emitting layer disposed between a pair of electrodes, and at least a charge-blocking layer disposed between the organic light-emitting layer and one of the electrodes. The phosphor layer typically absorbs less than all of the light emitted by the organic light-emitting layer and typically covers the entire organic light-emitting device. The light emitted by the organic light-emitting layer is mixed with the light emitted by the phosphor layer to produce light having a third spectrum.

The invention belongs to the surface patterning microstructure construction technique, which relates to a method for constructing a microstructure with anti-reflection performance on a foundation base by combining the self-assembly technique with the reactive ion beam etching technique. The method is to take monolayer polymeric micro-spheres, silicon dioxide micro-spheres and nano-particles of metal or metal oxides as a barrier layer and implement the RIE etching to the foundation base, then an approximate cone-shaped microstructure is constructed on the foundation base, and the structure has extreme high anti-reflection performance, thereby effectively improving the light energy utilization rate, reducing the interference of veiling glare in an optical system, increasing the optical transmittance, and further improving the sensitivity and stability of the optical system, and the method can be used for constructing large-area anti-reflection structures. The method of the invention has advantages of simple operation, changeable foundation base, strong applicability, good repeatability, low cost, high efficiency, adjustable anti-reflective applied wavelength and conformity to industrialized standards, and can be used for making photoelectric devices such as solar batteries and white light sensors.

Polysilicon diodes fabricated in standard CMOS logic technologies can be used as program selectors for a programmable resistive device, such as electrical fuse, contact/via fuse, anti-fuse, or emerging nonvolatile memory such as MRAM, PCM, CBRAM, or RRAM. The diode can be constructed by P+/N+ implants on a polysilicon as a program selector. By applying a high voltage to a resistive element coupled to the P terminal of a diode and switching the N terminal of a diode to a low voltage for proper time, a current flows through a resistive element may change the resistance state. On the polysilicon diode, the spacing and doping level of a gap between the P+ and N+ implants can be controlled for different breakdown voltages and leakage currents. The Silicide Block Layer (SBL) can be used to block silicide formation on the top of polysilicon to prevent shorting. If the resistive element is a polysilicon electrical fuse, the fuse element can be merged with the polysilicon diode in one piece to save area.

Polysilicon diodes fabricated in standard CMOS logic processes can be used as program selectors for One-Time Programmable (OTP) devices, such as electrical fuse, contact/via fuse, contact/via anti-fuse, or gate-oxide breakdown anti-fuse, etc. The OTP device has an OTP element coupled to a diode in a memory cell. The diode can be constructed by P+/N+ implants on a polysilicon as a program selector. By applying a high voltage to an OTP element coupled to the P-terminal of a diode and switching the N-terminal of a diode to a low voltage for suitable duration of time, a current flows through the OTP element may change the resistance state. On the polysilicon diode, the spacing and doping level of a gap between the P- and N-implants can be controlled for different breakdown voltages and leakage currents. The Silicide Block Layer (SBL) can be used to block silicide formation on the top of polysilicon to prevent shorting. If the OTP element is a polysilicon electrical fuse, the fuse element can be merged with the polysilicon diode in one piece to save area.

A photoelectric conversion device includes, in the following order: a first electrode; an electron blocking layer; a photoelectric conversion layer containing a merocyanine dye; a hole blocking layer; and a transparent electrode as a second electrode, and an absorption maximum wavelength in a thin film absorption spectrum of the photoelectric conversion layer containing a merocyanine dye is within a range of from 400 to 520 nm.

Embodiments of programmable memory cells using a plurality of diodes as program selectors are disclosed for those memory cells that can be programmed based on direction of current flow. These memory cells are MRAM, RRAM, CBRAM, or other memory cells that have a programmable resistive element coupled to the P-terminal of a first diode and to the N-terminal of a second diode. At least one of the diodes can be a polysilicon diode fabricated using standard CMOS processes. The polysilicon diode can be constructed by P+/N+ implants on a polysilicon substrate as a program selector. The polysilicon diode can be constructed by P+/N+ implants on a polysilicon as a program selector. By applying a high voltage to a resistive element and switching the N-terminal of the first diode to a low voltage while disabling the second diode, a current flowing through the memory cell can change the resistance into one state. Similarly, by applying a low voltage to a resistive element and switching the P-terminal of the second diode to a high voltage while disabling the first diode, a current flowing through the memory cell can change the resistance into another state. On the polysilicon diode, the spacing and doping level of a gap between the P- and N-implants can be controlled for different breakdown voltages and leakage currents. A Silicide Block Layer (SBL) can be used to block silicide formation on the top of polysilicon to prevent shorting.

Electro-Static Discharge (ESD) protection using at least one ring-shape diode is disclosed. The ring-shape diode can be constructed from polysilicon, active region body on insulated substrate, or junction diode on silicon substrate. The diodes can have a first type of implant in an outer ring and a second type of implant in an inner ring to serve as two terminals of a diode coupled through contacts, vias, or metals. The two types of implant ring regions are separated with an isolation structure. The isolation can be LOCOS, STI, dummy gate, or silicide block layer (SBL). The ESD structure has at least a ring-shape diode with a first terminal coupled to an I/O pad and the second terminal coupled to a first supply voltage. The contours of the ring-shape diode can be circles, polygons, or other shapes. The ring-shape ESD structures can be multiple and be constructed in concentric manner.

An array substrate of a display device, the array substrate: a substrate having a first region and a second region spaced apart from the first region; a blocking layer located on the substrate; a first electrode located on the blocking layer in the second region; an insulating film located on the blocking layer to cover the first electrode; a second electrode located on the insulating film to overlap the first electrode; and a third electrode overlapping the first electrode between the substrate and the blocking layer. Accordingly, it is possible to reduce an area that is occupied by a storage capacitor in a pixel region and to achieve high luminance by increasing the aperture ratio, by providing a structure and method of increasing a storage capacitance of the same area.