120 results about "Block layer" patented technology

A method for manufacturing a semiconductor device includes: forming a first conductive interconnect which penetrates a dielectric layer disposed over a substrate; forming a patterned dielectric layer on the dielectric layer, the patterned dielectric layer being formed with a trench and the first conductive interconnect being exposed from the trench; selectively forming a blocking layer to cover the first conductive interconnect, the blocking layer being formed using an acidic solution including a blocking material; selectively forming a barrier material layer on the dielectric layer and the patterned dielectric layer; removing the blocking layer; forming a conductive material layer on the barrier material layer; and removing a portion of the conductive material layer and a portion of the barrier material layer to form a second conductive connected to the first conductive interconnect.

Embodiments of the present application provide a semiconductor structure manufacturing method and a semiconductor structure. The manufacturing method comprises: providing a substrate; the substrate comprises a substrate, a dielectric structure on the substrate, and a blocking material layer on the dielectric structure; the dielectric structure comprises at least one dielectric layer; forming a first mask layer on the blocking material layer; the first mask layer comprises a first opening exposing a top surface of the blocking material layer; forming a second mask layer in the first opening, and removing the first mask layer; the second mask layer comprises a second opening exposing a top surface of the blocking material layer; using the second mask layer as a mask to pattern the blocking material layer, to form a blocking layer for patterning the dielectric structure; the blocking layer comprises a third opening exposing a top surface of the dielectric structure; the third opening has a size greater than that of the second opening.

This invention provides a GaN-based light-emitting diode epitaxial structure and its fabrication method. By introducing a Zn source as a surface activator throughout the growth process of the P-type AlGaN electron blocking layer, a P-type AlGaN electron blocking layer structure with a gradient distribution of Zn concentration along the direction of the P-type AlGaN electron blocking layer is constructed. Specifically, through the core role of the Zn surface activator and the innovative design of the Zn concentration gradient distribution, a smooth rise in the conduction band Ec and no loss of strong electron blocking capability are achieved, while ensuring that the valence band Ev is smooth and without spikes throughout and that hole injection is unimpeded throughout.

A photomask, a method of forming a pattern, a method of manufacturing a display device, and an electronic device are provided. The photomask includes a transparent substrate having a first surface and a second surface opposite each other, a first semi-transparent layer disposed on the first surface of the transparent substrate, a light-blocking layer disposed on the second surface of the transparent substrate, and a second semi-transparent layer disposed between the second surface of the transparent substrate and the light-blocking layer. The second semi-transparent layer has a transmittance higher than that of the first semi-transparent layer.

Methods and apparatus for substrate processing include: depositing a bulk layer of a dielectric material comprising a metal onto a device attached to a device substrate; depositing a graded layer of the dielectric material with a compositional gradient, onto the bulk layer; and depositing a bonding cap layer of the metal, having a purity of at least 99% by weight, onto the graded layer, wherein the graded layer has a dielectric gradient from substantially dielectric adjacent to the bulk layer to substantially conductive adjacent the bonding cap layer.

IC die package routing structures including a bulk layer of a first metal composition on an underlying layer of a second metal composition. The lower layer may be sputter deposited to a thickness sufficient to support plating of the bulk layer upon a first portion of the lower layer. Following the plating process, a second portion of the lower layer may be removed selectively to the bulk layer. Multiple IC die may be attached to the package with the package routing structures responsible for the transmission of high-speed data signals between the multiple IC die. The package may be further assembled to a host component that conveys power to the IC die package.

A display device includes a window, and a display module including a base layer including first and second areas, a first group of light-emitting elements the first area to be deactivated during a first operation mode, and activated during a second operation mode, a second group of light-emitting elements in the second area to be activated during the first and second operation modes, a first light-sensing element between the first and second groups, a first light-blocking layer defining a first opening corresponding to the first group, a second opening corresponding to the second group, and a third opening corresponding to the first light-sensing element, and a second light-blocking layer above the first light-blocking layer, apart from the first area in plan view, overlapping the second area, and defining a fourth opening corresponding to the second opening.

A semiconductor device and a manufacturing method thereof, the method comprising: providing a semiconductor substrate, the semiconductor substrate comprising an active region, a gate structure formed on the active region, and a gate sidewall formed on a sidewall of the gate structure; forming a metal silicide blocking layer; performing a first etching on the metal silicide blocking layer to form a field plate dielectric layer and a sidewall covering layer, the sidewall covering layer covering the gate sidewall; forming a metal silicide layer on a surface of the semiconductor substrate and the gate structure exposed by the metal silicide blocking layer remaining after the first etching; forming an interlayer dielectric layer; and performing a second etching to synchronously form a field plate contact hole and a shared contact hole, the field plate contact hole exposing part of the field plate dielectric layer, and the shared contact hole exposing part of the sidewall covering layer, the metal silicide layer on a top surface of the gate structure, and the metal silicide layer on a top surface of the active region. The application can increase the process window when multiple contact holes are etched together.

A display device according to an exemplary embodiment of the present disclosure includes a substrate in which an emission area and a non-emission area are divided and a plurality of sub-pixels are defined, a first electrode disposed in each of the plurality of sub-pixels, a bank disposed on an insulating layer above the substrate and exposing the first electrode through an opening, a trench formed by removing a partial area of the bank between the plurality of sub-pixels to expose the insulating layer, an organic layer disposed above the substrate on which the bank is provided, a charge blocking layer interposed in the organic layer in the trench, and a second electrode disposed on the organic layer.

A light receiving device includes a substrate including first and second areas, an element layer on the substrate and including a pixel defining film including first and second openings in the first and second areas, respectively, first and second light receiving areas respectively defined by the first and second openings, and an optical layer on the element layer and including a first light blocking layer and a light guide layer on the first light blocking layer. The first light blocking layer includes first light blocking patterns respectively including first transmission holes, the light guide layer includes first and second light guide patterns respectively including first and second light guide holes corresponding to the first and second openings, respectively. The first light guide hole overlaps the first opening in a plan view, and the second light guide hole is shifted with respect to the second opening in the plan view.

The present invention relates to an electronic device comprising at least at least two subpixels, where the subpixels comprise a common hole-transport layer c-HTL and different electron-blocking layers EBL1 and EBL2, where the interface charge density ICD at the interface of c-HTL / EBL1 and c-HTL / EBL2, fulfils specific criteria.

The present application relates to a kind of perovskite solar cells and its passivation method, the electron blocking layer is made of acyl chloride group derivative, on the one hand, the carbonyl group in acyl chloride group can be coordinated with the Pb 2+ Ion forms Lewis acid-base pair, thereby significantly reduce the defect state density of perovskite surface.Let go of group Cl ‑ Ion can increase the grain size of perovskite, improve the crystalline quality of perovskite layer.In addition, acyl chloride group and perovskite component reaction generates electron blocking layer cesium acetate, reduces the charge recombination at interface, while it can promote energy level gradient arrangement, effectively improve the separation and extraction capacity of carrier, successfully improve the photoelectric conversion efficiency and stability of carbon-based hole-free all-inorganic perovskite solar cell, and significantly reduce the hysteresis effect.The present application process is simple and has universality, is conducive to promoting the commercialization of perovskite, has wide market demand and application prospect.

The application discloses a kind of copolymer organic semiconductor devices based on isolation and interconnection and preparation method, including substrate, photoetching blocking layer, insulating isolation layer, N organic field effect transistor and N-1 interconnection line;Photoetching blocking layer includes isolation layer and inorganic dielectric layer;Isolation layer is opened with N longitudinal through isolation groove along length direction;Inorganic dielectric layer includes lower dielectric layer and upper dielectric layer;Lower dielectric layer is located in N isolation, and upper dielectric layer is laid on the top of isolation layer and lower dielectric layer;Each organic field effect transistor includes semiconductor layer, source, drain and gate;Semiconductor layer is laid in the isolation groove at the bottom of corresponding lower dielectric layer section, and its material is organic copolymer.The application effectively utilizes isolation groove and photoetching blocking layer, and the semiconductor layer of different semiconductor materials is wrapped and isolated, so as to realize the integration of different organic field effect transistors on the same substrate, and the organic field effect transistor can realize effective interconnection.

Embodiments of the disclosure include integrated circuit structures having source or drain dopant diffusion blocking layers. In an example, an integrated circuit structure includes a fin including silicon. A gate structure is over a channel region of the fin, the gate structure having a first side opposite a second side. A first source or drain structure is at the first side of the gate structure. A second source or drain structure is at the second side of the gate structure. The first and second source or drain structures include a first semiconductor layer and a second semiconductor layer. The first semiconductor layer is in contact with the channel region of the fin, and the second semiconductor layer is on the first semiconductor layer. The first semiconductor layer has a greater concentration of germanium than the second semiconductor layer, and the second semiconductor layer includes boron dopant impurity atoms.

The application discloses a high-hole-injection-efficiency LED epitaxial structure and a preparation method thereof, and relates to the technical field of semiconductor devices. The high-hole-injection-efficiency LED epitaxial structure comprises a substrate and an N-type semiconductor layer, a low-temperature stress release layer, a first confinement layer, a multi-quantum-well light-emitting layer, a second confinement layer, a low-temperature P-type semiconductor layer, an electron blocking layer and a high-temperature P-type semiconductor layer which are sequentially stacked on the substrate; the first confinement layer comprises periodically and alternately stacked first AlGaN layers and first GaN layers, and the Al component content of the first AlGaN layers changes in an increasing manner along an epitaxial direction; and the second confinement layer comprises periodically and alternately stacked second AlGaN layers and second InGaN layers, and the Al component content of the second AlGaN layers changes in a decreasing manner along the epitaxial direction. By adopting the application, the hole injection efficiency of the P-type semiconductor material can be improved, and the matching degree of the electron-hole concentration in the multi-quantum-well light-emitting layer can be improved, so that the light-emitting efficiency of the LED device is improved.

This application relates to a micro light-emitting device and its fabrication method. The device includes: a driving chip; a light-emitting layer disposed on one side of the driving chip, comprising a plurality of alternately distributed light-emitting units, the side of each light-emitting unit facing away from the driving chip including a light-emitting area; a light-blocking layer disposed on the side of the light-emitting layer facing away from the driving chip, comprising a plurality of alternately distributed first light-blocking units, the area between two adjacent first light-blocking units being a light-transmitting area, the light-transmitting area corresponding one-to-one with the light-emitting area; and a color conversion layer disposed on the side of the light-blocking layer facing away from the light-emitting layer, comprising a plurality of second light-blocking units and a plurality of color conversion units, the second light-blocking units corresponding to the first light-blocking units, the area between two adjacent second light-blocking units being a pixel area, and the color conversion units being disposed within the pixel area. The solution in this application can solve the problems of light crosstalk and light mixing in full-color displays, improving the color gamut and image quality during display.

A display apparatus is disclosed. The display apparatus includes a display panel including a first area and a second area, the first area including a transmissive portion configured to transmit light provided from an outside, the second area not including the transmissive portion; and a sensor overlapping the transmissive portion and configured to obtain electrical information based on information provided from the outside, wherein the display panel includes a thin film transistor layer including a plurality of transistors, a pixel definition layer defining an emission area of a plurality of pixels, and a light blocking layer on the pixel definition layer and defining the transmissive portion, and wherein the pixel definition layer in the first area covers at least a portion of the thin film transistor layer such that at least a portion of the light provided through the transmissive portion is blocked.

This invention discloses a bulk acoustic wave (BAW) device and its fabrication method. The BAW device includes: a substrate with a first groove on one side; a blocking layer located on the sidewall of the first groove and covering the entire sidewall of the first groove; a support structure located within the first groove; and a piezoelectric stacked structure located on one side of the substrate, specifically on the side of the support structure furthest from the substrate. This invention solves the problems of insufficient mechanical stability, susceptibility to external stress, and poor heat dissipation of traditional BAW devices.

The application relates to a second-order adjustable transistor with a time-domain programmable characteristic and a preparation method thereof. The transistor comprises an insulator substrate, a gate bottom electrode, a ferroelectric blocking layer, a floating gate layer, a tunneling layer, a channel layer and a source and a drain, wherein the blocking layer is a ferroelectric material layer with an electrically programmable polarization state. Through the coupling of the ferroelectric polarization effect and the floating gate charge capture mechanism, the Schottky barrier height at the floating gate interface is regulated, thereby changing the release dynamics of photo-generated carriers, realizing the adjustable relaxation time of photo-generated carriers in the millisecond to second range, and realizing the time-domain programmable regulation of multiple different time factors without the need of a continuous external bias voltage. The device breaks through the limitation of a single time factor of a neuromorphic device and is suitable for in-situ computing scenes such as multi-speed motion perception.

The disclosure provides a laser, a preparation method of the laser and an optical module, and relates to the technical field of optical elements, so as to meet the demand of the optical module for high-power lasers. The laser comprises a current blocking layer, and the current blocking layer comprises a P-InP blocking layer, an impurity freezing layer, a first N-InP blocking layer and a second N-InP blocking layer. The method comprises the following steps: introducing a first doping source into an epitaxial growth chamber to form the P-InP blocking layer on both sides of a BH mesa; stopping the introduction of the first doping source and reducing the temperature of the epitaxial growth chamber to a first preset temperature; introducing a second doping source into the epitaxial growth chamber, so that the second doping source penetrates into the surface at the top of the P-InP blocking layer, the top of the P-InP blocking layer is processed to form the impurity freezing layer, and the first N-InP blocking layer is formed above the impurity freezing layer; and the second N-InP blocking layer is formed above the first N-InP blocking layer.

A display device according to an example embodiment of the present inventive concept includes a first substrate, a gate line disposed on the first substrate and extending in parallel to a first direction, a storage electrode line disposed on the same layer as the gate line, a data line insulated from the gate line and the storage electrode line and extending in parallel to a second direction perpendicular to the first direction, a drain electrode disposed on the same layer as the data line and including an extension, a first electrode electrically connected to the drain electrode, a spacer disposed on the first electrode, a second substrate overlapping the first substrate, and a light blocking layer disposed on the second substrate and having an opening exposing the first electrode, a separation distance between the extension of the drain electrode and the data line along the first direction being 1 to 10 µm.

The application discloses a slow disk simulation method and device, equipment and medium, apply in hard disk fault simulation technical field, including: when the target function starts to execute, jump to the preset hook function through the preset jump instruction in the target function;The target function is the function of handling IO request in the block layer of the operating system kernel;The IO request is the IO request for the hard disk;The preset hook function is used to intercept the IO request, and the preset logic is used for delay injection. In this way, the function of handling IO request in the block layer of the operating system kernel is selected as the target function, the preset jump instruction and the hook function, the interception and delay injection of the IO request are realized, the slow disk simulation can be carried out for each type of hard disk, so as to meet the test demand of the slow disk detection mechanism.

A semiconductor structure is provided. The semiconductor structure includes a gate structure over a fin structure, and a source / drain structure in the fin structure and adjacent to the gate structure. The source / drain structure includes: a first epitaxial layer over the fin structure, a second epitaxial layer over the first epitaxial layer, and an epitaxial capping layer over the second epitaxial layer. The semiconductor structure also includes a silicide layer formed in contact with the source / drain structure. The silicide layer has a curved bottom surface, and the curved bottom surface of the silicide layer intersects with the second epitaxial layer and the epitaxial capping layer.

This invention provides a water-blocking optical film, a polarizer, and a display device. The water-blocking optical film provided in this invention includes a water-blocking layer and a first phase difference compensation layer stacked together. The water-blocking layer is made of a polymerizable composition.

This invention discloses a high-resolution quantum dot light-emitting device based on capillary self-assembly using a sacrificial layer and nanoimprinting, and its fabrication method. The method first prepares a hole injection layer and a hole transport layer on a substrate. A sacrificial layer and a charge blocking layer are then prepared on a PDMS soft stamp. A via array is formed on the charge blocking layer, and the sacrificial layer is pressed into the top of silicon pillars, forming a quantum dot light-emitting pixel array. Next, the PDMS stamp containing the quantum dot pixels is flipped over and hot-pressed onto the hole transport layer, and the sacrificial layer is removed by selective solvent dissolution. Finally, an electron transport layer and a top electrode are sequentially prepared on the structure to complete the construction of the QLED device. This invention utilizes a soft stamp and sacrificial layer process to achieve photolithography-free, high-precision, and damage-free quantum dot pixel patterning, effectively solving problems such as low resolution, pixel color mixing, and quantum dot damage in traditional processes. It is particularly suitable for fabricating high-resolution, full-color quantum dot light-emitting diodes.

An organic light emitting diode display according to an exemplary embodiment includes: a substrate; a first buffer layer on the substrate; a first semiconductor layer on the first buffer layer; a first gate insulating layer on the first semiconductor layer; a first gate electrode and a blocking layer on the first gate insulating layer; a second buffer layer on the first gate electrode; a second semiconductor layer on the second buffer layer; a second gate insulating layer on the second semiconductor layer; and a second gate electrode on the second gate insulating layer.

The application discloses an array substrate, a manufacturing method thereof and a touch display panel. The array substrate comprises a substrate, a scan line, a touch signal line and a plurality of touch electrodes arranged in sequence along a direction away from the substrate. A first insulating layer and an etching blocking layer are arranged between the scan line and the touch signal line. The etching blocking layer is arranged between the first insulating layer and the touch signal line. A second insulating layer is arranged between the touch signal line and the touch electrodes. A first contact hole penetrating through the second insulating layer is arranged in an intersection area between the scan line and the touch signal line. The touch electrodes are conductively connected with the touch signal line through the first contact hole. The etching blocking layer corresponds to the first contact hole. A projection area of the etching blocking layer on the substrate completely covers a projection area of the first contact hole on the substrate. The etching blocking layer for blocking the contact hole is arranged in the intersection area between the scan line and the touch signal line, so that the scan line is prevented from being continuously etched downward when the contact hole is etched.

The application provides a model setting method and system of a free report, and a readable storage medium. The model setting method of the free report comprises the following steps: acquiring a cell list, the cell list comprising a plurality of design cells; converting the design cells to obtain business cells; structurally processing the business cells to obtain design blocks; and sequentially processing cell information in the design blocks, and collecting cells on the same link together according to the cell information to form a design path. Through the technical scheme, the server adds the design block layer and the design path layer in the running time, the execution is clear in hierarchy, supports a more fine-grained business scenario, and is convenient for subsequent code maintenance and expansion.

An array substrate is provided. The array substrate includes an anode layer including a plurality of anodes on the base substrate, a respective anode being at least partially in a respective subpixel region; a carrier transport blocking layer on a side of the anode layer away from the base substrate, the carrier transport blocking layer at least partially blocking carrier transport; a pixel definition layer on a side of the carrier transport blocking layer away from the base substrate, the pixel definition layer defining subpixel apertures, a respective subpixel aperture exposing at least a portion of the respective anode; and an organic layer including at least a first portion in the respective subpixel region and on a side of the anode layer away from the base substrate.