917 results about "Block layer" patented technology

A GaN-based blue-green LED epitaxial structure, relating to the field of semiconductor photoelectric devices. The GaN-based blue-green LED epitaxial structure comprises a substrate, and a buffer layer, a dislocation regulation layer, a U-GaN layer, an N-GaN layer, a multi-quantum-well layer, an electron blocking layer and a P-GaN layer which are sequentially stacked on the substrate, wherein the dislocation regulation layer is of a periodic structure with the number of periods ranging from 2 to 10, and each period comprises a GaN layer and an Si-doped GaN layer that are sequentially stacked. The crystal quality of the epitaxial structure can be improved, thereby improving the light-emitting efficiency and the antistatic performance of the blue-green LED based on the epitaxial structure.

Embodiments of the present application relate to the technical field of display, and provide a display panel and a display device, for use in improving the wide-angle anti-peeping effect of the display panel. The display panel comprises: a substrate; a plurality of light-emitting elements located on one side of the substrate, wherein each of the light-emitting elements comprises a first light-emitting unit and a second light-emitting unit; a first light blocking layer located on the side of the first light-emitting unit distant from the substrate, wherein the first light blocking layer comprises a first opening; and a second light blocking layer located on the side of the first light blocking layer distant from the substrate, wherein the second light blocking layer comprises a second opening. In a direction perpendicular to the plane where the substrate is located, both the first opening and the second opening at least partially overlap the first light-emitting unit; and the area of the first opening is greater than that of the second opening, and the orthographic projection of the second light blocking layer on the plane where the substrate is located at least partially covers the edge of the first opening.

A display device includes a display area in which a plurality of first pixels and second pixels including a plurality of pixel electrodes spaced apart from each other are disposed, a first light blocking layer disposed in the display area and including a plurality of holes disposed to overlap the pixel electrodes, a plurality of color filters disposed on the first light blocking layer to correspond to the holes, and a second light blocking layer disposed on the color filter and disposed to correspond to the pixel electrodes of the second pixels, the first light blocking layer including a plurality of divided portions disposed around the holes of the second pixel and penetrating the first light blocking layer, and the color filters disposed in the second pixel and disposed to cover the hole of the first light blocking layer, where the divided portions are disposed to correspond to the holes.

The invention belongs to the technical field of solar cells, and particularly relates to a fluorinated biguanide salt synergistically passivated perovskite solar cell and a preparation method thereof. The method comprises the following steps: S1, coating the surface of a perovskite light absorption layer with a fluorinated biguanide hydrochloride solution to form a synergistic layer; coating the surface of the synergistic layer with a halogenated phenylethylamine solution to form a synergistic passivation layer; and S2, arranging an electron transport layer and a hole blocking layer on the surface of the passivation layer. According to the invention, the synergistic passivation layer is introduced in the preparation process of the perovskite solar cell. The introduction of the fluorinated biguanide salt passivation layer can modify the perovskite crystal and generate the low-dimensional perovskite at the crystal boundary, and the second passivation layer can interact with the low-dimensional perovskite structure, thereby further protecting the perovskite film, improving the interface of the perovskite light absorption layer and the electron transport layer, and improving the short-circuit current density, open-circuit voltage and cell efficiency of the cell.

The invention discloses a GaN-based blue-green light LED epitaxial structure and a preparation method thereof. The GaN-based blue-green light LED epitaxial structure comprises a substrate, and a buffer layer, a 3D layer, a U-GaN layer, an N-GaN layer, a multi-quantum well layer, an electron blocking layer and a P-GaN layer which are stacked on the substrate in sequence, the multi-quantum well layer comprises a shallow well transition layer, a high-temperature quantum well layer, a stress release layer and a low-temperature quantum well layer which are sequentially stacked, and the stress release layer comprises AlN layers and GaN layers which are periodically and alternately stacked. By implementing the invention, the luminous efficiency of the light-emitting diode under high current density can be effectively improved.

Semiconductor devices including one or more hydrogen-blocking layers are described. In one example, a semiconductor device comprises a semiconductor substrate including a source region, a gate region, a drain region, and a drain access region, where a heterojunction structure is disposed over the semiconductor substrate. The heterojunction structure includes a buffer layer over the semiconductor substrate and a barrier layer over the buffer layer. A p-doped III-N layer is disposed over the barrier layer in the gate region and a gate electrode is formed over the p-doped III-N layer. A first hydrogen-blocking layer is disposed over the gate electrode where the first hydrogen-blocking layer is configured to arrest diffusion of hydrogen into the p-doped III-N layer from a dielectric layer formed after forming the gate electrode.

The embodiment of the invention provides a laser array and a laser radar, and relates to the technical field of optical perception. The differential resistance of the laser array is adjustable, and the optical power of the output emitted laser is adjustable. The laser array comprises a first laser and a second laser; the first laser comprises a first reflecting layer, a first active layer and a second reflecting layer which are sequentially arranged along the epitaxial direction, and a first oxidation hole is formed in the second reflecting layer; the second laser comprises a third reflecting layer, a second active layer and a fourth reflecting layer which are sequentially arranged in the epitaxial direction, a second oxidation hole is formed in the fourth reflecting layer, and a light blocking layer is further arranged on the side, away from the second active layer, of the fourth reflecting layer. The projection of the light blocking layer on the second active layer is overlapped with the projection of the second oxidation hole on the second active layer; the first laser is electrically connected with the second laser.

A display device includes a display area in which a plurality of pixels, each including a plurality of pixel electrodes spaced apart from each other, are disposed. A first light blocking layer is disposed in the display area and includes a plurality of holes overlapping the plurality of pixel electrodes. A plurality of color filters is disposed on the first light blocking layer and respectively corresponds to the plurality of holes. A second light blocking layer is disposed on the color filter and corresponds to the pixel electrodes of some of the plurality of pixels. The second light blocking layer surrounds the pixel electrodes of some of the plurality of pixels in a plan view and includes a plurality of light blocking patterns having different widths.

The invention provides a trans-perovskite solar cell containing a fluorine arene phosphoric acid function compensation layer and a preparation method thereof, and the solar cell comprises a conductive substrate, a hole transport layer, a self-assembly monomolecular layer, a function compensation layer, a light active layer, an electron transport layer, a hole blocking layer and a back electrode which are sequentially stacked from bottom to top. The material of the function compensation layer is fluorine-containing aromatic hydrocarbon phosphoric acid. The fluorine-containing aromatic phosphoric acid provided by the invention can make up the anchoring defect on the basis of a self-assembled monomolecular layer, and can effectively passivate the defect at the bottom of perovskite through a plurality of active sites at the same time; the problem of non-ideal performance and stability caused by excessive defects at the self-assembled monomolecular layer / perovskite buried bottom interface of the trans-perovskite solar cell is solved, and a valuable scheme is provided for commercialization of the trans-perovskite solar cell in the future.

A display device includes a substrate, a semiconductor layer on the substrate, a gate insulating layer on the semiconductor layer, a first upper hydrogen blocking layer on the gate insulating layer and having a positive hydrogen formation energy, a first upper hydrogen capturing layer on the first upper hydrogen blocking layer corresponding to a central portion of the semiconductor layer and having a negative hydrogen formation energy, a gate electrode on the first upper hydrogen capturing layer, a source electrode and a drain electrode connected to both end portions of the semiconductor layer, and a passivation layer on the gate electrode, the source electrode and the drain electrode.

A method, device, and system for starting containers is provided. The method includes (i) in response to determining to start a container, determining whether a container layer for the container has been previously converted to a block storage format; (ii) in response to determining that the container layer has not been previously converted to a block storage format, downloading an archived version of the container layer, converting the archived version into a block storage format version of the container layer, storing the block storage format version of the container layer into a blob storage, and starting the container; and (iii) in response to determining that the container layer has been previously converted to a block storage format, starting the container based at least in part on the block storage format version.

A semiconductor device may include a gate structure including stacked conductive layers and insulating regions disposed between the conductive layers; a channel layer extending through the gate structure; data storage patterns surrounding the channel layer and disposed between the channel layer and the conductive layers, respectively; oxidation patterns surrounding the channel layer and disposed between the channel layer and the insulating regions, respectively; and a blocking layer surrounding the data storage patterns and the oxidation patterns and including concave portions disposed to correspond to the insulating regions.

The present invention relates to the field of optoelectronics, and discloses a light-emitting diode epitaxial wafer, a method for manufacturing the same, and an LED. The light-emitting diode epitaxial wafer comprises a substrate, on which a buffer layer, an undoped GaN layer, an N-type GaN layer, an active layer, an electron blocking layer, and a P-type GaN layer are sequentially provided; the electron blocking layer comprises a BAlN / P-GaN superlattice layer, an AlGaN / P-InGaN superlattice layer, and a BN layer stacked in sequence. The light-emitting diode epitaxial wafer provided by the present invention reduces electron overflow, improves hole injection efficiency, replenishes hole concentration, and enhances the luminous efficiency of the light-emitting diode.

Embodiments of the present application relate to the technical field of optical sensing, and provide a laser array and a laser radar. The differential resistance of the laser array is adjustable, and the optical power of output emitted laser light is adjustable. The laser array comprises a first laser and a second laser; the first laser comprises a first reflecting layer, a first active layer, and a second reflecting layer which are sequentially arranged in an epitaxial direction, and a first oxidation hole is formed in the second reflecting layer; the second laser comprises a third reflecting layer, a second active layer, and a fourth reflecting layer which are sequentially arranged in the epitaxial direction, a second oxidation hole is formed in the fourth reflecting layer, a light blocking layer is further provided on the side of the fourth reflecting layer away from the second active layer, and the projection of the light blocking layer on the second active layer overlaps the projection of the second oxidation hole on the second active layer; the first laser is electrically connected to the second laser.

This invention relates to an aromatic amine organic compound and an organic electroluminescent device containing the same, belonging to the field of semiconductor materials technology. The structure of the compound provided by this invention is shown in general formula (1): When the hole transport material or electron blocking layer material of the organic electroluminescent device is prepared by using the aromatic amine compound of this invention, the device voltage can be reduced and the device life can be extended at the same time, especially the device high temperature life is significantly improved.

The invention discloses an imidazole derivative molecule modified solar cell and a preparation method thereof, and belongs to the technical field of solar cells. The cell sequentially comprises an ITO (Indium Tin Oxide) conductive glass layer, a nickel oxide passivation layer, a [4-(3, 6-dimethoxy-9H-carbazole-9-yl) butyl] phosphonic acid hole transport layer, an ITO (Indium Tin Oxide) conductive glass layer and a nickel oxide passivation layer from bottom to top, the thin film solar cell is characterized in that the thin film solar cell comprises a substrate, a metal Ag electrode layer, a Cs0.05 (FA0. 95MA0. 05) 0. 95Pb (I0. 95Br0. 05) 3 narrow-band gap perovskite thin film PVSK modified by 2-(2 ', 6'-dichloroanilino)-2-imidazoline, a (6, 6)-phenyl-C61-butyric acid methyl ester electron transport layer, a 2, 9-dimethyl-4, 7-biphenyl-1, 10-phenanthroline hole blocking layer and a metal Ag electrode layer; according to the scheme, perovskite defects are passivated through imidazole derivative molecules, double-interface passivation and crystallization regulation are achieved, the film quality is improved, and the crystal quality of the perovskite film is remarkably improved; due to effective passivation of the double interfaces, ion migration is obviously inhibited, the carrier transmission efficiency is effectively improved, and the moisture resistance of the perovskite thin film and the device stability are improved.

According to one embodiment, a display device includes an anode, an organic EL element layer including a hole injection layer, a hole transport layer, an electron blocking layer, a light-emitting layer, a hole blocking layer, an electron transport layer and an electron injection layer, and a cathode, wherein ΔE2_LUMO is defined as a potential barrier between the electron transport layer and the hole blocking layer, and the light-emitting layer, ΔE2_HOMO is defined as a potential barrier between the hole transport layer and the electron blocking layer, and the light-emitting layer, and each of ΔE2_LUMO and ΔE2_HOMO is 0.1 eV or higher and 0.5 eV or less.

Systems, methods and computer readable media relating to neuro-thermodynamic computers configured to implement hierarchical architecture, wherein the hierarchical architecture includes one or more layers of components, and wherein the hierarchical architecture is configured to perform Gibbs sampling and nested Gibbs sampling. For example, a block layer may include an energy based model (EBM) implemented using oscillators and couplings between oscillators. A chip layer may include multiple blocks coupled to each other using relay oscillators. A package layer may include multiple chips coupled to each other using additional relay oscillators.

The present disclosure relates to semiconductor manufacturing technology, particularly relates to a light-emitting diode, which includes a light-emitting layer, an N-type semiconductor layer, a P-type semiconductor layer, an electron blocking layer and a connecting layer. The light- emitting layer has a first side and a second side opposite to each other. The N-type semiconductor layer is disposed on the first side of the light-emitting layer. The P-type semiconductor layer is disposed on the second side of the light-emitting layer. The electron blocking layer is disposed between the light-emitting layer and the P-type semiconductor layer. The connecting layer is disposed between the light-emitting layer and the electron blocking layer, wherein, the connecting layer is doped with indium.

The embodiment of the invention discloses an acceleration method and device based on an irregular sparse model, electronic equipment and a medium. A specific embodiment of the method comprises the steps of inputting a sparse model into a target compiler; in the layer intermediate representation, splitting a sparse weight matrix of the sparse model into sparse sub-blocks to obtain a split sparse weight matrix; based on a sparse operator performance model, generating attribute information of each sparse sub-block in the split sparse weight matrix; in the block layer intermediate representation, according to the attribute information of each sparse sub-block, performing fusion processing on each sparse sub-block; in operator layer intermediate representation, according to attribute information corresponding to each sparse block, mapping each sparse block and a calculation unit to obtain a mapping result; and generating a processing task corresponding to the sparse model according to the mapping result, and executing the processing task. According to the embodiment, end-to-end optimization is realized through multi-layer optimization, and the income boundary of the traditional irregular sparse acceleration design is broken through.

A method for manufacturing a semiconductor device includes: forming a first conductive interconnect which penetrates a dielectric layer disposed over a substrate; forming a patterned dielectric layer on the dielectric layer, the patterned dielectric layer being formed with a trench and the first conductive interconnect being exposed from the trench; selectively forming a blocking layer to cover the first conductive interconnect, the blocking layer being formed using an acidic solution including a blocking material; selectively forming a barrier material layer on the dielectric layer and the patterned dielectric layer; removing the blocking layer; forming a conductive material layer on the barrier material layer; and removing a portion of the conductive material layer and a portion of the barrier material layer to form a second conductive connected to the first conductive interconnect.

The invention provides a nitride semiconductor laser. The laser comprises a substrate, a lower coating layer, a lower waveguide layer, an active layer, an upper waveguide layer, an electron blocking layer and an upper coating layer which are sequentially arranged from bottom to top. And the lower waveguide layer comprises any one or a combination of more of InGaN, GaN, InN, AlInGaN, an InGaN / GaN superlattice, an InGaN / AlGaN superlattice, an InGaN / AlGaN superlattice, an InGaN / AlInN superlattice and an InGaN / AlInGaN superlattice. The peak rate electric field distribution of the lower waveguide layer has an arc distribution, and the peak rate electric field distribution has a curve distribution of a function y = logax (a > 1). The drift rate distribution of the saturated electrons of the lower waveguide layer has an arc-shaped distribution, and the drift rate distribution of the saturated electrons has a curve distribution of a third quadrant of a function y = x-b (b > 1, b is an odd number). The density distribution of valence band effective states of the lower waveguide layer has a curve distribution of a third quadrant of a function y = (cx + 1) / (cx-1) (c > 1).

An organic semiconductor device with low driving voltage is provided. The light-emitting device includes an anode, a cathode, and an EL layer between the anode and the cathode. The EL layer includes a hole-transport layer and alight-emitting layer. The hole-transport layer is positioned between the anode and the light-emitting layer. The hole-transport layer is not in contact with the anode. The hole-transport layer includes a transport layer material for a light-emitting device and the GSP_slope that is a potential gradient of a surface potential of an evaporated film of the material is higher than or equal to 20 (mV / nm).

Provided are display device and method of fabricating the same. A display device comprises a display panel having a first surface and a second surface; a light-blocking layer having a third surface and a fourth surface, the fourth surface facing the first surface of the display panel, the light-blocking layer comprising a recess portion on the third surface and a non-recess portion around the recess portion, and containing a material that selectively blocks light; a light-transmitting layer located on the light-blocking layer; a recess cover disposed between the recess portion and the light-transmitting layer; and an infrared sensor located on the light-transmitting layer and the recess cover, wherein the light-blocking layer blocks light having wavelengths in visible range and transmits light having wavelengths in infrared range.

The invention discloses a display panel, a preparation method thereof and a display device. The display panel comprises a substrate, an anode layer, a protective layer, a barrier layer and an insulating layer, wherein the substrate comprises a plurality of pixel areas arranged at intervals; the anode layer is located in the pixel area; the protection layer comprises a first protection layer branch part, and the first protection layer branch part at least partially covers the side wall of the anode layer; the barrier layer covers the first protective layer subsection; the insulating layer is filled between the adjacent pixel areas, and the insulating layer covers the barrier layer. According to the display panel, the barrier layer is arranged to ensure the uniformity of the etch-back water level in the wafer or the chip in the preparation process, and the protective layer is arranged to protect the side wall of the anode layer, so that the corrosion of the anode layer metal caused by the etching process in the preparation process of the barrier layer and the insulating layer is avoided, and the display effect of the display panel is improved.

Semiconductor structures and methods are provided. A semiconductor structure according to the present disclosure includes a substrate, a first semiconductor layer over the substrate, a second semiconductor layer over the first semiconductor layer and including a channel region sandwiched between a first source / drain region and a second source / drain region, a first plurality of nanostructures disposed over the channel region, a first leakage block layer over the first source / drain region, a second leakage block layer over the second source / drain region, a dielectric layer on the first leakage block layer, a first source / drain feature on the dielectric layer and in contact with first sidewalls of the first plurality of nanostructures, and a second source / drain feature disposed on the second leakage block layer and in contact with second sidewalls of the first plurality of nanostructures. The first leakage block layer and the second leakage block layer includes an undoped semiconductor material.

A display device includes a lower substrate, a pixel defining layer, a light emitting layer, an upper substrate, and a light blocking layer. The pixel defining layer is disposed on the lower substrate and includes a first opening and a second opening spaced apart from the first opening in a first direction. The light emitting layer is disposed in each of the first opening and the second opening. The upper substrate is disposed on the light emitting layer. The light blocking layer is disposed on the upper substrate and includes a third opening partially exposing the first opening and a fourth opening partially exposing the second opening. A first shape in which the first opening is exposed by the third opening and a second shape in which the second opening is exposed by the fourth opening are symmetrical to each other about a line of symmetry in a plan view.

The embodiments of the present disclosure belong to the technical field of back-contact cells, and particularly relate to a hybrid-passivated back-contact cell having passivation blocking layers and the manufacturing and application thereof. The hybrid-passivated back-contact cell comprises first semiconductor layers and second semiconductor layers, which are alternately arranged on a back surface of a silicon wafer, wherein two ends of each of the second semiconductor layers each extend outward to cover the outside of part of a back surface of a first semiconductor layer adjacent thereto; and overlapping portions of the first semiconductor layers and the second semiconductor layers in the direction of thickness form overlapping regions. The hybrid-passivated back-contact cell further comprises passivation blocking layers, which are in the overlapping regions and are arranged between the first semiconductor layers and the second semiconductor layers, wherein no mask layer is provided between the passivation blocking layers and the second semiconductor layers, the passivation blocking layers are made of amorphous silicon, and the thickness ratio of the passivation blocking layers to first doped polycrystalline silicon layers to tunneling oxide layers is 2-8: 60-100: 1. The embodiments of the present disclosure can protect the tunneling oxide layers from being corroded, thereby synergistically enhancing a passivation effect, and increasing the conversion efficiency and production yield of the cell.

The invention provides a semiconductor structure and a forming method thereof, and the semiconductor structure comprises a substrate which comprises a first device region and a second device region; the first gate structure is positioned on a part of the surface of the substrate in the first device region; the second gate structure is positioned on a part of the surface of the substrate in the second device region; the first source-drain doped region is positioned in the substrate at two sides of the first gate structure; the second source-drain doped region is positioned in the substrate at two sides of the second gate structure; the silicide barrier layer is located on the side wall of the first gate structure, and the silicide barrier layer further covers the surface of the second source-drain doped region and the top surface and the side wall surface of the second gate structure; the silicide layer is located on the surface of the first source-drain doped region and the top surface of the first gate structure; according to the method, the side wall of the gate structure in the region where the silicide layer needs to be formed is adjusted, the silicide barrier layer is directly used as the side wall corresponding to the first gate structure, compared with a traditional process, the distance between the gate structures is increased, a large space is provided for forming the silicide layer, and the forming difficulty of the silicide layer is reduced.

The invention discloses a preparation method of a semiconductor power device, and belongs to the technical field of semiconductors. Comprising the steps that an epitaxial layer and a barrier layer are sequentially arranged on a substrate layer, a groove is formed through photoetching, and a heavily-doped polycrystalline silicon layer is deposited in the groove through thermal oxidation; performing wet etching on the side wall of the groove, and performing thermal oxidation to form a gate oxide layer; the method comprises the following steps of: depositing a heavily doped polycrystalline silicon layer in a groove; performing ion implantation on the epitaxial layer in sequence; an insulating medium layer is formed above the grid polycrystalline silicon and the first isolation layer, a plurality of contact holes are etched inwards, and the distance between each contact hole and the corresponding groove is linearly increased; injecting ions into the bottom of the contact hole, and filling a metal filling layer; arranging a back drain metal layer on the back of the substrate layer; and mirroring and repeating. The manufacturing method has the beneficial effects that the basic unit cells are mirrored and repeated, so that the distance between the grooves and the contact holes is linearly increased, the heating uniformity of the device is improved, the heat dissipation capability is improved, and the safe working area of the device is widened.