15 results about "Metal work function" patented technology

In a wet etching process to pattern a metal layer such as a p-metal work function layer over a dielectric layer such as a high-k gate dielectric layer, a selectivity of the wet etching solution between the metal layer and the dielectric layer is increased utilizing an inhibitor. The inhibitor includes such inhibitors as a phosphoric acid, a carboxylic acid, an amino acid, or a hydroxyl group.

The utility model provides a silicon carbide MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) capable of reducing the voltage drop of a body diode. The lower side surface of an epitaxial layer is connected to the upper side surface of a silicon carbide substrate; a first groove is formed in the epitaxial layer; the P-type base region is arranged in the first groove, and a second groove is formed in the P-type base region; the N + source region is arranged in the second groove; the P + source region is arranged in the second groove, and the outer side surface of the P + source region is connected to the inner side surface of the N + source region; the lower side surface of the gate oxide layer is connected to the N + source region, the P-type base region and the epitaxial layer; the lower side surface of the polycrystalline silicon electrode layer is connected to the upper side surface of the gate oxide layer; the lower side surface of the first contact metal layer is connected to the N + source region; the lower side surface of the second contact metal layer is connected to the P + source region, and the second contact metal layer is connected to the first contact metal layer; the metal work function of the first contact metal layer is smaller than that of the second contact metal layer; and on the basis of reducing the on resistance, the forward voltage drop of the body diode is reduced, and the loss of the MOSFET when being applied in a circuit is also reduced.

To provide a method for forming an integrated circuit having a gate electrode that includes at least one layer containing molybdenum.SOLUTION: A semiconductor device 101 includes a gate structure that includes a gate electrode, on a gate dielectric 110, made up of a conductive fill 108 and one or more metal work function layers 109. The gate structure extends around a fin or any number of nanowires, nanoribbons, or nanosheets of a semiconductor material. The gate electrode includes one or more conductive layers on the gate dielectric, and at least one of those conductive layers contains molybdenum (e.g., molybdenum nitride). The conductive layer containing molybdenum may be used during the formation of the gate dielectric (e.g., during an annealing process), thus resulting in a higher quality gate dielectric.SELECTED DRAWING: Figure 1A

In a wet etching process to pattern a metal layer such as a p-metal work function layer over a dielectric layer such as a high-k gate dielectric layer, a selectivity of the wet etching solution between the metal layer and the dielectric layer is increased utilizing an inhibitor. The inhibitor includes such inhibitors as a phosphoric acid, a carboxylic acid, an amino acid, or a hydroxyl group.

The invention discloses a method for preparing a metal silicide, a semiconductor device and a preparation method of the semiconductor device. The method comprises the steps that a substrate, a gate structure and a substrate protection layer are prepared, the substrate protection layer is located in an active area of the substrate, and the gate structure comprises a metal work function layer used for regulating and controlling gate threshold voltage and a gate protection layer used for protecting the gate structure which are sequentially arranged from bottom to top; etching the substrate protection layer through etching gas by using a contact hole process to form a first contact hole of which the bottom is positioned in the active region; and forming a metal silicide in the active region by taking the first contact hole as a reaction window. Through the scheme of the embodiment of the invention, the working procedures of a grid side wall thickening process and a wet-method grid side wall thinning process can be simplified, so that the problem that holes appear in the interlayer insulating dielectric layer is solved, the risk of device bridging is reduced, and meanwhile, the reliability of the device is improved. And the damage to the metal silicide and the gate structure caused by chemical liquid medicine used in a wet-method gate side wall thinning process can be avoided, so that the risks of poor contact and failure of the device are reduced.

A semiconductor gate-all-around (GAA) device may include a semiconductor substrate, source and drain regions on the semiconductor substrate, a plurality of semiconductor nanostructures extending between the source and drain regions, a gate surrounding the plurality of semiconductor nanostructures in a gate-all-around arrangement, and a dopant diffusion liner adjacent at least one of the source and drain regions and comprising a first superlattice. The first superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

The application discloses a preparation method of quasi ohmic contact of weak p-type Ga2O3 and a solar blind photoelectric detector, and belongs to the technical field of semiconductor device preparation. The preparation method does not depend on traditional metal work function matching, a patterned Zn metal layer is prepared on the surface of the weak p-type Ga2O3 semiconductor layer, and a cyclic stepwise thermal annealing treatment is performed in a protective atmosphere, each temperature step is heated to a target temperature and kept for a certain time, and then cooled to room temperature, and the target temperature is increased with the time gradient. Through the cyclic stepwise thermal annealing treatment, the Zn metal kinetic instability is overcome, controllable and stable interface doping is realized, a gradient p + interface layer is constructed in situ, the energy band structure of the contact area is physically modified, and the ohmic contact problem on the strong FLP material is effectively solved. The solar blind photoelectric detector prepared based on the method has excellent performance.

The invention discloses a thin film transistor, a manufacturing method of the thin film transistor, a memory and a reading method of the memory. The thin film transistor comprises a first electrode, a first dielectric layer and a second electrode which are stacked in sequence and are all arranged on the outer side of the thin film transistor. The first electrode is made of a first metal material, the second electrode is made of a second metal material, and the work functions corresponding to the first metal material and the second metal material are different. According to the embodiment of the invention, the source electrode and the drain electrode of the vertical thin film transistor are made of electrode materials with asymmetric metal work functions, so that the transfer characteristics IDS-VG of source and drain currents in different directions of the transistor have asymmetry, and the output responses IDS-VDS are different. Therefore, when the thin film transistor is used as a reading transistor of the gain unit, crosstalk current during reading operation of the memory can be remarkably suppressed, larger reading margin is realized, meanwhile, the number of array memory units can be increased, and the reading operation power consumption of the memory can be reduced.

The invention discloses an isolated conductor surface potential control method based on active disturbance rejection control, and belongs to the technical field of space inertial sensor charge control. According to the invention, the problem that stable control of the surface potential of the isolated conductor cannot be realized due to insufficient dynamic response capability of the existing control method when the environmental charging rate is increased transiently and sharply is solved. According to the method, the environmental charging rate disturbance is accurately observed through the expansion state observer including disturbance error compensation, and the problems of metal work function change and related parameter attenuation of the potential control system caused by ultraviolet LED aging and environmental pollution influence are inhibited through the transition effect of the differential tracker and a nonlinear state error feedback control law. Particularly, when the environmental charging rate is increased sharply due to an extreme particle event, the surface potential of the isolated conductor can be controlled by compensation feedback to track the change potential in a scientific mode, so that the potential of the isolated conductor is always kept in a stable state. The method can be applied to isolated conductor surface potential control.

A semiconductor gate-all-around (GAA) device may include a semiconductor substrate, source and drain regions on the semiconductor substrate, a plurality of semiconductor nanostructures extending between the source and drain regions, a gate surrounding the plurality of semiconductor nanostructures in a gate-all-around arrangement, and a dopant diffusion liner adjacent at least one of the source and drain regions and comprising a first superlattice. The first superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

The invention provides an annealing method of a semiconductor structure, which comprises the following steps of: providing an annealing system comprising a process control module and an annealing machine, establishing a relationship between the film thickness of the metal work function layers made of different materials and the open-loop power and annealing time during annealing, and writing the relationship into a process control module; providing a wafer to be annealed, wherein a metal work function layer is formed on the upper surface layer of the wafer to be annealed, and conveying the wafer to the annealing machine table; the annealing system obtains the film thickness and the material of the metal work function layer, and feeds back the film thickness and the material of the metal work function layer to the process control module; and the process control module carries out processing based on the relationship to obtain preset power, modifies the open-loop power in the menu into the preset power, and controls the annealing machine to carry out annealing work. According to the invention, the open-loop power is obtained by processing the relationship among the film thickness, the open-loop power and the annealing time, and the open-loop power in the menu is modified by using the process control module, so that the establishment of the menu is reduced.

A display device includes: a substrate including: a first region, and a second region, an anode at the first region, an organic layer on the anode at the first region, and on the second region, an electron injection layer on the organic layer at the first region and the second region, the electron injection layer including a first metal, a cathode on the electron injection layer at the first region, the cathode including a second metal having a greater work function than a work function of the first metal, and a capping layer on the cathode at the first region, and on the electron injection layer at the second region.

This disclosure discloses a method for preparing metal silicides, a semiconductor device, and the same method. The method includes: preparing a substrate, a gate structure, and a substrate protective layer, wherein the substrate protective layer is located in the active region of the substrate; the gate structure includes, from bottom to top, a metal work function layer for regulating the gate threshold voltage and a gate protective layer for protecting the gate structure; using a contact hole process, etching the substrate protective layer with an etching gas to form a first contact hole with its bottom located in the active region; and forming metal silicides in the active region using the first contact hole as a reaction window. The scheme of this disclosure simplifies the steps in the gate sidewall thickening process and the wet gate sidewall thinning process, thereby solving the problem of voids in the interlayer insulating dielectric layer and reducing the risk of device bridging. Simultaneously, it avoids damage to the metal silicides and gate structure caused by the chemical solutions used in the wet gate sidewall thinning process, thereby reducing the risk of poor device contact and device failure.

The present invention provides a method for predicting the metal work function fluctuation effect of semiconductor field-effect transistors. The method comprises solving for target devices under multiple sets of metal work function conditions, extracting electrical characteristic parameters during device operation, and forming a data set required for constructing a metal work function fluctuation effect prediction model. Based on the fitting relationship between different electrical characteristic parameters and metal work functions in the data set, a fitting function for the metal work function fluctuation effect prediction model is calculated and verified to obtain a verified prediction model. A metal work function fluctuation distribution probability model is established based on the mechanism of metal work function fluctuation during the production process, and a random distribution sample of metal work function fluctuation is generated. The random distribution sample of metal work function fluctuation of the device to be predicted is input into the verified prediction model to obtain the fluctuation distribution of the electrical characteristic parameters of the device under metal work function fluctuation. The present invention can quickly and accurately predict the effect of metal work function fluctuation on device performance.

The present invention discloses a circuit simulation method for metal work function fluctuation of a nanosheet gate-all-around field-effect transistor, belonging to the field of microelectronic devices. This circuit simulation method first performs global model extraction on the IV and CV data of the nanosheet gate-all-around field-effect transistor based on the BSIM-CMG model, and then uses a calculation formula to obtain the mean and standard deviation of the fluctuation of the parameter PHIG in the model under the influence of metal work function fluctuation. By embedding them into the simulation netlist of the circuit simulation software for circuit simulation, the circuit performance parameters caused by metal work function fluctuation can be obtained. Using the present invention, the influence of device characteristic fluctuation can be obtained more accurately, and the accuracy is consistent with the result obtained by TCAD simulation. The traditional TCAD simulation volatility method is slow and costly, while the circuit simulation method established by the present invention is fast and has small errors.