7 results about "Metal work function" patented technology

The utility model provides a silicon carbide MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) capable of reducing the voltage drop of a body diode. The lower side surface of an epitaxial layer is connected to the upper side surface of a silicon carbide substrate; a first groove is formed in the epitaxial layer; the P-type base region is arranged in the first groove, and a second groove is formed in the P-type base region; the N + source region is arranged in the second groove; the P + source region is arranged in the second groove, and the outer side surface of the P + source region is connected to the inner side surface of the N + source region; the lower side surface of the gate oxide layer is connected to the N + source region, the P-type base region and the epitaxial layer; the lower side surface of the polycrystalline silicon electrode layer is connected to the upper side surface of the gate oxide layer; the lower side surface of the first contact metal layer is connected to the N + source region; the lower side surface of the second contact metal layer is connected to the P + source region, and the second contact metal layer is connected to the first contact metal layer; the metal work function of the first contact metal layer is smaller than that of the second contact metal layer; and on the basis of reducing the on resistance, the forward voltage drop of the body diode is reduced, and the loss of the MOSFET when being applied in a circuit is also reduced.

The invention discloses a method for preparing a metal silicide, a semiconductor device and a preparation method of the semiconductor device. The method comprises the steps that a substrate, a gate structure and a substrate protection layer are prepared, the substrate protection layer is located in an active area of the substrate, and the gate structure comprises a metal work function layer used for regulating and controlling gate threshold voltage and a gate protection layer used for protecting the gate structure which are sequentially arranged from bottom to top; etching the substrate protection layer through etching gas by using a contact hole process to form a first contact hole of which the bottom is positioned in the active region; and forming a metal silicide in the active region by taking the first contact hole as a reaction window. Through the scheme of the embodiment of the invention, the working procedures of a grid side wall thickening process and a wet-method grid side wall thinning process can be simplified, so that the problem that holes appear in the interlayer insulating dielectric layer is solved, the risk of device bridging is reduced, and meanwhile, the reliability of the device is improved. And the damage to the metal silicide and the gate structure caused by chemical liquid medicine used in a wet-method gate side wall thinning process can be avoided, so that the risks of poor contact and failure of the device are reduced.

The application discloses a preparation method of quasi ohmic contact of weak p-type Ga2O3 and a solar blind photoelectric detector, and belongs to the technical field of semiconductor device preparation. The preparation method does not depend on traditional metal work function matching, a patterned Zn metal layer is prepared on the surface of the weak p-type Ga2O3 semiconductor layer, and a cyclic stepwise thermal annealing treatment is performed in a protective atmosphere, each temperature step is heated to a target temperature and kept for a certain time, and then cooled to room temperature, and the target temperature is increased with the time gradient. Through the cyclic stepwise thermal annealing treatment, the Zn metal kinetic instability is overcome, controllable and stable interface doping is realized, a gradient p + interface layer is constructed in situ, the energy band structure of the contact area is physically modified, and the ohmic contact problem on the strong FLP material is effectively solved. The solar blind photoelectric detector prepared based on the method has excellent performance.

A semiconductor gate-all-around (GAA) device may include a semiconductor substrate, source and drain regions on the semiconductor substrate, a plurality of semiconductor nanostructures extending between the source and drain regions, a gate surrounding the plurality of semiconductor nanostructures in a gate-all-around arrangement, and a dopant diffusion liner adjacent at least one of the source and drain regions and comprising a first superlattice. The first superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

The invention provides an annealing method of a semiconductor structure, which comprises the following steps of: providing an annealing system comprising a process control module and an annealing machine, establishing a relationship between the film thickness of the metal work function layers made of different materials and the open-loop power and annealing time during annealing, and writing the relationship into a process control module; providing a wafer to be annealed, wherein a metal work function layer is formed on the upper surface layer of the wafer to be annealed, and conveying the wafer to the annealing machine table; the annealing system obtains the film thickness and the material of the metal work function layer, and feeds back the film thickness and the material of the metal work function layer to the process control module; and the process control module carries out processing based on the relationship to obtain preset power, modifies the open-loop power in the menu into the preset power, and controls the annealing machine to carry out annealing work. According to the invention, the open-loop power is obtained by processing the relationship among the film thickness, the open-loop power and the annealing time, and the open-loop power in the menu is modified by using the process control module, so that the establishment of the menu is reduced.

A display device includes: a substrate including: a first region, and a second region, an anode at the first region, an organic layer on the anode at the first region, and on the second region, an electron injection layer on the organic layer at the first region and the second region, the electron injection layer including a first metal, a cathode on the electron injection layer at the first region, the cathode including a second metal having a greater work function than a work function of the first metal, and a capping layer on the cathode at the first region, and on the electron injection layer at the second region.

This disclosure discloses a method for preparing metal silicides, a semiconductor device, and the same method. The method includes: preparing a substrate, a gate structure, and a substrate protective layer, wherein the substrate protective layer is located in the active region of the substrate; the gate structure includes, from bottom to top, a metal work function layer for regulating the gate threshold voltage and a gate protective layer for protecting the gate structure; using a contact hole process, etching the substrate protective layer with an etching gas to form a first contact hole with its bottom located in the active region; and forming metal silicides in the active region using the first contact hole as a reaction window. The scheme of this disclosure simplifies the steps in the gate sidewall thickening process and the wet gate sidewall thinning process, thereby solving the problem of voids in the interlayer insulating dielectric layer and reducing the risk of device bridging. Simultaneously, it avoids damage to the metal silicides and gate structure caused by the chemical solutions used in the wet gate sidewall thinning process, thereby reducing the risk of poor device contact and device failure.