54 results about "Low work function" patented technology

Provided is a multi-stack semiconductor device that includes: a lower field-effect transistor in which a lower channel structure is surrounded by a lower gate structure including a lower gate dielectric layer, a lower work-function metal layer and a lower gate metal pattern; and an upper field-effect transistor in which an upper channel structure is surrounded by an upper gate structure including an upper gate dielectric layer, an upper work-function metal layer and an upper gate metal pattern, wherein a channel width of the upper channel structure is smaller than a channel width of the lower channel structure, and wherein a replacement metal gate (RMG) inner spacer is formed between the lower work-function metal layer and the upper work-function metal layer at regions where the lower channel structure is not vertically overlapped by the upper channel structure.

A semiconductor device according to one embodiment includes a semiconductor part including a first semiconductor layer, a second semiconductor layer located on the first semiconductor layer, and a third semiconductor layer located in a first trench of the second semiconductor layer, a first electrode located on a back surface of the first semiconductor layer, a first metallic film in contact with the second semiconductor layer in the first trench, a second metallic film in contact with the third semiconductor layer and the first metallic film in the first trench, and a second electrode in contact with the second metallic film in the first trench. The first metallic film includes a high work function metal, and the second metallic film includes a low work function metal having a lower work function than that of the first metallic film.

An irradiation-resistant diamond Schottky diode and its fabrication method are disclosed. The purpose of this invention is to solve the problem of poor radiation resistance stability in Schottky diodes. In this irradiation-resistant diamond Schottky diode, p-type diodes are epitaxially grown on an intrinsic diamond substrate. + Diamond epitaxial layer, in p + An ohmic electrode is deposited in a portion of the upper surface of the diamond epitaxial layer, at p + p-type epitaxial growth is performed on the region of the diamond epitaxial layer where no ohmic electrode is deposited. ‑ Type II diamond drift layer, in p ‑ Easily oxidizable metal electrodes are deposited on a diamond drift layer, serving as Schottky electrodes. These electrodes are then terminated with oxygen. ‑ A metal oxide layer is formed between the drift layers of the diamond. This invention utilizes a low work function, easily oxidizable metal as a Schottky electrode. The low work function, easily oxidizable metal passivates the oxygen terminals on the diamond surface. The oxide layer formed on the diamond surface makes the oxygen terminals less susceptible to radiation-induced reconstruction, resulting in stronger radiation resistance.

A Schottky diode and a manufacturing method thereof, the Schottky diode comprising a first metal layer, a semiconductor layer, a second metal layer, a passivation layer and a metal sidewall; the first metal layer is formed on a substrate, and the first metal layer is a high work function metal; the semiconductor layer is formed on the first metal layer, or the semiconductor layer is partially formed on the first metal layer and partially formed on the substrate; the metal sidewall is in contact with a sidewall of the semiconductor layer, the metal sidewall is a high work function metal, and a Schottky contact is formed between the metal sidewall and the semiconductor layer; the passivation layer covers the metal sidewall, the semiconductor layer and the first metal layer; an ohmic contact is formed between the second metal layer and the semiconductor layer, and the second metal layer is a low work function metal. By arranging the metal sidewall on the sidewall of the semiconductor layer, the sidewall of the semiconductor layer is depleted by the Schottky contact between the metal sidewall and the semiconductor layer, the edge electric field is weakened, and the leakage current under reverse voltage is reduced.

Pixels in an organic light-emitting diode (OLED) display may have optical cavities defined by a partially transparent cathode layer and a reflective anode structure. Light at a wavelength emitted by a pixel may form a standing wave between the anode and the cathode. The standing wave may have an upper antinode and a lower antinode. Pixels of different colors may have emissive layers aligned with different antinodes. The OLED layers for the pixels may include an electron transport layer that is doped with a low work function material. The cathode may include one or more layers of transparent conductive oxide and / or metal. The cathode may be shorted to a metal mesh and / or a conductive cutting structure to decrease resistance.

A semiconductor device includes: a lateral layer spaced apart from a lower structure and extending in a direction parallel to the lower structure; a vertical conductive line extending in a direction perpendicular to the lower structure and coupled to a first-side end of the lateral layer; a data storage element coupled to a second-side end of the lateral layer; and a lateral conductive line extending in a direction crossing the lateral layer, wherein the lateral conductive line includes: a first work function electrode; a second work function electrode disposed adjacent to the vertical conductive line and having a lower work function than the first work function electrode; and a third work function electrode disposed adjacent to the data storage element and having a lower work function than the first work function electrode.

This invention provides a multi-electrode coupled optoelectronic device, comprising a bottom electrode made of a low work function metal, a p-type semiconductor layer with light-absorbing function disposed on the upper surface of the bottom electrode, a thin insulating layer disposed on the upper surface of the light-absorbing p-type semiconductor layer, an n-type semiconductor layer with light-absorbing function disposed on the surface of the insulating layer, a top electrode made of a high work function metal and at least one auxiliary electrode disposed on the upper surface of the light-absorbing n-type semiconductor layer. This invention also provides a method for fabricating the multi-electrode coupled optoelectronic device and its application.

The present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate and a word line. The word line is embedded in the substrate and includes a high work function layer and a low work function layer on the high work function layer, in which an average work function of the high work function layer is larger than an average work function of the low work function layer, the low work function layer includes a lower portion and an upper portion on the lower portion, and an average grain size of the lower portion is smaller than an average grain size of the upper portion.

The application belongs to the technical field of crystalline silicon solar cells, and particularly relates to an HBC solar cell structure and a non-amorphous damage preparation method thereof, which comprises the following steps: step S1, polishing both sides of a silicon wafer; step S2, depositing an i:a-Si layer, a P:a-Si layer, a high work function TCO layer and an i:a-Si mask layer on the back of the silicon wafer from top to bottom; step S3, laser oxidizing the P area of the back of the silicon wafer; step S4, wet cleaning the back of the silicon wafer; step S5, depositing an i:a-Si layer, an N:a-Si layer, a low work function TCO layer and an i:a-Si mask layer on the back of the silicon wafer from top to bottom; step S6, laser oxidizing the N area of the back of the silicon wafer; step S7, cleaning the back of the silicon wafer and texturing the front of the silicon wafer; step S8, preparing an aluminum oxide layer and a silicon nitride layer on the front and back of the silicon wafer, and filling an isolation area of an isolation interdigital arrangement structure; step S9, laser opening a mask on the back of the silicon wafer; and step S10, printing metal paste in a windowed area to complete the preparation of the solar cell.

The invention relates to the technical field of preparation of organic photoelectric materials, in particular to an electron injection material and an OLED (Organic Light Emitting Diode). An electron injection layer material containing an N atom group is used as a main body material and is subjected to co-evaporation with low-work function metal to form an electron injection layer; the compound containing the N atom group in the main body material binds the low work function metal, so that the stability of the metal in the electron injection layer is improved, the interface bonding effect between the cathode and the electron transmission layer is optimized, the active metal content of the electron injection layer is reduced, the layering influence between the organic layer and the metal is reduced, and the performance of the device is improved. And the device life and luminous efficiency are improved.

A thermionic energy converter, preferably including an anode and a cathode. An anode of a thermionic energy converter, preferably including an n-type semiconductor, one or more supplemental layers, and an electrical contact. A method for work function reduction and / or thermionic energy conversion, preferably including inputting thermal energy to a thermionic energy converter, illuminating an anode of the thermionic energy converter, thereby preferably reducing a work function of the anode, and extracting electrical power from the system.

A semiconductor device includes: a trench formed in a substrate; a gate dielectric layer covering sidewalls and a bottom surface of the trench; a first gate electrode gap-filling a bottom portion of the trench over the gate dielectric layer; a second gate electrode including a metal nitride which is the same as the first gate electrode over the first gate electrode and doped with a low work function adjusting element; a buffer layer covering a top surface of the second gate electrode and the gate dielectric layer exposed over second gate electrode; and a capping layer gap-filling the other portion of the trench over the buffer layer.

The present technology generally relates to vertical cell array transistors (VCATs) and methods of forming such VCATs. The VCAT includes one or more bit lines arranged in a first horizontal direction, one or more word lines arranged in a second horizontal direction, and one or more channels extending in a vertical direction substantially orthogonal to the first direction and the second horizontal direction, the one or more channels are configured such that the one or more bit lines intersect the source / drain regions of the one or more channels and the one or more word lines intersect the gate regions of the one or more channels. The VCAT includes where at least one of the one or more word lines includes a first portion adjacent to the source / drain region and a second portion adjacent to the gate region. The second portion includes a high work function material and the first portion includes a low work function material.

The invention discloses a threshold voltage adjusting method of an HKMG. The threshold voltage adjusting method comprises the steps of 1, completing a process ring of a P-type metal gate so as to form a patterned work function TiN layer on a semiconductor substrate on which a TaN barrier layer is formed; the semiconductor substrate comprises multiple levels of threshold voltage regions, the thicknesses of work function TiN layers of the threshold voltage regions are different, the threshold voltage regions are divided into multiple CPP regions according to different CPP, and the CPP enables the thicknesses of the work function TiN layers of the CPP regions in the threshold voltage regions to generate a first difference. And 2, selective etching with the etching selection ratio of TaN to TiN larger than 1 is carried out through WCl5, and in selective etching, CPP can generate a second influence on the etching thickness of the work function TiN layer so that the first difference can be reduced. And thirdly, a work function TiAl layer is formed. According to the invention, the threshold voltages of different CPP regions can be cooperatively regulated and controlled, the filling thickness of the work function material is reduced, a work function material filling window is effectively expanded, the threshold voltage regulation and control range is expanded, and a reliability test window is expanded.

The invention discloses a FeOCl / MoS2 heterojunction catalyst as well as a preparation method and application thereof, and belongs to the technical field of water treatment materials. The FeOCl / MoS2 heterojunction catalyst comprises a two-dimensional layered 2H-phase MoS2 substrate and a FeOCl nanosheet which is grown on the surface of the MoS2 substrate in an in-situ manner, wherein a heterojunction interface in close contact is formed between the FeOCl and the MoS2, and a built-in electric field pointing to the FeOCl from the MoS2 exists at the heterojunction interface. According to the present invention, by using the difference of energy bands during the interface contact of FeOCl and MoS2, the interface polarization is caused to produce the potential difference, the electrons are driven to directionally transfer from the MoS2 with the low work function to the FeOCl with the high work function on the interface, and the electron density and the structure of the Fe site are regulated so as to substantially improve the catalytic activity and achieve the purpose of efficiently degrading the pollutants in the water.

A semiconductor memory device and method for making the same. The semiconductor memory device includes an active layer spaced apart from a substrate, extending in a direction parallel to the substrate, and including a channel; a bit line extending in a vertical direction to the substrate and contacting a first end portion of the active layer; a capacitor contacting a second end portion of the active layer; a word line including a high work function electrode adjacent to the bit line and a low work function electrode adjacent to the capacitor; a first gate dielectric layer disposed between the low work function electrode and the active layer; and a second gate dielectric layer disposed between the high work function electrode and the active layer, the second gate dielectric layer being thinner than the first gate dielectric layer.

The invention provides a semiconductor structure. The semiconductor structure comprises a substrate, a character line and a dielectric layer. The word line is embedded in the substrate, the word line comprises a high work function layer and a low work function layer on the high work function layer, and the work function of the high work function layer is larger than that of the low work function layer. The dielectric layer is arranged between the substrate and the character line, and the dielectric layer comprises a first part and a second part. The first portion is between the substrate and the high work function layer. The second portion is between the substrate and the low work function layer, wherein a thickness of the second portion is greater than a thickness of the first portion. The semiconductor structure improves the performance of the word line. An electric field between a grid electrode of a word line and other elements which can be arranged on the word line can be reduced, so that the interference of the electric field on the performance of the word line is reduced. The gate-induced drain leakage current in the semiconductor structure can be reduced. No air gap is used for replacing the dielectric material, so that the dielectric constant drop caused by the air gap can be avoided, and the drop of the control of the grid electrode of the word line when the word line is operated is prevented.

This invention belongs to the field of semiconductor devices and micro / nanoelectronics technology, and discloses a CNTFET based on MoTi alloy contacts and its fabrication method. The CNTFET includes a substrate, a gate electrode, a gate dielectric layer, a carbon nanotube channel, and source and drain electrodes, wherein the source and drain electrodes are MoTi alloys or multilayer metal structures coated with MoTi layers. By controlling the Mo / Ti atomic ratio and optimizing deposition process conditions, this invention constructs a contact structure with tunable work function, high oxidation resistance, and excellent thin film quality, effectively reducing the Schottky barrier between the metal and carbon nanotubes, and achieving stable near-ohmic contacts. This device overcomes the shortcomings of existing technologies such as easy oxidation of low work function metals like Sc and Y, poor interface stability, and insufficient process compatibility. It significantly reduces contact resistance and improves the N-type conductivity stability, on-state current, and long-term reliability of the device in air environments, making it suitable for the integration of high-performance carbon-based logic devices and next-generation micro / nanoelectronic systems.

Pixels in an organic light-emitting diode (OLED) display may have optical cavities defined by a partially transparent cathode layer and a reflective anode structure. Light at a wavelength emitted by a pixel may form a standing wave between the anode and the cathode. The standing wave may have an upper antinode and a lower antinode. Pixels of different colors may have emissive layers aligned with different antinodes. The OLED layers for the pixels may include an electron transport layer that is doped with a low work function material. The cathode may include one or more layers of transparent conductive oxide and / or metal. The cathode may be shorted to a metal mesh and / or a conductive cutting structure to decrease resistance.

The invention provides a semiconductor structure. The semiconductor structure includes a substrate and a word line. A word line is embedded in a substrate, the word line including a high work function layer and a low work function layer on the high work function layer, where an average work function of the high work function layer is greater than an average work function of the low work function layer, the low work function layer including a lower portion and an upper portion on the lower portion, and an average grain size of the lower portion is smaller than an average grain size of the upper portion. The semiconductor structure improves the performance of the word line, such as reducing current leakage, reducing drain leakage current caused by a gate, increasing dopants in the word line, reducing resistance and the like.

To provide a semiconductor device that can reduce contact resistance.SOLUTION: A semiconductor device according to an embodiment comprises: a semiconductor part that has a first semiconductor layer, a second semiconductor layer provided on the first semiconductor layer, and a third semiconductor layer provided in a first trench of the second semiconductor layer; a first electrode that is provided on a rear face of the first semiconductor layer; a first metal film that is in contact with the second semiconductor layer in the first trench; a second metal film that is in contact with the third semiconductor layer and the first metal film in the first trench; and a second electrode that is in contact with the second metal film in the first trench. The first metal film includes a high work function metal, and the second metal film includes a low work function metal having a lower work function than the first metal film.SELECTED DRAWING: Figure 1

An apparatus comprises gate structures in a substrate, the gate structures comprising a metal material and a low work function material adjacent to the metal material. Cell capacitors are electrically coupled to source / drain regions of the substrate and bit lines are electrically coupled to other source / drain regions of the substrate. Contacts extend into the low work function material of the gate structures, the low work function material and materials surrounding the contacts do not comprise a polysilicon material. Additional apparatus and methods of forming the apparatus are disclosed.

This technology generally relates to vertical cell array transistors (VCATs) and methods for forming such VCATs. A VCAT may include one or more bit lines arranged in a first horizontal direction, one or more word lines arranged in a second horizontal direction, and one or more channels, each extending vertically substantially orthogonal to the first and second horizontal directions such that one or more bit lines intersect the source / drain regions of one or more channels, and one or more word lines intersect the gate regions of one or more channels. The VCAT includes cases where at least one of the one or more word lines includes a first section adjacent to the source / drain region and a second section adjacent to the gate region. The second section includes a high work function material, and the first section includes a low work function material.

The invention discloses a method for improving the performance of a perovskite radiation detector and the perovskite radiation detector, and relates to the field of semiconductor radiation detectors. Comprising the steps that a first voltage is applied to first metal of the perovskite radiation detector, a second voltage is applied to second metal of the perovskite radiation detector, the voltage difference between the first voltage and the second voltage is hundred volts, the second voltage is larger than the first voltage, the duration of applying the voltage to the two ends of the metal is a first duration, the first duration is an hour-level duration, and the second duration is a second duration; wherein the first metal is a high work function metal, and the second metal is a low work function metal. According to the method for improving the performance of the perovskite radiation detector, the dark current of the detector is effectively reduced, the carrier collection efficiency of the detector is improved, the energy resolution of the detector is improved, and the yield of the high-performance perovskite radiation detector is improved.

A semiconductor device includes: a trench formed in a substrate; a gate dielectric layer covering sidewalls and a bottom surface of the trench; a first gate electrode gap-filling a bottom portion of the trench over the gate dielectric layer; a second gate electrode including a metal nitride which is the same as the first gate electrode over the first gate electrode and doped with a low work function adjusting element; a buffer layer covering a top surface of the second gate electrode and the gate dielectric layer exposed over second gate electrode; and a capping layer gap-filling the other portion of the trench over the buffer layer.

This application provides a semiconductor device and its fabrication method, as well as an electronic device, relating to the field of semiconductor technology, capable of reducing the subthreshold swing of transistors. The semiconductor device includes a transistor. The transistor includes a channel, a source, and a drain; the source and drain are disposed at opposite ends of the channel; a first intercalation layer is disposed between the source and the channel, and the first intercalation layer is in contact with both the source and the channel. The channel is made of a lightly doped semiconductor or an intrinsic semiconductor. The drain is made of a heavily doped semiconductor. The source is made of a P-type heavily doped semiconductor; wherein, the first intercalation layer is made of a high work function material, and the Fermi level of the high work function material is no more than 1 / 3 of the band gap of the channel semiconductor; or, the source is made of an N-type heavily doped semiconductor; the first intercalation layer is made of a low work function material, and the Fermi level of the low work function material is no more than 1 / 3 of the band gap of the channel semiconductor.

The invention relates to a two-dimensional JFET device and a manufacturing method thereof. The two-dimensional JFET device comprises: an insulating substrate; the few-layer two-dimensional ferroelectric semiconductor film is located on the surface of the insulating substrate; the two-dimensional semi-metal thin film is located in the middle area of the surface of the few-layer two-dimensional ferroelectric semiconductor thin film; the metal electrodes are divided into a source electrode, a drain electrode and a gate electrode, the source electrode and the drain electrode are located on the surfaces of the few-layer two-dimensional ferroelectric semiconductor films on the two sides of the two-dimensional semimetal film respectively, and the gate electrode is located on the surface of the two-dimensional semimetal film. According to the two-dimensional JFET device, the high conductivity of the two-dimensional semimetal and the spontaneous polarization, adjustable and controllable characteristics, low work function, no dangling bond and other characteristics of the two-dimensional ferroelectric semiconductor material are utilized, the Schottky barrier height of a junction region and the working voltage range of the device are reduced, the voltage drop sharing phenomenon is avoided, and the device reliability is improved. And nearly ideal sub-threshold swing and accurate control on channel conductivity are realized.

A solar cell comprises a first anti-reflection layer, a passivation layer, an electrode emission layer, a silicon-based bottom layer, a tunneling oxide layer, a doped polycrystalline silicon layer and a second anti-reflection layer, which are stacked, wherein a first electrode and a second electrode are respectively provided on the first anti-reflection layer and the second anti-reflection layer, a low-work-function conductive layer is provided in the doped polycrystalline silicon layer, and the low-work-function conductive layer is adjacent to the second electrode.

The present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate, a word line, and a dielectric layer. The word line is embedded in the substrate and includes a high work function layer and a low work function layer on the high work function layer, in which a work function of the high work function layer is larger than a work function of the low work function layer. The dielectric layer is between the substrate and the word line, in which the dielectric layer includes a first portion and a second portion. The first portion is between the substrate and the high work function layer. The second portion is between the substrate and the low work function layer, in which a thickness of the second portion is larger than a thickness of the first portion.

An artificial synapse device is provided. The artificial synapse device comprises: a substrate; a gate electrode disposed on the substrate; an insulating layer disposed on the substrate to cover the gate electrode; a weight control layer disposed on the insulating layer and capable of trapping or de-trapping charges by a voltage applied to the gate electrode; a semiconductor layer disposed on the weight control layer and including a two-dimensional semiconductor material; a source electrode disposed to be in contact with one side of the semiconductor layer and including a metal having a relatively low work function; and a drain electrode disposed to be in contact with the other side of the semiconductor layer and including a metal having a relatively high work function, wherein both a current flowing from the source electrode toward the drain electrode and a current flowing from the drain electrode toward the source electrode can be generated.