43results about How to "Lower Schottky Barrier Height" patented technology

A thin film transistor, a method of manufacturing the same, and a flat panel display device having the same use an oxide semiconductor as an active layer, wherein the thin film transistor includes: an oxide semiconductor layer formed on a substrate and having a channel region, a source region, and a drain region; a gate electrode insulated from the oxide semiconductor layer by a gate insulating layer; an ohmic contact layer formed on the source region and the drain region of the oxide semiconductor layer; and a source electrode and a drain electrode coupled to the source region and the drain region through the ohmic contact layer, the ohmic contact layer being formed of a metal having a lower work function lower than work functions of the source electrode and the drain electrode.

A tunneling injection based Schottky source/drain memory cell comprising: a first semiconductor layer with a first conductivity type overlying an insulating layer, wherein the first semiconductor acts as a body region; a gate dielectric overlying the semiconductor layer; a gate electrode overlying the gate dielectric; a pair of spacers on sides of the gate electrodes; and a first Schottky barrier junction formed on a source region and a second Schottky barrier junction formed on a drain region on opposing sides of the body region. The source and the regions have an overlapping portion with the gate electrode and length of overlapping portion is preferably greater than about 5 Å. Interfacial layers are formed between the first and the second Schottky barrier regions.

The embodiments of the present invention provide a Ge-based NMOS device structure and a method for fabricating the same. By using the method, double dielectric layers of germanium oxide (GeO₂) and metal oxide are deposited between the source/drain region and the substrate. The present invention not only reduces the electron Schottky barrier height of metal/Ge contact, but also improves the current switching ratio of the Ge-based Schottky and therefore, it will improve the performance of the Ge-based Schottky NMOS transistor. In addition, the fabrication process is very easy and completely compatible with the silicon CMOS process. As compared with conventional fabrication method, the Ge-based NMOS device structure and the fabrication method in the present invention can easily and effectively improve the performance of the Ge-based Schottky NMOS transistor.

An InP high electron mobility transistor (HEMT) structure in which a gate metal stack includes an additional thin layer of a refractory metal, such as molybdenum (Mo) or platinum (Pt) at a junction between the gate metal stack and a Schottky barrier layer in the HEMT structure. The refractory metal layer reduces or eliminates long-term degradation of the Schottky junction between the gate metal and the barrier layer, thereby dramatically improving long-term reliability of InP HEMTs, but without sacrifice in HEMT performance, whether used as a discrete device or in an integrated circuit.

An embodiment of the invention provides a germanium-based NMOS device and a method for fabricating the same, which relates to fabrication process technology of an ultra-large-scale-integrated (ULSI) circuit. The germanium-based NMOS device has two dielectric layer interposed between a metal source/drain and a substrate. The bottom dielectric layer includes a dielectric material having a high pinning coefficient S such as hafnium oxide, silicon nitride, hafnium silicon oxide or the like, and the top dielectric layer includes a dielectric material having a low conduction band offset ΔE_C such as titanium oxide, gallium oxide, strontium titanium oxide or the like. According to the method, Fermi level pinning effect can be alleviated, electron barrier height can be lowered, and thus performance of the germanium-based Schottky NMOS device can be improved. Compared with a conventional single dielectric layer such as aluminum oxide (Al₂O₃), Schottky barrier height can be lowered while low source/drain resistances can be maintained, and thus performance of the device can be significantly improved.

Provided is a semiconductor device that can reduce the contact resistance, has a small current collapse, and can improve the pinch-off characteristic upon a high-frequency operation. A field effect transistor using a wurtzite (having (0001) as the main plane) type III-nitride semiconductor includes: a substrate (101); an undercoat layer (103) of a first III-nitride semiconductor; and a carrier travel layer (104) of a second III-nitride semiconductor. The undercoat layer (103) (101) and the carrier travel layer (104) is formed on the substrate in this order. The field effect transistor includes source/drain electrodes (105, 106) in ohmic contact, and a gate electrode (107) in Schottky contact directly or via another layer on the carrier travel layer (104). The undercoat layer (103) has an average lattice constant greater than that of the carrier travel layer (104) and a band gap greater than that of the carrier travel layer (104).

The field-effect semiconductor device includes a channel layer; a contact layer; a semiconductor structure having an electron-affinity different from those of the channel layer and the contact layer and formed between the channel layer and the contact layer; an ohmic electrode formed on the contact layer; and a Schottky electrode formed on the semiconductor structure. The junction face between the channel layer and the semiconductor structure and the junction face between the contact layer and the semiconductor structure are iso-type heterojunctions.

Disclosed are a semiconductor structure and a formation method thereof. The formation method comprises the steps of forming a base, wherein the base comprises a substrate, a gate structure positionedon the substrate, source and drain doped regions positioned in the base on the two sides of the gate structure, and an interlayer dielectric layer positioned on the base and for covering the top of the gate structure, and the substrate comprises a first region for forming a P type device and a second region for forming an N type device; forming a first contact opening for exposing the source and drain doped regions in the interlayer dielectric layer on the two sides of the gate structure; performing a P type dopant segregated schottky doping process on the source and drain doped regions exposed from the first contact opening in the first region and the second region; forming a metal silicide layer at the bottom of the first contact opening; and forming a first contact hole inserting plug in the first contact opening. By adjusting the doping concentration of the source and drain doped regions in the second region, use of a photomask can be avoided when the P type dopant segregated schottky doping process is performed, so that lowering of the process cost is realized, and the N type device suffers from relatively low influence.

The present invention provides a chip epitaxial structure of a low-resistance LED and a preparation method thereof. The structure comprises a substrate, a buffer layer, an N-type semiconductor material layer, a multi-quantum well layer, a P-type semiconductor material layer, a current expanding layer and a P-type Ohmic electrode in order in an epitaxial growth direction. The current expanding layer and the N-type semiconductor material layer are respectively embedded with insulation layers. The epitaxial structure further comprises an N-pole Ohmic contact layer and an N-type Ohmic electrode; the N-pole Ohmic contact layer is located on part of the N-type semiconductor material layer; and the N-type Ohmic electrode is located on the N-pole Ohmic contact layer. The preparation method is simple, high in operability and low in cost, can increase the injection efficiency of carriers to a certain extent on the basis of further reduction of the Ohmic contact resistance, and greatly improves the implementation performances.

The present disclosure provides a semiconductor structure in accordance with some embodiments. The semiconductor structure includes a semiconductor feature, a passivation layer that includes indium sulfide formed over a surface of the semiconductor feature. More particularly, the surface of the semiconductor feature comprises indium-based III-V compound semiconductor material.

The invention discloses a semiconductor device and a manufacturing method thereof. The method comprises the following steps of: providing a semiconductor substrate; forming a pseudo-gate region and side walls of the pseudo-gate region on the semiconductor substrate; forming epitaxial layers on the semiconductor substrate on the two sides of the pseudo-gate region to form source and drain regions, wherein the epitaxial layers are made of metal silicide, metal germanide or metal silicon germanide; forming interlayer dielectric layers to cover the epitaxial metal silicide layers of the source and drain regions; removing the pseudo-gate region to form an opening; and forming a gate dielectric layer on the inner walls of the opening, and forming a metal gate electrode on the gate dielectric layer to fill the opening. Before a substitute gate is formed, the epitaxial layers are formed on the semiconductor substrate on the two sides of the gate region and cover the whole source and drain regions of a Schottky barrier field effect transistor device, and the height of a Schottky barrier between the epitaxial source and drain regions and a channel is effectively reduced, so that the source and drain parasitic resistance of the device is obviously reduced, and the performance of the device is improved.

The invention relates to a semiconductor device and a formation method thereof. The formation method comprises that pre-non-crystallization processing is carried out on a source-drain doped region exposed out of the bottom of a first through hole; after pre-non-crystallization processing, a protection layer is formed on the source-drain doped region exposed out of the bottom of the first through hole; a pattern layer filling the first through hole is formed on the protection layer, and the pattern layer positioned in the top of a dielectric layer includes an opening; the dielectric layer is etched along the opening till the top of a gate structure is exposed, and a second through hole out of which the top of the gate structure is exposed is formed in the dielectric layer; the pattern layeris removed in the oxygen-containing atmosphere; the protection layer is removed; a metal contact layer is formed on the source-drain doped region exposed out of the bottom of the first through hole;and a conductive plug filling the first through hole is formed on the metal contact layer, and a gate plug filling the second through hole is formed at the same time. The contact resistance between the source-drain doped region and the metal contact layer is reduced, and the electrical performance of the semiconductor device is improved.

A method for for a semiconductor structure includes for a substrate including a PMOS region, forming a gate structure on that substrate, forming a P-type doped epitaxial lay in the substrate on both sides of the gate structure of the PMOS region, forming a silicon layer on the surface of the P-type doped epitaxial layer, and forming an interlayer dielectric layer covering the top of the gate structure on the substrate; Contact openings exposing the silicon layer are formed in the interlayer dielectric layers on both sides of the gate structure of the PMOS region. The silicon layer is doped bymetal segregation Schottky method; Forming a metal layer at the bottom of the contact opening; The metal layer and the silicon layer are reacted to form a metal silicide layer by annealing treatment;A contact hole plug is formed in the contact opening. The solid solubility of metal segregated Schottky doped ions in the metal silicide layer is lower than that in the silicon layer, Therefore, dopedions precipitate from the metal silicide layer and segregate at the interface between the metal silicide layer and the P-type doped epitaxial layer, thus lowering the Schottky barrier height of PMOS,thereby reducing the contact resistance of the PMOS region.

The invention discloses a silicon heterojunction solar cell emitter, which comprises: an n-type silicon substrate having an emitter surface; a first intrinsic passivation layer formed on the emitter surface; a p-type silicon doped layer formed on the first intrinsic passivation layer; and an adsorption atom layer formed on the p-type silicon doped layer, wherein the adsorption atom layer comprisesadsorption atoms which are deposited on the surface of the p-type silicon doped layer and form a positive dipole moment potential field with the silicon atoms on the surface of the p-type silicon doped layer. The invention also discloses a preparation method of the silicon heterojunction solar cell emitter and a silicon heterojunction solar cell. The height of the Schottky barrier of the p-type silicon doped layer and the TCO interface of the emitter to the hole of the n-type silicon substrate is low, and the fill factor and the conversion efficiency of the silicon heterojunction solar cell are high.

A method of forming a fin-type field effect transistor comprises: forming a first etch hole that exposes a first source region and a first drain region surface in a dielectric layer, and a second etch hole exposing a second source region and a second drain region; forming a second oxide layer containing aluminum on the side wall and the bottom surface of the second etch hole; forming a first oxide layer containing sulfur or selenium on the side wall and the bottom surface of the first etch hole; performing annealing such that sulfur ions or selenium ions in the first oxide layer containing sulfur or selenium diffuse into the first source region and the first drain region at the bottom of the first etch hole, aluminum ions in the second oxide layer containing aluminum diffuse into the second source region and the second drain region at the bottom of the second etch hole; and removing the first oxide layer and the second oxide layer, forming a first metal silicide on the surfaces of the first source region and the first drain region, and forming a second metal silicide layer on the surfaces of the second source region and the second drain region. The method of the present invention reduces the Schottky barrier height of the fin-type field effect transistor source-drain region.

The invention provides an electrode of a p-type gallium nitride-based device as well as a preparation method and application thereof. The electrode comprises a nickel oxide layer, a platinum layer and a gold layer which are sequentially stacked, wherein the nickel oxide layer is of a P-type structure, the platinum layer is located between the P-type nickel oxide layer and the gold layer, and the nickel oxide layer is an ohmic contact layer of the p-type gallium nitride-based device. The electrode of the p-type gallium nitride-based device is used for a source electrode and a drain electrode of the p-type gallium nitride-based device, more carriers flow between metal and a semiconductor by introducing a Schottky barrier height of the P-type NiO layer, the transition metal and the semiconductor interface, and meanwhile, by means of ultrahigh vacuum heat treatment, the problem that the height of the Schottky barrier is increased due to a Ga2O3 pollution layer is solved, the ohmic contact resistance of the source electrode and the drain electrode of the device is reduced, the performance of a p-type gallium nitride-based transistor is improved, the p-type gallium nitride-based device can play a greater role in a CMOS circuit, and the defect is changed into the advantage.

The present invention provides a Schottky electrode for a nitride semiconductor device having a high barrier height, a low leak current performance and a low resistance and being thermally stable, and a process for production thereof. The Schottky electrode for a nitride semiconductor has a layered structure that comprises a copper (Cu) layer being in contact with the nitride semiconductor and a first electrode material layer formed on the copper (Cu) layer as an upper layer. As the first electrode material, a metal material which has a thermal expansion coefficient smaller than the thermal expansion coefficient of copper (Cu) and starts to undergo a solid phase reaction with copper (Cu) at a temperature of 400° C. or higher is employed.

The invention discloses a semiconductor device manufacturing method which comprises the steps of forming a grid stack structure on a substrate containing silicon; depositing nickel metal layers on the substrate and the grid stack structure; primarily annealing to enable silicon in the substrate to react with the nickel metal layer to form nickel-rick phase metal silicide; injecting ions to enable doping ions to be injected into the nickel-rich phase metal silicide; secondarily annealing to enable the nickel-rick phase metal silicide to be converted into nickel metal silicide source leakage and simultaneously forming separation and condensation zone at the interface between the nickel metal silicide source leakage and the substrate. According to the semiconductor device manufacturing method, doping ions are injected into the nickel-rick phase metal silicide to be annealed, solid solubility of the doping ions is improved to form the high-concentration doping ion separation and condensation zone, schottky barrier height between the nickel metal silicide and a silicon channel is effectively reduced, and driving capacity of the device is improved.