Semiconductor structure and forming method thereof

Abstract

A method for for a semiconductor structure includes for a substrate including a PMOS region, forming a gate structure on that substrate, forming a P-type doped epitaxial lay in the substrate on both sides of the gate structure of the PMOS region, forming a silicon layer on the surface of the P-type doped epitaxial layer, and forming an interlayer dielectric layer covering the top of the gate structure on the substrate; Contact openings exposing the silicon layer are formed in the interlayer dielectric layers on both sides of the gate structure of the PMOS region. The silicon layer is doped bymetal segregation Schottky method; Forming a metal layer at the bottom of the contact opening; The metal layer and the silicon layer are reacted to form a metal silicide layer by annealing treatment;A contact hole plug is formed in the contact opening. The solid solubility of metal segregated Schottky doped ions in the metal silicide layer is lower than that in the silicon layer, Therefore, dopedions precipitate from the metal silicide layer and segregate at the interface between the metal silicide layer and the P-type doped epitaxial layer, thus lowering the Schottky barrier height of PMOS,thereby reducing the contact resistance of the PMOS region.

Description

Technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a semiconductor structure and a method of forming the same. Background technique [0002] With the continuous development of integrated circuit manufacturing technology, the critical size of the device is continuously reduced, and many problems have appeared accordingly. For example, the contact resistance between the contact hole plug and the doped epitaxial layer increases, which causes the response speed of the device to decrease, the signal is delayed, and the driving current decreases, which in turn leads to the performance degradation of the semiconductor device. [0003] In order to reduce the contact resistance between the contact hole plug and the doped epitaxial layer, a metal silicide process is introduced. The metal silicide has a lower resistivity and can significantly reduce the contact resistance, thereby increasing the driving current. [0004] At present, for t...

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Problems solved by technology

[0004] At present, for the PMOS (Metal Oxide Semiconductor) area and the NMOS area, the metal silicide material used is the same, but the effect of the metal silicide on reducing the contact resistance of the PMOS area and the NMOS area is different.

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