13 results about "Salicide" patented technology

The chip includes a first epitaxial (epi) layer, a second epi layer, a gate between the first epi layer and the second epi layer, and one or more channels coupled between the first epi layer and the second epi layer, wherein the one or more channels pass through the gate. The chip also includes a first salicide layer formed on a bottom surface of the first epi layer.

A semiconductor device includes a semiconductor layer including a trench, wherein the trench is adjacent a mesa, a first metal silicide layer on a top portion of the mesa, and a second metal silicide layer on a bottom portion of the trench. The first metal silicide layer has a thickness that is no more than about 1 to 1.5 times greater than a thickness of the second metal silicide layer. Related methods of forming a semiconductor device are disclosed.

Apparatus and methods for shielded-gate trench power MOSFETs are disclosed herein. The power MOSFETs are fabricated using a self-aligned gate poly silicide to achieve low gate resistance. Accordingly, the power MOSFETs can be used in high speed applications operating with fast transistor switching speeds. Moreover, the self-aligned gate poly silicide processing can be achieved in relatively few processing steps, and thus can avoid the cost and / or complexity associated with conventional silicidation techniques for trench power MOSFETs. In particular, silicidation can include applying a silicide that is self-aligned to a gate oxide without an additional mask.

A semiconductor device structure is provided. The semiconductor device structure includes a fin spacer alongside a fin structure, a source / drain structure over the fin structure, and a salicide layer along a surface of the source / drain structure. A bottom portion of the salicide layer is in contact with the fin spacer. The semiconductor device structure also includes a capping layer over the salicide layer. A portion of the capping layer directly below the bottom portion of the salicide layer is in contact with the fin spacer. The semiconductor device structure also includes a dielectric layer over the capping layer. The dielectric layer is made of a different material than the capping layer.

The present application relates to the technical field of semiconductor manufacturing, in particular to a method for removing unreacted nickel platinum alloy in self-aligned silicide, comprising the following steps: a) providing a wafer with a metal layer on the surface; the metal layer comprises nickel platinum alloy; b) forming a porous titanium dioxide layer on the surface of the metal layer; c) removing the metal layer at room temperature by using a photocatalytic reaction; d) removing the porous titanium dioxide layer by using a hydrogen peroxide complexation reaction; e) sequentially performing impurity removal, water washing and drying on the surface of the wafer to obtain self-aligned silicide. Compared with the prior art, the method for removing unreacted nickel platinum alloy in self-aligned silicide provided by the present application realizes overall good interaction by using specific process steps and conditions, can remove unreacted nickel platinum alloy in self-aligned silicide at room temperature, avoids the influence of high-temperature wet process on the thermal stability of nickel silicide compound, and does not lose nickel silicide, thereby improving the process stability of self-aligned silicide, and further improving the product yield.

The application provides a method for improving the performance of a CMOS image sensor, which comprises the following steps: forming an N well and a P well on a P substrate; forming a first N+ region and a second N+ region in the P well near the upper surface of the P substrate; forming a transfer tube gate between the N well and the P well and a reset tube gate between the first N+ region and the second N+ region on the upper surface of the P substrate; forming an amorphous layer on the side of the N well shallow region near the transfer tube gate; forming a Pin barrier layer on the lower surface of the amorphous layer; and forming a self-aligned silicide barrier layer, which covers the upper surface of the amorphous layer and continuously extends to the surface of the transfer tube gate, the upper surface of the first N+ region, the surface of the reset tube and the upper surface of the second N+ region. The method can reduce the plasma-induced damage caused by subsequent processes, reduce the generation of dark current and white pixels, improve the full well capacity of the photodiode and reduce the dark current generated by the defects at the interface between Si and silicon oxide.

The invention relates to the technical field of semiconductor manufacturing, in particular to a method for removing unreacted nickel-platinum alloy in self-aligned silicide, which comprises the following steps of: a) providing a wafer with a metal layer on the surface; the metal layer comprises nickel platinum alloy; b) forming a porous titanium dioxide layer on the surface of the metal layer; c) removing the metal layer at normal temperature by adopting a photocatalytic reaction; d) removing the porous titanium dioxide layer by adopting a hydrogen peroxide complexation reaction; and e) sequentially carrying out impurity removal, water washing and drying on the surface of the wafer to obtain the self-aligned silicide. Compared with the prior art, the method for removing the unreacted nickel-platinum alloy in the self-aligned silicide, provided by the invention, adopts specific process steps and conditions, realizes relatively good overall interaction, can remove the unreacted nickel-platinum alloy in the self-aligned silicide at normal temperature, avoids the influence of a high-temperature wet process on the thermal stability of the nickel-silicon compound, and improves the yield of the nickel-silicon compound. And the nickel silicide is not lost, so that the stability of the self-aligned silicide process is improved, and the product yield is further improved.

The invention provides a method for forming a self-aligned silicide barrier layer. The method comprises the following steps: sequentially depositing a bottom dielectric layer, an etching stop layer and a top dielectric layer on a substrate to form a composite film layer; defining a retaining region of the barrier layer through photoetching; etching the top dielectric layer and stopping on the etching stop layer; carrying out adhesive wet cleaning to remove the residual top dielectric layer in the narrow gap area; removing the photoresist; removing the exposed etching stop layer; heat treatment; and removing the exposed bottom dielectric layer. According to the method, the photoresist is utilized to protect the film layer in the LDMOS region from thickness loss while the residual dielectric layer in the CMOS narrow-spacing region is thoroughly removed through the adhesive wet cleaning process, so that the contradiction between the thick film layer requirement and fine-spacing cleaning is solved, and the compatibility of the pressure resistance of the high-voltage device and the contact hole process is ensured.

The application provides a preparation method of a flash memory device, comprising the following steps: providing a substrate with a stacked floating gate layer, an ONO layer and a control gate layer formed thereon, the substrate is provided with a groove, and the groove is provided with a side wall structure; forming a conductive contact layer by using a self-aligned silicide process; performing selective etching on the side wall structure by using an SPT process; and forming an interlayer insulating medium layer. The application performs selective etching on the side wall structure by using an SPT (stress proximity technique) process. Since the etching selectivity of the SPT process on some material layers (silicon nitride layers) is high, the filling of the interlayer insulating medium layer in the groove is improved by performing targeted thinning on some material layers in the side wall structure after the formation of the conductive contact layer (self-aligned silicide process), so that the filling of the interlayer insulating medium layer can be improved without affecting the electrical performance of the device, the void defects are avoided, and the device yield is further improved.

The invention provides a method for forming a CMOS (Complementary Metal Oxide Semiconductor) image sensor integrated with a stress memory technology. The method comprises the following steps: depositing a first oxide layer and a stress medium layer on the surface of a substrate subjected to source and drain injection; retaining the stress medium layer of the N-type logic region and removing other regions; performing rapid thermal annealing to generate a stress memory effect, and then removing the residual layer; depositing a second oxide layer and a nitride layer; and reserving the laminated structure of the pixel region through photoetching, and forming a metal silicide in the logic region. By optimizing the stress memory cycle and the self-aligned silicide blocking process, the performance of the logic NMOS device is remarkably improved, the dark current of the pixel area is effectively inhibited, and both the image quality and the circuit speed are considered.

The invention provides a transistor. The transistor includes a well region arranged in a substrate, a gate structure arranged on the well region, a gate oxide layer, wherein a first portion of the gate oxide layer is thicker than a second portion of the gate oxide layer, a first doped region and a second doped region arranged in the well region, wherein along the horizontal direction, the distance between the first doped region and the first portion of the gate oxide layer is greater than the distance between the second doped region and the second portion of the gate oxide layer, and a salicide block located on the substrate and at one side of the gate structure, wherein the salicide block is located between the first portion of the gate oxide layer and the first doped region.

The chip includes a first epitaxial (epi) layer, a second epi layer, a gate between the first epi layer and the second epi layer, and one or more channels coupled between the first epi layer and the second epi layer, wherein the one or more channels pass through the gate. The chip also includes a first salicide layer formed on a bottom surface of the first epi layer.

A semiconductor cascade equipment includes a physical co-deposition (PCD) device and a rapid thermal annealing (RTU) device. An oxygen-free chamber is located between the PCD and RTU devices, with valves installed at both ends of the oxygen-free chamber where they connect to the PCD and RTU devices. A wafer transfer structure is located at the bottom of the oxygen-free chamber, comprising a slide rail, a vacuum chuck, and a robotic arm mounted on the slide rail. The robotic arm transfers wafers from the wafer cassette of the PCD device to the vacuum chuck, or from the vacuum chuck to the wafer cassette of the RTU device. This invention effectively reduces the risk of cobalt being oxidized to cobalt oxide, improving the quality of self-aligned silicides. It also eliminates the need for a titanium nitride deposition chamber, reducing the titanium nitride deposition run time and the interval between cobalt deposition and RTU, thus increasing production line efficiency.