1287 results about "Electrostatic discharge" patented technology

The invention discloses an electrostatic discharge immunity automatic test management method and system. The method comprises the steps that real-time environment state data in an experimental environment are collected in real time, then redundancy mechanism and check algorithm processing is carried out, and discharge parameters of an electrostatic generator are calculated and adjusted in real time through a multi-dimensional nonlinear self-adaptive control algorithm; performing electrostatic discharge based on the adjusted discharge parameters of the electrostatic generator, generating electrostatic interference of specified parameters, simulating an actual scene of electrostatic discharge, further transmitting a generated electrostatic discharge interference signal to test equipment, and generating a corresponding response signal; the response signals and the interference signals are preprocessed and then subjected to deep spectrum analysis, key features are extracted, and the immunity of the test equipment is intelligently evaluated through a neural network model. The control precision of the electrostatic generator is improved, the electrostatic generator can dynamically adapt to the change of the experimental environment, and it is ensured that the discharging condition is always in the optimal state.

The invention relates to the technical field of operation control, in particular to an unattended operation crucible loading and unloading operation control system and method based on visual processing, and the method comprises the following steps: monitoring a static accumulation value in a graphite powder fluidization conveying process in real time through a distributed static sensor; when the static accumulation value exceeds a safety threshold value, pulse type ion wind neutralization treatment is triggered, and a static balance material flow is generated; the dynamic alignment deviation of the stock bin and the crucible opening is calculated; the stepping angle and the rotating speed of a spiral auger in the stock bin are controlled based on the dynamic alignment deviation, and an axial vibration field is synchronously applied in the discharging process; the position of an air gap in a material is predicted based on a convolutional neural network, and a vacuum negative pressure value is dynamically adjusted to form a gradient suction mode. According to the device, the risks of powder agglomeration, conveying pipeline blockage or electrostatic discharge caused by electrostatic accumulation are effectively prevented, the safety of the conveying process is ensured, and meanwhile, the flowing stability of graphite powder is optimized.

An anti-interference bidirectional electrostatic protection circuit provided by the present invention comprises a first electrostatic discharge path and a second electrostatic discharge path which are arranged in parallel, and the first electrostatic discharge path comprises a first electrostatic discharge unit and a second electrostatic discharge unit which are arranged in a stacked manner. The second electrostatic discharge path comprises a third electrostatic discharge unit and a fourth electrostatic discharge unit which are stacked, the first electrostatic discharge unit and the second electrostatic discharge unit are arranged in opposite directions, the capacitance value of the first electrostatic discharge unit is larger than that of the second electrostatic discharge unit, and the capacitance value of the third electrostatic discharge unit is larger than that of the fourth electrostatic discharge unit. The third electrostatic discharge unit and the fourth electrostatic discharge unit are arranged in opposite directions, the capacitance value of the third electrostatic discharge unit is larger than that of the fourth electrostatic discharge unit, and the first electrostatic discharge unit and the third electrostatic discharge unit are arranged in opposite directions. Through circuit structure and layout optimization, accumulated charges on an internal floating node can be discharged.

A display panel and a display device are provided, the first signal line extends from the display region to the electrostatic discharge region in a first direction, and provides a first display signal to the sub-pixels; the electrostatic discharge units are arranged in the first direction, each electrostatic discharge unit includes a sub electrostatic discharge unit, each sub electrostatic discharge unit includes an electrostatic discharge circuit and a first conductor, the electrostatic discharge circuit is connected to the first signal line and the first conductor, and charges on the first signal line move towards the first conductor; the electrostatic discharge units include two adjacent electrostatic discharge units in a second direction perpendicular to the first direction, orthographic projections of the two adjacent electrostatic discharge units on a plane parallel to the first direction are not overlapped, and on a plane parallel to the second direction are overlapped.

A system and method for an electrostatic discharge (ESD) clamp circuit containing a disable circuit to selectively disable a discharge circuit is disclosed. An electrostatic discharge (ESD) clamp circuit including a discharge circuit to discharge a current flow during a transient ESD voltage event; a disable input to receive a disable input signal; and a disable circuit to, based upon the disable input signal, selectively disable the discharge circuit. When the disable input signal is a first logic state, the disable circuit is to allow the discharge circuit to be enabled; and when the disable input signal is in a second logic state, the disable circuit is to disable the discharge circuit.

The invention discloses a mother substrate and a display panel using the mother substrate. The mother substrate is used for the display panel. A mother substrate for a display panel includes: a conductive ring disposed in a non-display area outside a display area and surrounding each of the display areas; and one or more dummy pixel driving circuits, the one or more dummy pixel driving circuits being disposed in a non-display area outside the display area. An electrostatic discharge (ESD) prevention structure inside the dummy pixel driving circuit may prevent defects of the display panel due to ESD occurring in a manufacturing process of the display panel.

The present disclosure provides a semiconductor device and an electrostatic discharge (ESD) clamp circuit. The semiconductor device includes a voltage divider, a cascoded inverter, and a discharge circuit. The voltage divider is electrically coupled between a power supply voltage and an output voltage of the semiconductor device. The cascoded inverter is electrically coupled to the voltage divider. The discharge circuit is electrically coupled to the cascoded inverter. The cascoded inverter is configured to turn on the discharge circuit o discharge an electrostatic discharge (ESD) current in response to an ESD event occurring on the power supply voltage or the output voltage when the semiconductor device is in an ESD mode.

An array substrate includes a display area and a notch area. The display area includes a first display sub-area and a second display sub-area spaced apart from each other by the notch area. The notch area includes an electrostatic discharge area. The array substrate includes a plurality of data lines and a plurality of scan signal lines. The plurality of data lines at least partially extend into the electrostatic discharge area. The plurality of scan signal lines cross over the electrostatic discharge area. At least a portion of the electrostatic discharge area includes a plurality of first sub-regions and a plurality of second sub-regions alternately arranged. The plurality of scan signal lines are present in the plurality of first sub-regions, and absent in the plurality of second sub-regions. The plurality of data lines are present in the plurality of second sub-regions, and absent in the plurality of first sub-regions.

The utility model relates to the technical field of detection equipment, and particularly discloses automatic detection equipment for materials, which comprises a base, and a feeding mechanism, a camera shooting mechanism, a control assembly and a limiting mechanism which are arranged on the base, the feeding mechanism is arranged below the camera shooting mechanism, the control assembly controls the feeding mechanism to move an external detection product to the camera shooting mechanism, the control assembly controls the limiting mechanism to limit the external detection product, moved to the camera shooting mechanism, of the feeding mechanism, and the control assembly regulates and controls the camera shooting mechanism to take photos or videos of the external detection product. According to the automatic detection equipment, the external plate is moved to the detection table in a non-contact mode through the accurate conveying belt, the graph scanning and collecting device and the like, damage to the external plate possibly caused by uneven force, hand sweat corrosion or electrostatic discharge and the like during manual operation is avoided, graph collection and detection are conducted in an all-around mode, and the detection efficiency is improved. The detection efficiency of the electronic plate production line is greatly improved, the labor cost is reduced, and the practicability is high.

The embodiment of the invention discloses an electrostatic discharge inspection method and device for stacked chips, equipment and a storage medium, relates to the technical field of semiconductor circuits, and can save inspection time and computing resources so as to effectively improve inspection efficiency. The method comprises the steps that to-be-inspected discharge paths of stacked chips are divided into a first type of discharge paths and a second type of discharge paths, the first type of discharge paths represent electrostatic discharge paths coinciding with those in two-dimensional electrostatic discharge inspection, and the second type of discharge paths represent electrostatic discharge paths crossing core particles; performing two-dimensional electrostatic discharge inspection on each core particle forming the stacked chip so as to cover the first type of discharge path; and based on a shortest discharge path principle, screening out a target discharge path from the second type of discharge paths to perform electrostatic discharge inspection, wherein the target discharge path represents the shortest electrostatic discharge path in the electrostatic discharge paths crossing the core particles. The method and the device are suitable for electrostatic discharge inspection scenes of semiconductor chips.

A mother substrate for a display panel and a display panel using the same are disclosed. A mother substrate for a display panel includes a conductive ring disposed in a non-display area outside the display area and surrounding each of the display areas, and one or more dummy pixel driving circuits disposed in a non-display area outside the display area. An electrostatic discharge (ESD) prevention structure inside the dummy pixel driving circuit can prevent defects of display panels due to ESD occurring in the manufacturing process of the display panel.

The present disclosure provides a semiconductor device, which includes a control circuit, a driving circuit, a voltage pull-up device, and a discharging circuit. The control circuit is coupled between a first terminal and a second terminal of the integrated circuit, and provides a first voltage at a first node. The driving circuit is electrically connected to the control circuit at the first node, and provides a trigger signal at a second node in response to an electrostatic discharge (ESD) event occurring at the first terminal or the second terminal. The voltage pull-up device is coupled between the first terminal and the first node, and configured to pull up the first voltage at the first node in response to the ESD event occurring at the first terminal. The discharging circuit is electrically connected to the second node, and coupled between the first terminal and the second terminal.

The invention discloses a surge protection circuit, which belongs to the field of semiconductor surge protection devices, and comprises a plurality of resistors, a plurality of voltage stabilizing diodes and a plurality of transistors, the first end of the first resistor is connected with a bus voltage, the first end of the first transistor and the second end of the second transistor; the second end of the first resistor is connected with the third end of the first transistor and the cathode of the first Zener diode, and the anode of the first Zener diode is connected with the cathode of the second Zener diode and the third end of the third transistor. The anode of the second voltage stabilizing diode is connected with the second end of the third resistor, the second end of the third transistor, the first end of the second transistor and the ground, the second end of the first transistor is connected with the first end of the second resistor, and the second end of the second resistor is connected with the first end of the third resistor, the first end of the third transistor and the third end of the second transistor. According to the invention, the problems of surge voltage such as electrostatic discharge, electrical fast transient pulse train, lightning stroke, peak and the like, transient voltage generated in a hot plug process and the like can be solved.

The invention discloses a visual quantitative measurement and analysis device and method for detecting the surface discharge degree of an insulating material, and relates to the field of visual quantitative detection of the surface discharge degree of the insulating material. By constructing an electrostatic discharge system, the pulse discharge process of the insulating surface under the actual operation condition is simulated, and then the surface of the insulating material is induced to discharge. A visual processing device is built, through the polarization effect between dust and charges, the surface charge distribution condition is rapidly reproduced through the dust, and equipment recording is shot. A gray-scale map working principle is applied, a gray-scale conversion and binarization processing program is written, the program is started to convert a recorded picture into a binary image only containing black and white pixel points, the number of the pixel points is counted, and the charge distribution density in an effective discharge radius is calculated through formula conversion, so that the electrostatic discharge degree is quantitatively represented. By changing environmental conditions such as humidity and air pressure, service life state evaluation of the insulation equipment and insulation detection and structure optimization work of the novel insulation equipment in a complex environment are researched.

The invention discloses a high-voltage bidirectional silicon controlled rectifier electrostatic protection device and a manufacturing method. The high-voltage bidirectional silicon controlled rectifier electrostatic protection device comprises a P-type substrate, a P-type well and a high-voltage N well, the emitter P + injection of a parasitic PNP triode and the emitter N + injection of a parasitic NPN triode in the P-type well are arranged alternately, so that the length of a transverse discharge path of the silicon controlled rectifier is reduced to the greatest extent, the square resistance of a PNPN positive feedback conduction path is greatly reduced, and the key problem that a symmetrical bidirectional silicon controlled rectifier structure cannot be effectively opened in a high-voltage window of more than 70V is solved; in addition, the layout can provide an additional parasitic NPN triode path for a silicon controlled rectifier path, the effective area of an emitter of the parasitic NPN triode and the proportion of the emitter in a silicon controlled rectifier loop are increased, and the current discharge capacity of the device is further improved. Therefore, reference can be provided for the structural design of the high-voltage symmetrical bidirectional silicon controlled rectifier electrostatic protection device, and the silicon controlled rectifier can be effectively applied to ESD protection of a high-voltage bidirectional port.

The invention relates to the technical field of soil treatment, and particularly discloses a soil micro-plastic electrostatic separation device and method.The soil micro-plastic electrostatic separation device comprises a sample pool, an electrostatic adsorption mechanism is arranged on one side of the sample pool, and the electrostatic adsorption mechanism is connected with an electrostatic discharge generator through a wire; the electrostatic adsorption mechanism comprises an adsorption plate and a connecting handle; the bottom box and the heightening frame bodies are made of wood, the height of the sample pool can be adjusted by installing the heightening frame bodies in an assembling mode, a nylon coating is arranged on the outer side of an adsorption plate and used for adsorbing micro-plastics and eradicating the risk of high-voltage electric leakage, and the height of the adsorption plate can be adjusted through an arranged supporting assembly; the particle size range of the micro-plastic covered by electrostatic adsorption is wide, compared with a traditional method, the recovery rate is remarkably improved, and the original form of the micro-plastic and the natural structure of soil are protected through normal-temperature physical separation and no reagent addition.

An electrostatic discharge semiconductor device is disclosed and comprises: a first well region of a first doping type, extending from the surface of an epitaxial layer to the surface of the substrate; a second well region and a third well region of a second doping type; a fourth well region of the second doping type; a fifth well region and a sixth well region have a first doping type; a first injection region and a second injection region, spaced apart in each well region. The second injection region in the second and third well regions is connected to a cathode, and the first and second injection regions in the fourth well region are connected to an anode. The electrostatic discharge semiconductor device enhances its electrostatic protection capability by adjusting the avalanche breakdown voltage between the floating fifth and sixth well regions and the triggering voltage of the device.

An apparatus includes a drain and a source on opposing sides of an epitaxial layer, a body region and a plurality of gates formed in the epitaxial layer, an interlayer dielectric layer over the epitaxial layer, a gate-source electrostatic discharge (ESD) diode in the interlayer dielectric layer, a source contact connected to the source and a first terminal of the gate-source ESD diode structure, a gate contact connected to the plurality of gates and a second terminal of the gate-source ESD diode structure, a drain contact on opposing sides of the epitaxial layer of the source contact, a breakdown voltage enhancement and leakage prevention structure formed underneath the gate-source ESD diode structure, wherein the breakdown voltage enhancement and leakage prevention structure comprises a body ring structure.

The described techniques address issues associated with electrostatic discharge (ESD) protection for multi-die integrated circuits (ICs). The techniques include the use of two or more semiconductor dies within a multi-die IC, which may include a first semiconductor die without ESD protection but with full ESD exposure. The first semiconductor receives ESD protection via a second semiconductor die that is integrated as part of the same package with the first semiconductor die. The second semiconductor die may be electrically more remote from ESD-exposed pins compared to the first semiconductor die. The first semiconductor die may include integrated passive devices. The second semiconductor die enables ESD protection for both semiconductor dies in the same integrated IC package.

A display panel and a display device are disclosed and, more specifically, the display panel includes a substrate including a display area where a plurality of subpixels are disposed, a gate driving circuit disposed in a non-display area outside the display area to supply a plurality of scan signals to the plurality of subpixels, an electrostatic discharge unit disposed in the non-display area, and a plurality of pads disposed in the non-display area and coupled with a plurality of signal lines electrically connected to the gate driving circuit and the electrostatic discharge unit, wherein the plurality of pads include, as sequentially disposed, a clock pad connected with a clock signal line, a first line pad connected with a first power line, an additional pad connected with an electrostatic discharge high-potential voltage line and an electrostatic discharge low-potential voltage line, and a second line pad connected with a second power line.

ElectroStatic Discharge (ESD) protection circuitry for a semiconductor chip. The ESD protection circuitry includes a first node for coupling to an I / O node of the semiconductor chip and includes a first conductive path coupled to the first node via a first diode. The first conductive path is configured to be at first voltage level higher than or equal to a voltage level of a first supply voltage. The ESD protection circuitry includes a second conductive path coupled to the first node via a second diode. The second conductive path is configured to be at second voltage level lower than or equal to a voltage level of a second supply voltage. The second supply voltage is lower than the first supply voltage. The ESD protection circuitry includes a second node for coupling to a ground node or a supply node of the semiconductor chip for providing the second supply voltage.

According to an exemplary embodiment of the present disclosure, a display device includes a display panel divided into a display area, a non-display area, a bending area, and a pad area and bent in one direction in the bending area; a plurality of pixels disposed in the display area; at least one gate driver disposed in the non-display area and configured to supply a gate voltage to the plurality of pixels; flexible films connected to a plurality of pads disposed in the pad area; and at least one electrostatic discharge (ESD) circuit disposed in the pad area and connected to the at least one gate driver through a discharge line.

The invention discloses an electrostatic protection circuit and method, equipment and a storage medium, and relates to the technical field of electrostatic protection, and the circuit comprises a metal sheet connecting plug, an electrostatic discharge circuit, an electrostatic sampling circuit and a microcontroller; the metal sheet connecting plug is electrically connected with the metal sheet, the electrostatic discharge circuit and the electrostatic sampling circuit respectively; the electrostatic sampling circuit comprises a voltage division circuit and a conditioning circuit, and the voltage division circuit is electrically connected with the metal sheet connecting plug and the conditioning circuit; and the microcontroller is in communication connection with the electrostatic sampling circuit and the electrostatic discharge circuit and is used for performing analog-to-digital conversion on the output voltage of the conditioning circuit to obtain electrostatic voltage and controlling the electrostatic discharge circuit to be switched on or switched off. The static voltage of the operator can be acquired in real time through the microcontroller so as to accurately judge whether the static discharge of the current operator is in place or not, so that the condition of hot-line operation of corresponding equipment when the static discharge is insufficient is reduced, and the accuracy and reliability of the static discharge are improved.

A display device according to one or more embodiments includes a display device including a substrate including a display area and a non-display area, pixels in the display area above the substrate, an electrostatic discharge circuit in the non-display area above the substrate, a first line in the non-display area above the substrate, and configured to receive a first voltage, a second line in the non-display area above the substrate, and configured to receive a second voltage that is lower than the first voltage, a first connection line connected between the first line and the electrostatic discharge circuit under the first line on the substrate, and a second connection line connected between the second line and the electrostatic discharge circuit under the second line on the substrate.

The present disclosure provides a display substrate including a base substrate, a plurality of data lines, a plurality of multiplexing circuits, a plurality of multiplexing data lines, a plurality of first electrostatic discharge circuits, a plurality of second electrostatic discharge circuits, and a plurality of first signal lines located on the base substrate. The plurality of multiplexing circuits are sequentially arranged along edges of the display region. The plurality of multiplexing circuits are electrically connected with the plurality of multiplexing data lines and the plurality of data lines. The plurality of first electrostatic discharge circuits are electrically connected to the plurality of multiplexing data lines, and the plurality of second electrostatic discharge circuits are electrically connected to the plurality of first signal lines.

The invention provides a fast capture implementation method suitable for high-speed spread frequency hopping signals, which comprises the following steps of: 1, starting a capture process, and carrying out digital de-hopping; 2, roughly capturing and searching the de-hopped signal; and step 3, finely capturing and searching the de-hopped signal. According to the method provided by the invention, a large-range preliminary search method is used for assisting a small-range fine search method to replace the problem of resource doubling caused by a traditional spread frequency hopping large dynamic interval search method, so that the on-satellite resource consumption is greatly reduced, the capture time is shortened, and the method is insensitive to the transmission rate. The method is suitable for a space environment with a severe signal-to-noise ratio, a complex electromagnetic compatibility environment, an electrostatic discharge environment and a random interference environment, and is also suitable for a complex space environment.

The invention provides an electrostatic discharge structure robustness evaluation method and device, and belongs to the technical field of semiconductors, and the method comprises the steps: carrying out the layer-by-layer removal of a chip, carrying out the circuit analysis of the obtained layout information, obtaining a schematic circuit diagram, carrying out the section dyeing processing according to the schematic circuit diagram, and obtaining the geometric information, and detecting the electrostatic discharge structure to obtain PN region distribution information, performing TCAD simulation by using the layout information, the geometric information and the PN region distribution information, and determining the robust performance of the electrostatic discharge structure of the chip according to the obtained electrical characteristic information. According to the electrostatic discharge structure robustness evaluation method and device provided by the invention, an electrostatic discharge structure robustness evaluation means based on structure extraction and TCAD simulation is provided, and a device design manufacturer does not need to provide a schematic circuit diagram and layout of the electrostatic discharge structure and does not need to provide process parameters; and the robustness evaluation efficiency of the ESD structure of the semiconductor device is effectively improved.

An apparatus includes a drain and a source on opposing sides of an epitaxial layer, a body region and a plurality of gates formed in the epitaxial layer, an interlayer dielectric layer over the epitaxial layer, a gate-source electrostatic discharge (ESD) diode in the interlayer dielectric layer, a source contact connected to the source and a first terminal of the gate-source ESD diode structure, a gate contact connected to the plurality of gates and a second terminal of the gate-source ESD diode structure, a drain contact on opposing sides of the epitaxial layer of the source contact, a breakdown voltage enhancement and leakage prevention structure formed underneath the gate-source ESD diode structure, wherein the breakdown voltage enhancement and leakage prevention structure comprises a body ring structure.

The present disclosure provides an electronic device, comprising: a substrate including an active region and a peripheral region; a common lead disposed corresponding to the peripheral region of the substrate; the scanning line is arranged on the substrate, and in the peripheral area, the scanning line is electrically connected with a first electrostatic discharge wire through a first electrostatic protection circuit; wherein the common lead is electrically separated from the first electrostatic discharge lead, and a first distance is formed between the common lead and the first electrostatic discharge lead in the overlook direction of the substrate, and the first distance is larger than or equal to 1.5 microns (mu m) and smaller than or equal to 12 millimeters (mm).

In some aspects of the present disclosure, an electrostatic discharge (ESD) protection circuit is disclosed. In some aspects, the ESD protection circuit includes a first transistor coupled to a pad, a second transistor coupled between the first transistor and ground, a stack of transistors coupled to the first transistor, and an ESD clamp coupled between the stack of transistors and the ground.