4907 results about "Electrostatic discharge" patented technology

A package structure including a first lead, a second lead, an encapsulant, a light-emitting device and an electrostatic discharge (ESD) protection device is provided. The second lead is disposed beside the first lead, and parts of the first lead and the second lead are encapsulated by the encapsulant. The encapsulant has a first cavity and a second cavity. Parts of the first lead and the second lead are exposed by the first cavity and the other parts of the first lead and the second lead are exposed by the second cavity. The light-emitting device is disposed inside the first cavity and electrically connected to the first lead and the second lead. The ESD protection device is disposed inside the second cavity and electrically connected to the first lead and the second lead.

A solid state (light emitting diode) lamp in numerous configurations have improved thermal management by providing a direct thermal pathway from the plurality of LED chips to the threaded screw base (standard 100˜240 VAC lamp socket), or power coupling. The control circuitry is disposed opposite the printed circuit board and LED chips with respect to the heat sink so that the heat sink is interposed between the printed circuit board and the control circuitry. The LED chips are powered using a high voltage/high current configuration. The light radiation pattern is infinitely adjustable (very wide through very narrow) via a system of easily interchangeable lenses. The solid state lamps can be mass produced rapidly at significantly lower cost with very high luminous intensity. ESD protection may be included to protect the LED chips from electrostatic discharge damage.

A disk drive includes a disk having a recording surface, a head stack assembly that includes a body portion, an actuator arm cantilevered from the body portion and a head gimbal assembly supported at the actuator arm. The head gimbal assembly includes a suspension having a first end and a second end, the first end being attached to the actuator arm, a slider coupled to the second end of the suspension, the slider comprising a transducer for reading from and writing to the recording surface. A gimbal is coupled to the second end of the suspension and to the slider. An array of diodes is attached to the suspension to protect the transducer from electrostatic discharge or electrical overstress events.

The present invention discloses an electrostatic chuck sucking and supporting a substrate with an electrostatic force and an OLED manufacturing apparatus having the same. The electrostatic chuck includes an insulating plate having at least one opening penetrating a center thereof, a pair of electrodes mounted on the insulating plate, a first controller applying a voltage to the pair of electrodes, and an electrostatic charge removing unit disposed near the insulating plate and emitting ions into the at least one opening to remove electrostatic charges distributed around a side of the insulating plate.

A disk drive is disclosed comprising a disk and a head actuated over the disk. The head comprising a first head terminal and a second head terminal. The disk drive further comprises an electrostatic discharge (ESD) protection circuit comprising a first depletion mode metal oxide semiconductor field effect transistor (MOSFET) and a second depletion mode MOSFET. A first transistor terminal of the depletion mode MOSFETs are coupled to respective head terminals, and a second transistor terminal of the depletion mode MOSFETs are coupled to ground. The gate terminals of the first and second depletion mode MOSFETs are biased to turn on the depletion mode MOSFETs while the disk drive is powered down, thereby grounding the first and second head terminals to protect the head from ESD.

A substrate-supporting rod (4) comprises a resin body (41) and a metal rod (43). The resin body (41) includes a body portion (411) being cylinder-shaped and having a first through hole (413) in a direction of the axis thereof and a number of shelves (415, 415′) arising from said body portion (411) and extending in parallel and inwardly of a cassette (5) at a predetermined pitch. The metal rod (43) is received in the first through hole (413) of the body portion (411) so as to increase the rigidity of the substrate-supporting rob (4). A projection (4151) is defined on the end of each shelf (415, 415′) to support a substrate (45). Further, the body portion (411) is molded from an electrically conductive resin so that not only the cassette (5) can be protected against static discharge but also resin material is saved and cost is decreased.

A method to reduce electrostatic discharge susceptibility when assembling a stacked IC device. The method includes coupling a ground plane of a first semiconductor device and a ground plane of a second semiconductor device to substantially a same electrical potential. Active circuitry on the first semiconductor device and active circuitry on the second semiconductor device are electrically coupled after the ground planes are coupled. Electrically coupling the ground planes of the first and the second semiconductor device creates a preferred electrostatic discharge path to ground, thus minimizing potential damage to sensitive circuit elements.

An unassembled stacked IC device includes an unassembled tier. The unassembled stacked IC device also includes a first unpatterned layer on the unassembled tier. The first unpatterned layer protects the unassembled tier from ESD events.

A silicon-on-insulator (SOI) electrostatic discharge (ESD) protection device that can protect very sensitive thin gate oxides by limiting the power dissipation during the ESD event, which is best achieved by reducing the voltage drop across the active (protection) device during an ESD event. In one embodiment, the invention provides very low triggering and holding voltages. Furthermore, the SOI protection device of the present invention has low impedance and low power dissipation characteristics that reduce voltage build-up, and accordingly, enable designers to fabricate more area efficient protection device.

Conventionally, there are problems that high resolution is difficult to be achieved since an extreme narrow width bank can not be formed and an aperture ratio as a light-emitting device is low. In addition, there is a threat of electrostatic discharge damage or adhesion of dust during the transportation of a substrate provided with an anode into the equipment for depositing EL material. In view of the foregoing, a first bank formed of an inorganic insulating film is formed, and an insulating film is formed thereon, then, a second bank in contact with a side face of the first bank by carrying out etch back, and then, a side wall bank is formed. For preventing electrostatic discharge damage, an antistatic layer is formed, and the substrate is transported, then, the antistatic layer is removed to form the second bank.

A silicon-on-insulator (SOI) electrostatic discharge (ESD) protection device that can protect very sensitive thin gate oxides by limiting the power dissipation during the ESD event, which is best achieved by reducing the voltage drop across the active (protection) device during an ESD event. In one embodiment, the invention provides very low triggering and holding voltages. Furthermore, the SOI protection device of the present invention has low impedance and low power dissipation characteristics that reduce voltage build-up, and accordingly, enable designers to fabricate more area efficient protection device

A touch panel including a substrate, a plurality of first sensing series, and a plurality of second sensing series is provided. The first sensing series and the second sensing series are disposed on the substrate. The first sensing series extend along a first direction and are electrically insulated from each other. Each of the first sensing series includes a plurality of first sensing pads and a plurality of first bridge portions connected between the first sensing pads. The second sensing series extend along a second direction and are electrically insulated from each other. Each of the second sensing series includes a plurality of second sensing pads and a plurality of second bridge portions connected between the second sensing pads. Each of the first bridge portions and one of the second bridge portions are intersected, and at least one of the second bridge portions has at least one electrostatic discharge tip.

A finger sensor may include a finger sensing integrated circuit (IC) having a finger sensing area and at least one bond pad adjacent thereto, and a flexible circuit coupled to the IC finger sensor. More particularly, the flexible circuit may include a flexible layer, and at least one conductive trace carried thereby and coupled to the at least one bond pad. The sensor may also include at least one Electrostatic Discharge (ESD) electrode carried by the flexible layer. The ESD electrode may be positioned adjacent a beveled edge, for example, of an IC carrier and thereby exposed through a small gap between an adjacent portion of a frame.

Silicon is formed at selected locations on a silicon-insulator (SOI) substrate during fabrication of selected electronic components, including resistors, capacitors, and diodes. The silicon location is defined using a patterned, removable mask, and the silicon may be applied by deposition or growth and may take the form of polysilicon or crystalline silicon. Electrostatic discharge (ESD) characteristics of the SOI device is significantly improved by having a thick double layer of silicon in selected regions.

A workpiece has at least two semiconductor chips, each semiconductor chip having a first main surface, which is at least partially exposed, and a second main surface. The workpiece also comprises an electrically conducting layer, arranged on the at least two semiconductor chips, the electrically conducting layer being arranged at least on regions of the second main surface, and a molding compound, arranged on the electrically conducting layer.

Devices, systems and methods are disclosed for a neural access device that includes an implant which transcutaneously exits the skin of a patient and provides transport of signals between a sensor implanted in a patient and an external device. The transcutaneous implant has integrated features to provide reduced risk of injury due to mechanical forces as well as electrostatic discharge energy applied to the external portion of the device. Transcutaneous devices which provide wireless communication between a sensor and an external device are also disclosed.

An I/O electrostatic discharge (ESD) device having a gate electrode over a substrate, a gate dielectric layer between the gate electrode and the substrate, a pair of sidewall spacers respectively disposed on two opposite sidewalls of the gate electrode, a first lightly doped drain (LDD) region disposed under one of the sidewall spacers, a source region disposed next to the first LDD region, a second LDD region disposed under the other sidewall spacer, and a drain region disposed next to the second LDD region, wherein a doping concentration of the second LDD region is larger than a doping concentration of the first LDD region.

A vertical tunneling FET (TFET) provides low-power, high-speed switching performance for transistors having critical dimensions below 7 nm. The vertical TFET uses a gate-all-around (GAA) device architecture having a cylindrical structure that extends above the surface of a doped well formed in a silicon substrate. The cylindrical structure includes a lower drain region, a channel, and an upper source region, which are grown epitaxially from the doped well. The channel is made of intrinsic silicon, while the source and drain regions are doped in-situ. An annular gate surrounds the channel, capacitively controlling current flow through the channel from all sides. The source is electrically accessible via a front side contact, while the drain is accessed via a backside contact that provides low contact resistance and also serves as a heat sink. Reliability of vertical TFET integrated circuits is enhanced by coupling the vertical TFETs to electrostatic discharge (ESD) diodes.

A gallium nitride-based light emitting device, and a method for manufacturing the same are provided. The light emitting device comprises a substrate; a main GaN-based LED including a first p-side electrode and a first n-side electrode, the main GaN-based LED formed in a first region on the substrate; and an ESD protecting GaN-based LED including a second p-side electrode and a second n-side electrode, the ESD protecting GaN-based LED formed in a second region on the substrate. The first region is separated from the second region by a device isolation region. The first p-side and n-side electrodes are electrically connected to the second n-side and p-side electrodes, respectively.

A low triggering voltage PD-SOI (Partially-Depleted Silicon-on-Insulator) electrostatic discharge (ESD) protection structure is disclosed. In one embodiment, the protection structure includes: A semiconductor substrate; a thin film layer separated from a bulk silicon substrate by an insulator inside the semiconductor substrate; a first isolation region formed in the thin film layer; a second isolation region formed in the thin film layer; a first region having a first conductivity type formed in between the first and second isolation region; a second region formed in between the first region and the second isolation region, the second region being of a second conductivity type; a third region formed in between the first isolation region and the first region, the third region being of the first conductivity type; a fourth region formed in between the second isolation region and the second region, the fourth region being of the first conductivity type; a fifth region having an exposed upper surface formed in the first region, the fifth region being of the second conductivity type; a sixth region having an exposed surface formed in the second region, the sixth region being of the second conductivity type; and a seventh region having an exposed upper surface formed in the second region and overlapping the first region, moreover, the seventh region being between the fifth and sixth region and the seventh region being of the first conductivity type. Another embodiment of the present invention is very similar to the previous one, which is also extracted in the present specification.

An electrostatic discharge (ESD) protection clamp (61) for I/O terminals (22, 23) of integrated circuits (ICs) (24) comprises an NPN bipolar transistor (25) coupled to an integrated Zener diode (30). Variations in the break-down current-voltage characteristics (311, 312, 313, 314) of multiple prior art ESD clamps (31) in different parts of the same IC chip is avoided by forming the anode (301) of the Zener (30) in the shape of a base-coupled P+ annular ring (75) surrounded by a spaced-apart N+ annular collector ring (70) for the cathode (302) of the Zener (30). Even though an angled implant (51, 86, 98) used to form the N+ annular collector ring (70) causes location dependent variations in the width (53) of the Zener space charge (ZSC) region (69), the improved annular shaped clamp (61) always has a portion that initiates break-down at the design voltage so that variations in the width (53) of the ZSC region (69) do not cause significant variations in the clamp's current-voltage characteristics (611, 612, 613, 614).