1048 results about "Electrostatic discharge" patented technology

The invention relates to the technical field of operation control, in particular to an unattended operation crucible loading and unloading operation control system and method based on visual processing, and the method comprises the following steps: monitoring a static accumulation value in a graphite powder fluidization conveying process in real time through a distributed static sensor; when the static accumulation value exceeds a safety threshold value, pulse type ion wind neutralization treatment is triggered, and a static balance material flow is generated; the dynamic alignment deviation of the stock bin and the crucible opening is calculated; the stepping angle and the rotating speed of a spiral auger in the stock bin are controlled based on the dynamic alignment deviation, and an axial vibration field is synchronously applied in the discharging process; the position of an air gap in a material is predicted based on a convolutional neural network, and a vacuum negative pressure value is dynamically adjusted to form a gradient suction mode. According to the device, the risks of powder agglomeration, conveying pipeline blockage or electrostatic discharge caused by electrostatic accumulation are effectively prevented, the safety of the conveying process is ensured, and meanwhile, the flowing stability of graphite powder is optimized.

An anti-interference bidirectional electrostatic protection circuit provided by the present invention comprises a first electrostatic discharge path and a second electrostatic discharge path which are arranged in parallel, and the first electrostatic discharge path comprises a first electrostatic discharge unit and a second electrostatic discharge unit which are arranged in a stacked manner. The second electrostatic discharge path comprises a third electrostatic discharge unit and a fourth electrostatic discharge unit which are stacked, the first electrostatic discharge unit and the second electrostatic discharge unit are arranged in opposite directions, the capacitance value of the first electrostatic discharge unit is larger than that of the second electrostatic discharge unit, and the capacitance value of the third electrostatic discharge unit is larger than that of the fourth electrostatic discharge unit. The third electrostatic discharge unit and the fourth electrostatic discharge unit are arranged in opposite directions, the capacitance value of the third electrostatic discharge unit is larger than that of the fourth electrostatic discharge unit, and the first electrostatic discharge unit and the third electrostatic discharge unit are arranged in opposite directions. Through circuit structure and layout optimization, accumulated charges on an internal floating node can be discharged.

A system and method for an electrostatic discharge (ESD) clamp circuit containing a disable circuit to selectively disable a discharge circuit is disclosed. An electrostatic discharge (ESD) clamp circuit including a discharge circuit to discharge a current flow during a transient ESD voltage event; a disable input to receive a disable input signal; and a disable circuit to, based upon the disable input signal, selectively disable the discharge circuit. When the disable input signal is a first logic state, the disable circuit is to allow the discharge circuit to be enabled; and when the disable input signal is in a second logic state, the disable circuit is to disable the discharge circuit.

An array substrate includes a display area and a notch area. The display area includes a first display sub-area and a second display sub-area spaced apart from each other by the notch area. The notch area includes an electrostatic discharge area. The array substrate includes a plurality of data lines and a plurality of scan signal lines. The plurality of data lines at least partially extend into the electrostatic discharge area. The plurality of scan signal lines cross over the electrostatic discharge area. At least a portion of the electrostatic discharge area includes a plurality of first sub-regions and a plurality of second sub-regions alternately arranged. The plurality of scan signal lines are present in the plurality of first sub-regions, and absent in the plurality of second sub-regions. The plurality of data lines are present in the plurality of second sub-regions, and absent in the plurality of first sub-regions.

The utility model relates to the technical field of detection equipment, and particularly discloses automatic detection equipment for materials, which comprises a base, and a feeding mechanism, a camera shooting mechanism, a control assembly and a limiting mechanism which are arranged on the base, the feeding mechanism is arranged below the camera shooting mechanism, the control assembly controls the feeding mechanism to move an external detection product to the camera shooting mechanism, the control assembly controls the limiting mechanism to limit the external detection product, moved to the camera shooting mechanism, of the feeding mechanism, and the control assembly regulates and controls the camera shooting mechanism to take photos or videos of the external detection product. According to the automatic detection equipment, the external plate is moved to the detection table in a non-contact mode through the accurate conveying belt, the graph scanning and collecting device and the like, damage to the external plate possibly caused by uneven force, hand sweat corrosion or electrostatic discharge and the like during manual operation is avoided, graph collection and detection are conducted in an all-around mode, and the detection efficiency is improved. The detection efficiency of the electronic plate production line is greatly improved, the labor cost is reduced, and the practicability is high.

The embodiment of the invention discloses an electrostatic discharge inspection method and device for stacked chips, equipment and a storage medium, relates to the technical field of semiconductor circuits, and can save inspection time and computing resources so as to effectively improve inspection efficiency. The method comprises the steps that to-be-inspected discharge paths of stacked chips are divided into a first type of discharge paths and a second type of discharge paths, the first type of discharge paths represent electrostatic discharge paths coinciding with those in two-dimensional electrostatic discharge inspection, and the second type of discharge paths represent electrostatic discharge paths crossing core particles; performing two-dimensional electrostatic discharge inspection on each core particle forming the stacked chip so as to cover the first type of discharge path; and based on a shortest discharge path principle, screening out a target discharge path from the second type of discharge paths to perform electrostatic discharge inspection, wherein the target discharge path represents the shortest electrostatic discharge path in the electrostatic discharge paths crossing the core particles. The method and the device are suitable for electrostatic discharge inspection scenes of semiconductor chips.

The present disclosure provides a semiconductor device, which includes a control circuit, a driving circuit, a voltage pull-up device, and a discharging circuit. The control circuit is coupled between a first terminal and a second terminal of the integrated circuit, and provides a first voltage at a first node. The driving circuit is electrically connected to the control circuit at the first node, and provides a trigger signal at a second node in response to an electrostatic discharge (ESD) event occurring at the first terminal or the second terminal. The voltage pull-up device is coupled between the first terminal and the first node, and configured to pull up the first voltage at the first node in response to the ESD event occurring at the first terminal. The discharging circuit is electrically connected to the second node, and coupled between the first terminal and the second terminal.

The invention discloses a surge protection circuit, which belongs to the field of semiconductor surge protection devices, and comprises a plurality of resistors, a plurality of voltage stabilizing diodes and a plurality of transistors, the first end of the first resistor is connected with a bus voltage, the first end of the first transistor and the second end of the second transistor; the second end of the first resistor is connected with the third end of the first transistor and the cathode of the first Zener diode, and the anode of the first Zener diode is connected with the cathode of the second Zener diode and the third end of the third transistor. The anode of the second voltage stabilizing diode is connected with the second end of the third resistor, the second end of the third transistor, the first end of the second transistor and the ground, the second end of the first transistor is connected with the first end of the second resistor, and the second end of the second resistor is connected with the first end of the third resistor, the first end of the third transistor and the third end of the second transistor. According to the invention, the problems of surge voltage such as electrostatic discharge, electrical fast transient pulse train, lightning stroke, peak and the like, transient voltage generated in a hot plug process and the like can be solved.

The invention discloses a high-voltage bidirectional silicon controlled rectifier electrostatic protection device and a manufacturing method. The high-voltage bidirectional silicon controlled rectifier electrostatic protection device comprises a P-type substrate, a P-type well and a high-voltage N well, the emitter P + injection of a parasitic PNP triode and the emitter N + injection of a parasitic NPN triode in the P-type well are arranged alternately, so that the length of a transverse discharge path of the silicon controlled rectifier is reduced to the greatest extent, the square resistance of a PNPN positive feedback conduction path is greatly reduced, and the key problem that a symmetrical bidirectional silicon controlled rectifier structure cannot be effectively opened in a high-voltage window of more than 70V is solved; in addition, the layout can provide an additional parasitic NPN triode path for a silicon controlled rectifier path, the effective area of an emitter of the parasitic NPN triode and the proportion of the emitter in a silicon controlled rectifier loop are increased, and the current discharge capacity of the device is further improved. Therefore, reference can be provided for the structural design of the high-voltage symmetrical bidirectional silicon controlled rectifier electrostatic protection device, and the silicon controlled rectifier can be effectively applied to ESD protection of a high-voltage bidirectional port.

The invention relates to the technical field of soil treatment, and particularly discloses a soil micro-plastic electrostatic separation device and method.The soil micro-plastic electrostatic separation device comprises a sample pool, an electrostatic adsorption mechanism is arranged on one side of the sample pool, and the electrostatic adsorption mechanism is connected with an electrostatic discharge generator through a wire; the electrostatic adsorption mechanism comprises an adsorption plate and a connecting handle; the bottom box and the heightening frame bodies are made of wood, the height of the sample pool can be adjusted by installing the heightening frame bodies in an assembling mode, a nylon coating is arranged on the outer side of an adsorption plate and used for adsorbing micro-plastics and eradicating the risk of high-voltage electric leakage, and the height of the adsorption plate can be adjusted through an arranged supporting assembly; the particle size range of the micro-plastic covered by electrostatic adsorption is wide, compared with a traditional method, the recovery rate is remarkably improved, and the original form of the micro-plastic and the natural structure of soil are protected through normal-temperature physical separation and no reagent addition.

An electrostatic discharge semiconductor device is disclosed and comprises: a first well region of a first doping type, extending from the surface of an epitaxial layer to the surface of the substrate; a second well region and a third well region of a second doping type; a fourth well region of the second doping type; a fifth well region and a sixth well region have a first doping type; a first injection region and a second injection region, spaced apart in each well region. The second injection region in the second and third well regions is connected to a cathode, and the first and second injection regions in the fourth well region are connected to an anode. The electrostatic discharge semiconductor device enhances its electrostatic protection capability by adjusting the avalanche breakdown voltage between the floating fifth and sixth well regions and the triggering voltage of the device.

An apparatus includes a drain and a source on opposing sides of an epitaxial layer, a body region and a plurality of gates formed in the epitaxial layer, an interlayer dielectric layer over the epitaxial layer, a gate-source electrostatic discharge (ESD) diode in the interlayer dielectric layer, a source contact connected to the source and a first terminal of the gate-source ESD diode structure, a gate contact connected to the plurality of gates and a second terminal of the gate-source ESD diode structure, a drain contact on opposing sides of the epitaxial layer of the source contact, a breakdown voltage enhancement and leakage prevention structure formed underneath the gate-source ESD diode structure, wherein the breakdown voltage enhancement and leakage prevention structure comprises a body ring structure.

A display panel and a display device are disclosed and, more specifically, the display panel includes a substrate including a display area where a plurality of subpixels are disposed, a gate driving circuit disposed in a non-display area outside the display area to supply a plurality of scan signals to the plurality of subpixels, an electrostatic discharge unit disposed in the non-display area, and a plurality of pads disposed in the non-display area and coupled with a plurality of signal lines electrically connected to the gate driving circuit and the electrostatic discharge unit, wherein the plurality of pads include, as sequentially disposed, a clock pad connected with a clock signal line, a first line pad connected with a first power line, an additional pad connected with an electrostatic discharge high-potential voltage line and an electrostatic discharge low-potential voltage line, and a second line pad connected with a second power line.

ElectroStatic Discharge (ESD) protection circuitry for a semiconductor chip. The ESD protection circuitry includes a first node for coupling to an I / O node of the semiconductor chip and includes a first conductive path coupled to the first node via a first diode. The first conductive path is configured to be at first voltage level higher than or equal to a voltage level of a first supply voltage. The ESD protection circuitry includes a second conductive path coupled to the first node via a second diode. The second conductive path is configured to be at second voltage level lower than or equal to a voltage level of a second supply voltage. The second supply voltage is lower than the first supply voltage. The ESD protection circuitry includes a second node for coupling to a ground node or a supply node of the semiconductor chip for providing the second supply voltage.

The invention discloses an electrostatic protection circuit and method, equipment and a storage medium, and relates to the technical field of electrostatic protection, and the circuit comprises a metal sheet connecting plug, an electrostatic discharge circuit, an electrostatic sampling circuit and a microcontroller; the metal sheet connecting plug is electrically connected with the metal sheet, the electrostatic discharge circuit and the electrostatic sampling circuit respectively; the electrostatic sampling circuit comprises a voltage division circuit and a conditioning circuit, and the voltage division circuit is electrically connected with the metal sheet connecting plug and the conditioning circuit; and the microcontroller is in communication connection with the electrostatic sampling circuit and the electrostatic discharge circuit and is used for performing analog-to-digital conversion on the output voltage of the conditioning circuit to obtain electrostatic voltage and controlling the electrostatic discharge circuit to be switched on or switched off. The static voltage of the operator can be acquired in real time through the microcontroller so as to accurately judge whether the static discharge of the current operator is in place or not, so that the condition of hot-line operation of corresponding equipment when the static discharge is insufficient is reduced, and the accuracy and reliability of the static discharge are improved.

An apparatus includes a drain and a source on opposing sides of an epitaxial layer, a body region and a plurality of gates formed in the epitaxial layer, an interlayer dielectric layer over the epitaxial layer, a gate-source electrostatic discharge (ESD) diode in the interlayer dielectric layer, a source contact connected to the source and a first terminal of the gate-source ESD diode structure, a gate contact connected to the plurality of gates and a second terminal of the gate-source ESD diode structure, a drain contact on opposing sides of the epitaxial layer of the source contact, a breakdown voltage enhancement and leakage prevention structure formed underneath the gate-source ESD diode structure, wherein the breakdown voltage enhancement and leakage prevention structure comprises a body ring structure.

A display device includes a base layer including a display area and a non-display area, an emission unit including a first electrode electrically connected to a first driving power source, a second electrode electrically connected to a second driving power source, and a light-emitting element disposed between first and second electrodes, a first transistor including a first terminal electrically connected to the first driving power source, a second terminal electrically connected to the first electrode of the emission unit, and a gate electrode electrically connected to a first node, a second transistor including a first terminal electrically connected to a data line, a second terminal electrically connected to the first node, and a gate electrode electrically connected to a scan line, and an electrostatic discharge circuit disposed in the display area and disposed between the first driving power source and the data line.

A semiconductor device is provided, including an input / output (I / O) pad, a power clamp, an electrostatic discharge (ESD) clamp circuit, a bias circuit, and a voltage-triggered source. The power clamp is coupled between first and second power rails. The ESD clamp circuit is connected to the I / O pad and coupled between an electrostatic discharge bus and the second power rail. The bias circuit is coupled between the first power rail and the electrostatic discharge bus, and is configured to couple the ESD bus to the first power rail during a normal operation mode, and float the electrostatic discharge bus during an electrostatic discharge mode or a fail-safe mode. The voltage-triggered source is coupled between the ESD bus and the second power rail, and provides a trigger voltage for a first electrostatic discharge path in response to an ESD event occurring on the I / O pad.

A touch sensor includes a sensor electrode, a touch panel overlying the sensor electrode, and a dielectric covering separating the sensor electrode from the touch panel. The dielectric covering may be configured to inhibit electrostatic discharge through the sensor electrode.

The present disclosure provides a display substrate including a base substrate, a plurality of data lines, a plurality of multiplexing circuits, a plurality of multiplexing data lines, a plurality of first electrostatic discharge circuits, a plurality of second electrostatic discharge circuits, and a plurality of first signal lines located on the base substrate. The plurality of multiplexing circuits are sequentially arranged along edges of the display region. The plurality of multiplexing circuits are electrically connected with the plurality of multiplexing data lines and the plurality of data lines. The plurality of first electrostatic discharge circuits are electrically connected to the plurality of multiplexing data lines, and the plurality of second electrostatic discharge circuits are electrically connected to the plurality of first signal lines.

A vacuum chuck may include a chuck body formed from silicon carbide. A carbon coating, such as a diamond-like carbon coating, may be deposited on the chuck body. Coating the silicon carbide vacuum chucks with the carbon coatings may control electrostatic discharge events. The carbon coatings may increase the surface resistance of the chuck body and bring the vacuum chucks to within an electrostatic discharge specification which is a tightening specification in the semiconductor industry.

The utility model discloses an InCell glass electrostatic discharge assembly which comprises an InCell glass body and an FPC body, a CF layer is located on the upper portion of a glass face ITO layer, a CND ITO layer is arranged on the surface of the CF layer, the CND ITO layer is electrically connected with the glass face ITO layer, the glass face ITO layer is electrically connected with the FPC body, the FPC body comprises an FPC metal layer, and the FPC metal layer is arranged on the upper portion of the InCell glass body. One side of the stainless steel reinforcement is connected with the FPC metal layer in a bonding mode through the first conductive adhesive layer, and the other side of the stainless steel reinforcement is connected with the module iron frame in a bonding mode through the second conductive adhesive layer. After the FPC body is reversely folded, the module iron stand and the stainless steel reinforcement form an electric connection structure through the conductive adhesive. At the moment, once static electricity is generated on the CND ITO layer of the InCell glass body, the static electricity can quickly flow away from a conductive channel formed by the first conductive adhesive layer and the second conductive adhesive layer, so that the FPC body is prevented from being interfered by the static electricity, and the display effect is effectively improved.

The present disclosure provides a semiconductor device, which includes a control circuit, a driving circuit, a voltage pull-up device, and a discharging circuit. The control circuit is coupled between a first terminal and a second terminal of the integrated circuit, and provides a first voltage at a first node. The driving circuit is electrically connected to the control circuit at the first node, and provides a trigger signal at a second node in response to an electrostatic discharge (ESD) event occurring at the first terminal or the second terminal. The voltage pull-up device is coupled between the first terminal and the first node, and configured to pull up the first voltage at the first node in response to the ESD event occurring at the first terminal. The discharging circuit is electrically connected to the second node, and coupled between the first terminal and the second terminal.

The present invention discloses a board-to-board floating connector with electrostatic discharge resistance, which is connected to a first circuit board and a second circuit board, and includes a male connection module and a female connection module. The male connection module further includes a first housing, a board body, a plurality of male terminals, a first pin and a first shielding member; and the female connection module further includes a second housing, a groove body, a plurality of female terminals, a second pin and a second shielding member. The first shielding member and the first pin establish a first electrical path, and the second shielding member and the second pin establish a second electrical path. Through the male connection module, the female connection module and their combination, an electrostatic can be discharged.

The utility model provides an annular internal circuit electrostatic protection layout structure with back gate contact, which comprises a resistor R0 connected with an input end, an NMOS (N-channel Metal Oxide Semiconductor) tube NM0, a PMOS (P-channel Metal Oxide Semiconductor) tube PM0 and a PMOS tube PM1 connected with the PM0, wherein the NMOS tube NM0 and the PMOS tube PM0 are respectively connected with the other end of the resistor R0, and a drain electrode of the NM0, a grid electrode and a drain electrode of the PM0 are connected with the other end of the resistor R0 and then connected with an output end; a grid electrode and a source electrode of the NM0 are connected and then grounded, a source electrode of the PM0 is connected with a drain electrode of the PM1, and a grid electrode and a source electrode of the PM1 are connected with a power supply VDD; pM0, PM1 and NM0 are all square grid electrodes, and PM1 and NM0 are in back gate contact. According to the utility model, the back gate contact is used to prevent minority carriers from entering the substrate, so that the latch-up effect is avoided and the area is reduced; the series-connected polycrystalline silicon current-limiting resistors are used, high voltage generated when electrostatic discharge occurs is converted into small current through the high-resistance resistor, a self-protection function is achieved, and the risk that the current flows to a power source from a device does not exist. Comprising a clamping structure with a self-protection function, the drain electrode is widened, and the high-resistance annular MOS device can be quickly started and can bear instant high voltage.

The invention belongs to the field of electrostatic discharge (ESD) and electrical overstress (EOS) pulse protection of an integrated circuit, and particularly provides an electrostatic surge integrated protection circuit of a high-reliability high-voltage driving chip, which is used for solving the problems of easy latching, high trigger voltage, poor robustness, low starting speed and the like in a traditional high-voltage ESD / EOS protection scheme. The SCR structure, the Zener structure and the LDMOS structure are technically embedded, the voltage clamping capacity of the Zener diode, the high voltage endurance capacity of the LDMOS, the quick response characteristic of the composite transistor and the strong discharge capacity of the SCR are integrated, the electrostatic and surge integrated protection efficiency is achieved, and under the ESD / EOS electric stress effect, the electrostatic and surge integrated protection effect is achieved. The composite structure promotes orderly opening of the Zener structure, the SCR structure and the LDMOS structure under the action of positive feedback, so that ESD and EOS protection requirements of different pulse frequencies are met, the hysteresis effect and the trigger voltage are remarkably reduced, and the latch-up phenomenon is effectively avoided.

The invention relates to the technical field of display, in particular to an ESD (Electro-Static Discharge) anti-interference method and device for display equipment. Abnormal interruption of a row effective signal DE in an image effective area is monitored in real time, when it is detected that the DE signal is abnormally pulled down due to electrostatic discharge (ESD) interference, an abnormal mark is generated immediately, a cache module is triggered to skip current abnormal row data, and normal image data of a previous row is output repeatedly, so that display abnormities such as a blurred screen, a blank screen or a splash screen are avoided. The device is compatible with mainstream interfaces such as an EDP, a DP, a VBYONE, an LVDS, an MIPI, an HDMI and a VGA, the anti-ESD capability of display equipment can be remarkably improved on the premise of extremely low hardware resource occupation only by additionally arranging DE anomaly detection and line cache control logic at a receiving end, and the device is widely applied to high-standard scenes such as vehicle-mounted scenes, medical scenes and industrial control scenes requiring stable and reliable pictures.

An electrostatic discharge circuit, comprising a first voltage line, a second voltage line and a plurality of transistors. A first voltage signal provided by the first voltage line is greater than a second voltage signal provided by the second voltage line. The plurality of transistors are connected in series between the first voltage line and the second voltage line. At least one of the plurality of transistors is an oxide thin-film transistor, the oxide thin-film transistor comprises a top gate and a bottom gate, and the bottom gate is electrically connected to a third voltage line. The first voltage signal provided by the first voltage line is greater than a third voltage signal provided by the third voltage line.

An electrostatic discharge circuit for a semiconductor die includes a plurality of GGNMOS transistors coupled between a first rail and a second rail of the semiconductor die. Each GGNMOS transistor includes a body contact that is coupled to a trigger rail through a ballast circuit and is coupled to the second rail. During the detection of an ESD event of a sufficient severity, the trigger rail is placed in an asserted condition to make the GGNMOS transistors conductive to discharge ESD current from the first rail to the second rail.

The invention discloses an electrostatic discharge device which comprises a feeding assembly and a discharge assembly, the feeding assembly is provided with an inclined surface, the inclined surface can make electronic components slide to at least one discharge position along the inclined surface by means of gravity, and the discharge assembly is arranged at the discharge position and used for conducting electrostatic discharge on the electronic components. According to the invention, the inclined surface of the feeding assembly automatically conveys the electronic components by using gravity, so that the problems of non-standard operation and high labor intensity caused by manual taking are eliminated, and each electronic component can be ensured to be in vertical contact with a discharge position; and the discharging assembly performs automatic discharging at the discharging position, so that mainboard component failure caused by incomplete manual discharging or leakage discharging is avoided. More specifically, the automatic process improves the discharge efficiency, reduces the operation time, and guarantees the discharge quality through a stable discharge point, thereby solving the problems of quality defects and low efficiency.