409 results about "Nitride semiconductors" patented technology

A semiconductor device includes a substrate, a buffer layer over the substrate, an n-type electrode overlapping the buffer layer, and an electron injection layer in contact with the n-type electrode over the buffer layer. The electron injection layer includes an n-type dopant and a first nitride semiconductor containing gallium. The first nitride semiconductor further contains at least one element of aluminum and indium.

To provide a liquid dispensing device that can increase the frequency of the drive signal. [Solution] A capacitive load drive circuit that outputs a drive signal to displace a capacitive load comprises: an amplification circuit that outputs an amplified modulated signal by driving a first transistor that is driven in accordance with a first gate drive signal corresponding to a modulated signal obtained by modulating a base drive signal output by a modulation circuit, and a second transistor that is driven in accordance with a second gate drive signal corresponding to the modulated signal; and a demodulation circuit that outputs a drive signal obtained by demodulating the amplified modulated signal, wherein at least one of the first transistor and the second transistor comprises a first layer containing a first nitride semiconductor and a second layer containing a second nitride semiconductor having a larger band gap than the first nitride semiconductor, with the second layer positioned above the first layer, in a liquid dispensing device.

A nitride semiconductor layer includes a first layer, a second layer, and a p-type semiconductor layer. The p-type semiconductor layer includes a connection part connected with a source electrode, and an extension part extending in a first direction through the nitride semiconductor layer from the connection part. The extension part is positioned between a first interface between the first layer and the second layer, and a second interface between a substrate and the nitride semiconductor layer. An end of the extension part is positioned between a position of an end of a gate electrode at a drain electrode side in the first direction and a position of an end of the drain electrode at the gate electrode side in the first direction.

A surface-emitting laser element includes: a first guide layer including a photonic crystal layer that is formed on a c plane of a group-3 nitride semiconductor and includes air holes arranged with two-dimensional periodicity in a plane parallel to the photonic crystal layer, and an embedding layer that is formed on the photonic crystal layer and closes the air holes; an active layer formed on the first guide layer; and a second guide layer formed on the active layer, wherein an air hole set including at least a main air hole and a sub-air hole smaller in size than the main air hole is arranged at each square lattice point in the plane parallel to the photonic crystal layer, and wherein the main air hole has a regular-hexagonal prism shape, a long-hexagonal prism shape, or an elliptic cylindrical shape with a major axis parallel to a <11-20> axis.

This semiconductor device includes a substrate, a channel layer provided on one side of a surface of the substrate and including a first nitride semiconductor having a first bandgap, a barrier layer provided on an opposite side of the channel layer from the substrate and including a second nitride semiconductor that includes Alx1Iny1Ga(1−x1−y1)N (0<x1<1, 0<y1<1) and has a second bandgap larger than the first bandgap of the first nitride semiconductor, and an intermediate layer provided in the barrier layer and including a third nitride semiconductor that includes Alx2Iny2Ga(1−x2−y2)N (0≤x2<1, 0≤y2<1), and the semiconductor device satisfies (1−x1−y1)<(1−x2−y2).

A semiconductor device includes: a substrate; a channel layer; a nitride semiconductor layer that includes a barrier layer; a source electrode; a drain electrode; a gate electrode; and an insulating layer. The gate electrode includes a junction portion and a drain-side protruding portion. The insulating layer includes an in-situ Si3N4 film and an ex-situ Si3N4 film. At least one of the following is satisfied: (a) the halogen concentration of the in-situ Si3N4 film is lower than the halogen concentration of the ex-situ Si3N4 film; or (b) the interface oxygen concentration between the in-situ Si3N4 film and the nitride semiconductor layer is lower than the interface oxygen concentration between the ex-situ Si3N4 film and the in-situ Si3N4 film.

This nitride semiconductor device includes: a conductive substrate having a substrate upper surface; a high-resistance layer; a nitride semiconductor layer formed on the high-resistance layer; a first electrode (source electrode) formed on the nitride semiconductor layer; and a via. The high-resistance layer is formed on the substrate upper surface, and has a higher resistance value than does the conductive substrate. The via is electrically connected to the first electrode (source electrode), is provided so as to pass through the nitride semiconductor layer and the high-resistance layer, and contacts the substrate upper surface.

An n-type ohmic electrode 30 is provided on an n-type group III nitride semiconductor layer 10. The n-type ohmic electrode 30 has an Al layer 33 and a second direction-side Al-Ti region 34 located, relative to the Al layer 33, in a second direction opposite to a first direction which is toward the n-type group III nitride semiconductor layer 10. The second direction-side Al-Ti region 34 contains 50 at% or more of Al, 5-30 at% of Ti, and 10 at% or less of O.

The application provides a nitride semiconductor laser with an optical field regulation layer, comprising, from bottom to top, a substrate, a lower limiting layer, a lower waveguide layer, an active layer, an upper waveguide layer, an electron blocking layer and an upper limiting layer, wherein the lower waveguide layer comprises a first lower waveguide layer and a second lower waveguide layer, the first lower waveguide layer is located below the second lower waveguide layer, a first optical field regulation layer is arranged between the first lower waveguide layer and the lower limiting layer, a second optical field regulation layer is arranged between the first lower waveguide layer and the second lower waveguide layer, the first lower waveguide layer, the second lower waveguide layer and the second optical field regulation layer all have an In element concentration variation trend, and the first optical field regulation layer has an Al element concentration variation trend. The application can inhibit the refractive index dispersion of the laser, reduce the influence of the high-concentration carrier concentration fluctuation of the lower waveguide layer on the refractive index variation of the active layer and the lower waveguide layer, improve the confinement factor of the laser and enhance the mode gain of the laser.

A light emitting diode includes an n-type nitride semiconductor layer, a V-pit generation layer disposed on the n-type nitride semiconductor layer and having V-pits, an active layer disposed on the V-pit generation layer and including a first well region formed along a flat surface of the V-pit generation layer and a second well region formed in the V-pit of the V-pit generation layer, a p-type nitride semiconductor layer disposed on the active layer and a sub-emission layer interposed between the n-type nitride semiconductor layer and the p-type nitride semiconductor layer and disposed near the active layer. The sub-emission layer may emit light having a peak wavelength within a range of wavelengths shorter than a peak wavelength of the first well region, and light emitted from the light emitting diode is within a range of 0.205≤X≤0.495 and 0.265≤Y≤0.450 in CIE color coordinates (X, Y).

The present application relates to a manufacturing method of a nitride semiconductor substrate, a nitride semiconductor substrate, and a laminated structure. The manufacturing method has a process of preparing a base substrate; a first process of directly epitaxially growing a single crystal of a Group III nitride semiconductor having a top surface with a (0001) surface exposed on a main surface of the base substrate, causing the top surface to have a plurality of recesses composed of inclined interfaces other than the (0001) surface, causing the inclined interfaces to gradually expand as they go upward from the main surface of the base substrate, and causing the (0001) surface to disappear from the top surface, thereby growing a first layer having a surface composed only of the inclined interfaces; and a second process of epitaxially growing a single crystal of the Group III nitride semiconductor on the first layer, causing the inclined interfaces to disappear, and growing a second layer having a mirror-finished surface.

The present invention relates to a method of manufacturing a group 3 nitride semiconductor template with improved bonding layer quality, and more specifically, to a method of manufacturing a group 3 nitride semiconductor template having a high-quality group 3 nitride semiconductor seed layer, which can significantly improve the quality of a bonding layer by performing annealing on the bonding layer in two stages depending on a temperature.

A nitride semiconductor and method of making the same are provided. In embodiments, a method for manufacturing a nitride semiconductor includes: providing a nitride semiconductor material including at least one main dopant defining a p-type portion; doping the nitride semiconductor material with at least one co-dopant co-located with the main dopant, wherein the co-dopant reduces gas-enhanced diffusion of the main dopant by a component in an ambient gas during annealing; and annealing the nitride semiconductor material under pressure, thereby producing an annealed nitride semiconductor material with an activated main dopant. In implementations, a nitride semiconductor is produced including an annealed nitride semiconductor material doped with magnesium (Mg) and oxygen (O) in an activated p-type portion, wherein the Mg and O are present at a ratio of 2:1.

The present disclosure provides a nitride semiconductor transistor capable of improving distortion characteristics. The nitride semiconductor transistor includes: a nitride semiconductor layer having a channel layer and a barrier layer overlapping each other and having a first polarization in a first direction; a source electrode, a drain electrode, and a gate electrode in contact with the nitride semiconductor layer; a ferroelectric layer between the gate electrode and the drain electrode in plan view and having a second polarization in a second direction opposite to the first direction; the field plate is electrically connected to the source electrode and located above the nitride semiconductor layer, and the ferroelectric layer is located between the nitride semiconductor layer and the field plate.

This invention provides a nitride LED epitaxial wafer, its fabrication method, and its application. The nitride LED epitaxial wafer includes a substrate, a composite buffer layer, a nitride buffer layer, a first nitride semiconductor layer, a nitride light-emitting layer, and a second nitride semiconductor layer stacked together. The composite buffer layer comprises n sets of stacked composite buffer sublayers. The first to (n-1)th sets of composite buffer sublayers respectively include a modulation sublayer, a first capping sublayer, a composite structure sublayer, and a second capping sublayer stacked together. The nth set of composite buffer sublayers includes a modulation sublayer, a first capping sublayer, and a composite structure sublayer stacked together, where n ≥ 2. The composite structure sublayer has a nanostructured pattern. By employing the solution provided by this invention, the problems of dislocations or defects caused by lattice constant and thermal mismatch can be overcome, enabling the development of multifunctional buffer technology.

This nitride semiconductor device (1) comprises a power FET (11), an ESD protection FET (12), a diode (13), and a resistor element (14). A gate structure (50G) of the power FET (11) includes a p-type semiconductor layer (52G) and a gate electrode (54G) that is Schottky-connected to the p-type semiconductor layer (52G). An anode structure (50A) of the diode (13) includes a p-type semiconductor layer (52A). The gate structure (50G), a drain structure (51D) of the ESD protection FET (12), and the anode structure (50A) are electrically connected to each other. A source structure (50S) of the power FET (11), a source structure (51S) of the ESD protection FET (12), and a terminal structure (50R) of the resistor element (14) are electrically connected to each other. A gate structure (51G) of the ESD protection FET (12), a cathode structure (50K) of the diode (13), and a terminal structure (51R) of the resistor element (14) are electrically connected to each other.

A power transistor comprising: a heterojunction formed between two III-nitride semiconductor layers, the heterojunction being configured to allow the formation of a two-dimensional carrier gas at the heterojunction and thereby define an active area of the power transistor; a drain terminal; a source terminal comprising a plurality of source contact regions spaced apart from the drain terminal in a first direction, wherein the source contact regions are spaced apart from each other in a second direction, perpendicular to the first direction; a gate terminal comprising a plurality of gate contact regions; a plurality of first doped III-nitride regions, each of the first doped III-nitride regions surrounding a respective source contact region; and a plurality of isolation regions located inside a boundary of the active area, each isolation region being situated between a pair of first doped III-nitride regions.

The present disclosure provides a nitride semiconductor transistor capable of improving current density. The nitride semiconductor transistor includes: a first channel layer having a first upper surface having nitrogen polarity; the ferroelectric nitride semiconductor layer is positioned on the first upper surface and is provided with a second upper surface with metal polarity; the second channel layer is positioned on the second upper surface and is provided with a third upper surface with metal polarity; and the first barrier layer is positioned on the third upper surface and is provided with a fourth upper surface with metal polarity.

To obtain a nitride crystal substrate having good crystal quality.SOLUTION: A method for manufacturing a nitride crystal substrate using a vapor phase growth method includes a step of preparing a base structure in which at least a surface layer is made of a single crystal of a group III nitride semiconductor containing manganese, a step of epitaxially growing a main growth layer made of a single crystal of a group III nitride semiconductor having a manganese concentration lower than a manganese concentration of the surface layer of the base structure on the base structure, and a step of acquiring at least one self-supporting nitride crystal substrate from the main growth layer.SELECTED DRAWING: Figure 1

A nitride semiconductor device is a nitride semiconductor device including an active element and a passive element, and includes: a nitride semiconductor layer divided into an active region and an inactive region in a plan view; and a metal layer in contact with the nitride semiconductor layer in the inactive region. The active element is provided in the active region, and the passive element is provided in the inactive region. The metal layer includes a coherent state or a metamorphic state relative to the nitride semiconductor layer.

To provide a method for manufacturing a nitride semiconductor device.SOLUTION: The method for manufacturing a nitride semiconductor device includes the steps of: providing an amorphous protective film 30 containing silicon above a nitride semiconductor layer 25; performing heat treatment on the nitride semiconductor layer provided with the protective film in a hot isostatic pressing apparatus 110 under a pressure condition of at least 1 MPa and 1 GPa or less and a temperature condition of at least 1200°C and 1500°C or less. The protective film may be in contact with the nitride semiconductor layer and may include at least one of SiO2, SiN, and SiON.SELECTED DRAWING: Figure 3C

A nitride semiconductor material having low lattice thermal conductivity and a heat flow switching element including the same are provided. The nitride semiconductor material according to the present invention is a metal nitride represented by M-Si-N-Te (where M represents at least one kind of transition metal element, and Te represents an arbitrary element), and has a thermal effusivity of less than 2000 Ws0.5 / m2K. In particular, the M is at least one of Cr, Mn, Ni, Mo, and W. In addition, a heat flow switching element according to the present invention includes an N-type semiconductor layer 3, an insulator layer 4 formed on the N-type semiconductor layer, and a P-type semiconductor layer 5 formed on the insulator layer, wherein at least one of the N-type semiconductor layer and the P-type semiconductor layer is formed from the nitride semiconductor material described above.

To provide a method for manufacturing a nitride semiconductor light-emitting element, capable of controlling to a desired resonator length with high precision and high reproducibility (using such as a reflectance spectrum measured on site in parallel) during the formation of a resonator of a GaN-based surface-emitting laser.SOLUTION: A method for manufacturing a nitride semiconductor light-emitting element includes: a multilayer film reflection mirror lamination step of forming a multilayer film reflection mirror 11 by lamination; a resonator lamination step of, after performing the multilayer film reflection mirror lamination step, laminating a GaN resonator 12 on a surface of the multilayer film reflection mirror; and a reflectance measurement step of measuring the reflectance of the GaN resonator 12 while performing the resonator lamination step, the wavelength of light used in the reflectance measurement step being longer than the resonant wavelength of the multilayer film reflection mirror 11 at room temperature.SELECTED DRAWING: Figure 1

The present invention provides a nitride semiconductor light-emitting element that can improve light emission output. [Solution] The nitride semiconductor light-emitting device comprises a substrate whose c-plane is the growth surface, a buffer layer formed on the growth surface, an n-type semiconductor layer containing Al, Ga, and N formed on the buffer layer, an active layer formed on the n-type semiconductor layer and having at least one well layer containing Al, Ga, and N, and a p-type semiconductor layer formed on the active layer. The nitride semiconductor light-emitting device emits ultraviolet light with a central wavelength of 365 nm or less. When the well layer closest to the p-type semiconductor layer among the at least one well layer is designated as the target well layer, the ratio of the carbon concentration Cw of the target well layer to the carbon concentration Cn of the n-type semiconductor layer, Cw / Cn, is 3.0 / 100 or less.

A light-emitting element includes: a semiconductor structure including: an n-side semiconductor layer including an n-type nitride semiconductor layer; a p-side semiconductor layer including a p-type nitride semiconductor layer; and an active layer disposed between the n-side semiconductor layer and the p-side semiconductor, the active layer including a well layer made of a nitride semiconductor. The p-side semiconductor layer includes, in order from an active layer side, a first layer including Ga, Al, In, and N, a second layer containing Ga, Al, and N, and a third layer including Ga and N, the second layer being thinner than the first layer. A bandgap energy of the second layer is larger than a bandgap energy of the well layer. A p-type impurity concentration of the third layer is higher than a p-type impurity concentration of the first layer. A composition ratio of Al in the second layer is higher than a composition ratio of Al in the first layer.

There is provided a manufacturing method for a nitride semiconductor device including: providing an amorphous protective film containing silicon above a nitride semiconductor layer; and performing heat treating on the nitride semiconductor layer provided with the protective film, under a pressure condition of 1 MPa or higher and 1 GPa or lower, and under a temperature condition of 1200° C. or higher and 1500° C. or lower. The protective film may be in contact with the nitride semiconductor layer. The protective film may contain at least one of SiO2, SiN, or SION.

The present invention provides a semiconductor device and a method for manufacturing a semiconductor device that can improve yield. [Solution] The semiconductor device comprises a substrate having a first surface and a second surface opposite to the first surface, a first nitride semiconductor layer having a third surface in contact with the second surface and a fourth surface opposite to the third surface, with a recess formed on the fourth surface, a second nitride semiconductor layer provided in the recess, and a first metal layer provided on the second nitride semiconductor layer, wherein through holes are formed in the substrate, the first nitride semiconductor layer and the second nitride semiconductor layer, penetrating the substrate, the first nitride semiconductor layer and the second nitride semiconductor layer and reaching the first metal layer, and the second metal layer is in contact with the first metal layer and covers the first surface and the inner wall surface of the through holes, the first metal layer contains cobalt, and the second nitride semiconductor layer contains 1.0 × 10 18 cm -3 It contains impurity atoms at the above concentrations.

A compound semiconductor substrate and a method for manufacturing the compound semiconductor substrate including the steps of forming an electronic traveling layer consisting of a first nitride semiconductor, forming a barrier layer consisting of a second nitride semiconductor with a wider band gap than a band gap of the first nitride semiconductor on the electronic traveling layer, and forming a cap layer with an organometallic vapor phase epitaxy on the barrier layer and in contact with the barrier layer. The cap layer has a C concentration of 5*1017 atoms / cm3 or more and 1*1020 atoms / cm3 or less, and consists of a nitride semiconductor. During the step forming the cap layer, source gas of the nitride semiconductor forming the cap layer and hydrocarbon gas are introduced to a top surface of the barrier layer.

Variations in characteristics of a device which are caused by buried gate electrodes are suppressed. A nitride semiconductor device includes: a substrate; a first nitride semiconductor layer; a second nitride semiconductor layer; a source electrode; a drain electrode; at least one blind hole reaching an interior of the first nitride semiconductor layer from an upper surface of the second nitride semiconductor layer; a buried gate electrode inside the blind hole; and a gate finger electrode across an upper surface of the buried gate electrode and the upper surface of the second nitride semiconductor layer, wherein a side surface of the blind hole is along a {1 −1 0 0} plane of the first nitride semiconductor layer.

III-Nitride semiconductor devices including parasitic current suppression are described. In one example, a semiconductor device (200) includes a semiconductor substrate (299) including an active region (204) and an isolation region (203) surrounding the active region (204). The active region (204) includes a source region (215A), a gate region (215B), and a drain region (215D), where the source region (215A), the gate region (215B), and the drain region (215D) extend parallel to each other. A III-N heterojunction structure (297) is disposed on the semiconductor substrate (299), the III-N heterojunction structure (297) including a buffer layer (295) on the semiconductor substrate (299) and a barrier layer (293) on the buffer layer (295). A III-N gate layer (205) is disposed on the barrier layer (293), the III-N gate layer (205) including a gate portion (205A) disposed in the gate region (215B) and a gate extension (207A) extending from the gate portion (205A) to the isolation region (203).