66 results about "Nitride semiconductors" patented technology

This nitride semiconductor device includes: a conductive substrate having a substrate upper surface; a high-resistance layer; a nitride semiconductor layer formed on the high-resistance layer; a first electrode (source electrode) formed on the nitride semiconductor layer; and a via. The high-resistance layer is formed on the substrate upper surface, and has a higher resistance value than does the conductive substrate. The via is electrically connected to the first electrode (source electrode), is provided so as to pass through the nitride semiconductor layer and the high-resistance layer, and contacts the substrate upper surface.

This invention provides a nitride LED epitaxial wafer, its fabrication method, and its application. The nitride LED epitaxial wafer includes a substrate, a composite buffer layer, a nitride buffer layer, a first nitride semiconductor layer, a nitride light-emitting layer, and a second nitride semiconductor layer stacked together. The composite buffer layer comprises n sets of stacked composite buffer sublayers. The first to (n-1)th sets of composite buffer sublayers respectively include a modulation sublayer, a first capping sublayer, a composite structure sublayer, and a second capping sublayer stacked together. The nth set of composite buffer sublayers includes a modulation sublayer, a first capping sublayer, and a composite structure sublayer stacked together, where n ≥ 2. The composite structure sublayer has a nanostructured pattern. By employing the solution provided by this invention, the problems of dislocations or defects caused by lattice constant and thermal mismatch can be overcome, enabling the development of multifunctional buffer technology.

This nitride semiconductor device (1) comprises a power FET (11), an ESD protection FET (12), a diode (13), and a resistor element (14). A gate structure (50G) of the power FET (11) includes a p-type semiconductor layer (52G) and a gate electrode (54G) that is Schottky-connected to the p-type semiconductor layer (52G). An anode structure (50A) of the diode (13) includes a p-type semiconductor layer (52A). The gate structure (50G), a drain structure (51D) of the ESD protection FET (12), and the anode structure (50A) are electrically connected to each other. A source structure (50S) of the power FET (11), a source structure (51S) of the ESD protection FET (12), and a terminal structure (50R) of the resistor element (14) are electrically connected to each other. A gate structure (51G) of the ESD protection FET (12), a cathode structure (50K) of the diode (13), and a terminal structure (51R) of the resistor element (14) are electrically connected to each other.

To provide a method for manufacturing a nitride semiconductor light-emitting element, capable of controlling to a desired resonator length with high precision and high reproducibility (using such as a reflectance spectrum measured on site in parallel) during the formation of a resonator of a GaN-based surface-emitting laser.SOLUTION: A method for manufacturing a nitride semiconductor light-emitting element includes: a multilayer film reflection mirror lamination step of forming a multilayer film reflection mirror 11 by lamination; a resonator lamination step of, after performing the multilayer film reflection mirror lamination step, laminating a GaN resonator 12 on a surface of the multilayer film reflection mirror; and a reflectance measurement step of measuring the reflectance of the GaN resonator 12 while performing the resonator lamination step, the wavelength of light used in the reflectance measurement step being longer than the resonant wavelength of the multilayer film reflection mirror 11 at room temperature.SELECTED DRAWING: Figure 1

The present invention provides a nitride semiconductor light-emitting element that can improve light emission output. [Solution] The nitride semiconductor light-emitting device comprises a substrate whose c-plane is the growth surface, a buffer layer formed on the growth surface, an n-type semiconductor layer containing Al, Ga, and N formed on the buffer layer, an active layer formed on the n-type semiconductor layer and having at least one well layer containing Al, Ga, and N, and a p-type semiconductor layer formed on the active layer. The nitride semiconductor light-emitting device emits ultraviolet light with a central wavelength of 365 nm or less. When the well layer closest to the p-type semiconductor layer among the at least one well layer is designated as the target well layer, the ratio of the carbon concentration Cw of the target well layer to the carbon concentration Cn of the n-type semiconductor layer, Cw / Cn, is 3.0 / 100 or less.

III-Nitride semiconductor devices including parasitic current suppression are described. In one example, a semiconductor device (200) includes a semiconductor substrate (299) including an active region (204) and an isolation region (203) surrounding the active region (204). The active region (204) includes a source region (215A), a gate region (215B), and a drain region (215D), where the source region (215A), the gate region (215B), and the drain region (215D) extend parallel to each other. A III-N heterojunction structure (297) is disposed on the semiconductor substrate (299), the III-N heterojunction structure (297) including a buffer layer (295) on the semiconductor substrate (299) and a barrier layer (293) on the buffer layer (295). A III-N gate layer (205) is disposed on the barrier layer (293), the III-N gate layer (205) including a gate portion (205A) disposed in the gate region (215B) and a gate extension (207A) extending from the gate portion (205A) to the isolation region (203).

A nitride semiconductor device including: a substrate; a channel layer provided above the substrate; a vertical transistor provided in a first region, the vertical transistor being a normally-on transistor; and a lateral transistor provided in a second region, the lateral transistor being a normally-off transistor, in which the vertical transistor includes: a first portion that is a portion of the channel layer and overlaps the first region in a plan view of the substrate; a first gate electrode; and a first drain electrode, the lateral transistor includes: a second portion that is a portion of the channel layer and overlaps the second region in the plan view; a second gate electrode; and a second source electrode, the first gate electrode and the second source electrode are electrically connected to each other, and a source potential of the vertical transistor and a drain potential of the lateral transistor are equal.

The present invention relates to a nitride semiconductor device formed on a diamond substrate and a method for manufacturing a nitride semiconductor device, and more specifically, to a method for manufacturing a nitride semiconductor device formed on a diamond substrate in which twinning defects in a diamond layer formed on the substrate are prevented depending on the type of substrate and the orientation of the crystal plane, and by forming a single-crystal nitride semiconductor device alone on the diamond layer or forming a single-crystal nitride semiconductor device and a diamond semiconductor device simultaneously, the nitride semiconductor device and the nitride semiconductor device have high voltage, high frequency, and radiation resistance characteristics and improved heat dissipation performance.

This invention provides a GaN crystal that can be used as a substrate in nitride semiconductor devices with lateral device structures such as GaN-HEMT; and a GaN substrate that can be used in the fabrication of nitride semiconductor devices with lateral device structures such as GaN-HEMT. The GaN crystal has a 5cm² diameter. 2 The surfaces with an inclination of less than 10 degrees relative to the (0001) crystal plane have a Mn concentration of 1.0 × 10⁻⁶. 16 atoms / cm 3 Above and less than 1.0 × 10 19 atoms / cm 3 The total donor impurity concentration is less than 5.0 × 10⁻⁶. 16 atoms / cm 3 .

To provide a nitride semiconductor device with a high threshold voltage and high reliability. [Solution] A first nitride semiconductor layer 13 constituting the channel layer, a second nitride semiconductor layer 14 having a larger band gap than the first nitride semiconductor layer 13 and constituting the carrier supply layer, and a third nitride semiconductor layer 21 containing acceptor-type impurities are sequentially stacked. The third nitride semiconductor layer 21 is island-shaped, and a plasma processing region 21a is formed on its surface. The gate electrode 22 is in Schottky contact with the plasma processing region 21a.

This invention provides a semiconductor device with a high activation rate for p-type impurities. [Solution] The method for manufacturing a semiconductor device comprises: a p-type layer formation step of forming a p-type layer 12 made of a group III nitride semiconductor doped with p-type impurities by MOCVD; an annealing step of performing an annealing treatment on the surface of the p-type layer 12 with at least a region contributing to the device operation exposed to activate the p-type impurities of the p-type layer 12; and an n-type layer formation step of forming an n-type layer (second n-type layer 13) made of an n-type group III nitride semiconductor on the p-type layer 12 by a formation method using materials that do not contain hydrogen in the raw materials and carrier gas.

Semiconductor unit (100) for a power converter, wherein the semiconductor unit (100) comprises a power semiconductor (102) having a III nitride semiconductor layer (110), and a drain contact (104) and a source contact (106), and wherein the power semiconductor (100) in an operating state has a conductive channel (108) of a two-dimensional electron gas in a III nitride semiconductor layer (110) facing away from the contacts (104, 106), and a printed circuit board (112) in which the power semiconductor (102) is embedded, wherein the printed circuit board (112) has a recess (114) leading to the III nitride semiconductor layer (110) for guiding a positively charged liquid coolant (116) for cooling the power semiconductor (100) and for neutralizing opposite the drain contact (104) accumulated negative electron charges (118) on the power semiconductor (102).

Increase pressure resistance. [Solution] The nitride semiconductor device 1 comprises a first nitride semiconductor layer 21 having an n-type conductivity, a second nitride semiconductor layer 22 having a p-type conductivity provided above the first nitride semiconductor layer 21, and a source electrode 23 that is in direct contact with the second nitride semiconductor layer 22. Two or more mesa structures 30 are provided in the terminal region 12 between the active region 10 of the nitride semiconductor device 1 and the inert region 11 surrounding the active region 10. In the mesa structure 30, the lower end 32 of the side wall 31 of the first mesa 30A is located in the second nitride semiconductor layer 22, the lower end 35 of the side wall 34 of the second and subsequent mesa 30B reach the first nitride semiconductor layer 21, and the mesa depth of the first stage is more than half the thickness of the second nitride semiconductor layer 22.

A light-receiving element according to an embodiment of the present invention includes: a nitride semiconductor layer; and a chalcogenide layer that is disposed above the nitride semiconductor layer, includes a transition metal, and is epitaxially grown on the nitride semiconductor layer.

A nitride semiconductor device includes a first nitride semiconductor layer, a second nitride semiconductor layer that is formed on the first nitride semiconductor layer, and a gate portion that is formed on the second nitride semiconductor layer. The gate portion includes a semiconductor gate layer of a ridge shape that is formed on the second nitride semiconductor layer and a gate electrode that is formed on the semiconductor gate layer. The semiconductor gate layer includes a first semiconductor gate layer that is constituted of a nitride semiconductor and a second semiconductor gate layer that is formed between the first semiconductor gate layer and the gate electrode. The nitride semiconductor device further includes a first dielectric film that covers a side surface of the semiconductor gate layer and that extends onto the second nitride semiconductor layer.

The present invention provides a nitride semiconductor device that can reduce on-resistance. [Solution] The nitride semiconductor device 200 includes a first nitride semiconductor layer 2, second nitride semiconductor layers 3, 3A located thereon and having a larger bandgap energy than the first nitride semiconductor layer, a third nitride semiconductor layer 4 located thereon and having a smaller bandgap energy than the second nitride semiconductor layer, a P-type semiconductor layer 6 electrically connected to the third nitride semiconductor layer, a control electrode 7 located thereon, a first electrode 8 located on the first nitride semiconductor layer and spaced apart from the third nitride semiconductor layer, and a second electrode 10 located spaced apart from the third nitride semiconductor layer which extends in the opposite direction from the first electrode across the control electrode when viewed in plan, and which reaches from the upper surface of the second nitride semiconductor layer to the first nitride semiconductor layer, or a second electrode 10 provided on the upper part of a diffusion layer 14 with a high impurity concentration that reaches from the upper surface of the second nitride semiconductor layer to the first nitride semiconductor layer.

The objective is to provide a semiconductor light-emitting element with reduced ripple in FFP (Flexible Printed Fluorescent Particle). The semiconductor light-emitting element includes a GaN substrate, a first nitride semiconductor portion disposed on the substrate and containing n-type impurities, a second nitride semiconductor portion disposed on the first nitride semiconductor portion and containing n-type impurities, and a third nitride semiconductor portion disposed on the second nitride semiconductor portion and containing n-type impurities. The concentration of n-type impurities in the first nitride semiconductor portion is greater than that in the third nitride semiconductor portion, and the concentration of n-type impurities in the second nitride semiconductor portion is greater than that in the third nitride semiconductor portion. The Al composition ratio of the second nitride semiconductor portion is greater than that of the first nitride semiconductor portion, and the Al composition ratio of the third nitride semiconductor portion is greater than that of the first nitride semiconductor portion.

The present invention provides a nitride semiconductor light-emitting element that can lower the forward voltage in a light-emitting element formed by tunnel junction of multiple semiconductor parts that emit ultraviolet light. [Solution] A light-emitting element comprising: a first semiconductor part having a first n-side semiconductor layer, a first active layer disposed on the first n-side semiconductor layer and emitting ultraviolet light, and a first p-side semiconductor layer disposed on the first active layer; and a second semiconductor part having a second n-side semiconductor layer disposed on the first semiconductor part, a second active layer disposed on the second n-side semiconductor layer and emitting ultraviolet light, and a second p-side semiconductor layer disposed on the second active layer, wherein the first p-side semiconductor layer comprises a first layer containing Al and a second layer disposed on the first layer and containing Al and p-type impurities; the second p-side semiconductor layer comprises a third layer containing Al and a fourth layer disposed on the third layer and containing Al and p-type impurities; the second n-side semiconductor layer is tunnel-junctioned with the second layer; and the thickness of the first layer is thinner than the thickness of the third layer.

This invention relates to a nitride semiconductor epitaxial wafer, its fabrication method, and optoelectronic devices. The nitride semiconductor epitaxial wafer comprises a growth substrate, an n-type nitride layer, a nitride diffusion layer, a composite light-emitting layer, a nitride barrier layer, and a p-type nitride layer, stacked sequentially. The composite light-emitting layer comprises spaced nanopillar spacers and light-emitting units disposed between adjacent nanopillar spacers. The nanopillar spacers separate the light-emitting units, making the light-emitting units nanostructured. This not only reduces the stress in the light-emitting layer within the light-emitting units and improves the composition incorporation and uniformity of the epitaxial layer, but also utilizes the quantum size confinement effect to reduce QCSE, improve the radiative recombination efficiency of electrons and holes, and reduce the carrier trapping effect caused by sidewall damage. This improves the luminous efficiency and brightness of the nitride semiconductor epitaxial wafer, reduces the full width at half maximum (FWHM) of the emission wavelength, and enhances the color purity for display applications.

A nitride semiconductor device includes: a first nitride semiconductor layer; a second nitride semiconductor layer located on the first nitride semiconductor layer, having a higher bandgap energy than the first nitride semiconductor layer; a third nitride semiconductor layer located on the second nitride semiconductor layer, having a lower bandgap energy than the second nitride semiconductor layer; a P-type semiconductor layer electrically connected to the third nitride semiconductor layer; a control electrode on the P-type semiconductor layer; a first electrode located on the first nitride semiconductor layer and separately disposed from the third nitride semiconductor layer; and a second electrode, which, when viewed from above, is separately disposed from the end of the third nitride semiconductor layer extending to the opposite side of the first electrode across the control electrode, and extends from the upper surface of the second nitride semiconductor layer to the first nitride semiconductor layer, or is disposed on the upper part of a diffusion layer extending from the upper surface of the second nitride semiconductor layer to the first nitride semiconductor layer and having a higher impurity concentration.

Provided is a group III element nitride semiconductor substrate which includes a first face and a second face and has a large diameter and with which the occurrence of chipping defects is suppressed when manufacturing a device. A group III element nitride semiconductor substrate according to an embodiment of the present invention includes a first face and a second face, and has a thickness of at least 100 μm, wherein: when, on a straight line from a centroid position on the surface of the first face to a centroid position on the surface of the second face, peak wave numbers corresponding to the E2 H phonon modes are measured at intervals of 5 μm from a spot corresponding to 5 μm inward from the surface of the first face to a spot corresponding to half of the thickness of the substrate and from a spot corresponding to 5 μm inward from the surface of the second face to a spot corresponding to half of the thickness of the substrate, and n peak wave numbers obtained through the measurement are B1-Bn (where n is the number of peak wave numbers measured and an integer obtained by rounding up digits after the decimal point of [(thickness (μm) of group III element nitride semiconductor substrate–5 (μm)) / 5 (μm)]), in order from the side of the surface of the first face, the difference (Bmax-Bmin) between the maximum peak wave number Bmax and the minimum peak wave number Bmin among the n measured values is at most 2.0 cm-1.

A patterned aluminum nitride (AlN) composite substrate and a preparation method thereof are provided. A single crystal AlN with a semi-suspended AlN structure is prepared on a high temperature-resistant substrate. A non-suspended AlN of the single crystal AlN is covered by an optical medium material while a suspended AlN is exposed. A surface of the suspended AlN with a low dislocation density and a low mismatch stress and distributed periodically is used as a nucleation growth zone of a nitride semiconductor. An epitaxial interface is changed from an AlN / high temperature-resistant substrate into a homogeneous or nearly-homogeneous interface between the nitride semiconductor and the AlN. In this way, the patterned AlN composite substrate is obtained.

Provided are a power device and a manufacturing method thereof. The power device includes an epitaxial structure, a doped nitride semiconductor layer, a passivation layer, a source and a drain. The epitaxial structure includes an active region and an edge region, where the edge region surrounds the active region and includes a first edge region and a second edge region, the first edge region of the epitaxial structure is an electrically isolated region, and a conductive channel is provided at an interface between the channel layer and the barrier layer in the second edge region. The doped nitride semiconductor layer includes a first region and a second region connected to each other, and a distance between an edge of the conductive channel of the second edge region and a vertical projection of an edge of the second region on the barrier layer is greater than a first preset value.

Manufacturing a nitride semiconductor light-emitting device includes a depositing an n-type cladding layer and an active layer with a multi-quantum well structure having a plurality of well layers on a substrate in a chamber. In depositing the active layer, a silicon source is not supplied into the chamber. The method includes supplying the silicon source into the chamber after depositing the n-type cladding layer and before depositing the active layer thereby, when a well layer located second from the n-type cladding layer side among the plurality of well layers is defined as a second well layer, a peak of distribution of a silicon concentration in a stacking direction of the n-type cladding layer and the active layer appears in a range where the second well layer is formed, and the silicon concentration at an apex of the peak is not less than 1.49×1018 atoms / cm3 and not more than 4.96×1018 atoms / cm3.

The present invention provides an optical device having a well layer made of a group III nitride semiconductor containing high crystal quality In. [Solution] The optical device using a group III nitride semiconductor is made of an n-type group III nitride semiconductor and comprises a pit generation layer 12 that generates a plurality of pits 25, a first periodic structure layer (periodic structure layer 13) formed on the pit generation layer and having a periodic structure in which group III nitride semiconductors of different compositions are alternately stacked, an intermediate layer 16 formed on the first periodic structure layer and made of an n-type group III nitride semiconductor, and a well layer 18 formed on the intermediate layer 16 and made of an undoped group III nitride semiconductor containing In, wherein the pits 25 extend from the pit generation layer 12 to the surface of the well layer 18.

The application discloses a no-interface wurtzite ferroelectric nitride memory, which comprises a nitride semiconductor substrate and a wurtzite ferroelectric dielectric layer in contact; the wurtzite ferroelectric dielectric layer is directly grown on the nitride semiconductor substrate by using a good lattice matching between the wurtzite ferroelectric material and the nitride substrate material, through an in-situ sputtering process, an atomic layer deposition process or an epitaxial growth process; and finally, the no-interface wurtzite ferroelectric nitride memory between the wurtzite ferroelectric material and the nitride semiconductor substrate is realized, so as to solve a series of problems such as additional power consumption and reliability degradation caused by the existing non-ideal interface layer of the ferroelectric memory. The no-interface wurtzite ferroelectric nitride memory provided by the application has low power consumption, high reliability, high switching ratio and high memory window, and can be applied to the development of high-computing-power, high-energy-efficiency, low-power-consumption and high-reliability storage and computing devices and chip technologies.

The present invention provides a method for manufacturing a group III nitride semiconductor that can improve crystallinity. [Solution] A method for manufacturing a group III nitride semiconductor, comprising: an alkali metal coating step of covering the surface 11a of a solid alkali metal 11 with a group III metal 12; a mixed melt generation step of melting the alkali metal 11 coated with the group III metal 12 together with carbon 13 to produce a mixed melt; and a crystal growth step of immersing a seed substrate in the mixed melt under a nitrogen-containing atmosphere to grow a group III nitride semiconductor on the seed substrate.

This application relates to semiconductor device technology and discloses a nitride semiconductor device and its manufacturing method, including a nitride substrate, a barrier layer, a source electrode, a drain electrode, a gate structure, and a strain-adjustable dielectric layer. The barrier layer is located above the nitride substrate. The gate structure is disposed on the barrier layer between the source electrode and the drain electrode, and includes a multilayer nitride stack structure. The multilayer nitride stack structure includes at least two P-type nitride layers and at least one etch stop layer sandwiched between the P-type nitride layers. The projection of the upper P-type nitride layer onto the surface of the barrier layer is within the projection range of the lower P-type nitride layer onto the surface of the barrier layer, and the lower P-type nitride layer extends horizontally towards the drain electrode, forming a stepped structure towards the drain electrode. The strain-adjustable dielectric layer covers the surface and is used to adjust the electric field density in the gate structure region and the gate-drain region. This application can improve the problem of electric field concentration in the gate structure region and the gate-drain region.

A nitride semiconductor transistor includes a channel layer and a first barrier layer overlapping the channel layer, the first barrier layer containing a rare earth group III element, aluminum, and nitrogen. The first barrier layer includes a first region having a first oxygen concentration equal to or less than 20 at.%, and a second region having a second oxygen concentration greater than 20 at.%. The first region is located between the channel layer and the second region. A thickness of the first region is greater than that of the second region. A maximum value of the second oxygen concentration is equal to or less than 50 at.%.

According to the present invention, the luminous efficiency of a nitride semiconductor element is improved. This nitride semiconductor element comprises: a nitride semiconductor substrate that contains Al; and a semiconductor multilayer part that is disposed on the nitride semiconductor substrate. The semiconductor multilayer part comprises: a cladding layer having a first conductivity type, the cladding layer containing a nitride semiconductor having the first conductivity type; a light emitting layer which is disposed on the cladding layer having the first conductivity type, and which is formed of a nitride semiconductor comprising one or more quantum wells; and a cladding layer having a second conductivity type, the cladding layer being disposed on the light emitting layer, and being formed of a nitride semiconductor containing Al and having the second conductivity type. The deviation α from the uniformity of the alloy in the surface direction of a waveguide layer having the second conductivity type is 130 meV to 350 meV (inclusive).