743 results about "Nitride semiconductors" patented technology

The present invention relates to a method for manufacturing a group 3 nitride semiconductor template and a semiconductor template manufactured thereby, wherein a laser lift-off technique and a chemical lift-off technique are used so that a high-quality group 3 nitride semiconductor layer can be formed on the top of a high heat dissipation support substrate having the same or a similar lattice constant and thermal expansion coefficient.

A nitride semiconductor device includes a semiconductor layered structure including a substrate, a channel layer, and a barrier layer. The channel layer is formed above the substrate and made of a nitride semiconductor layer. The barrier layer is formed on the channel layer, has a wider band gap than the channel layer, and is made of a nitride semiconductor layer. The semiconductor layered structure includes an isolation region in which impurities are implanted. The position of an impurity concentration peak in the depth direction in the isolation region is deeper than the interface between the barrier layer and the channel layer. The concentration of the impurities at the interface between the barrier layer and the channel layer in the isolation region is lower than the concentration at the impurity concentration peak.

A semiconductor device includes a first nitride semiconductor layer, a second nitride semiconductor layer provided on the first nitride semiconductor layer, the second nitride semiconductor layer having a band gap larger than the first nitride semiconductor layer, a first electrode provided on the second nitride semiconductor layer, a second electrode provided on the second nitride semiconductor layer, a first insulating film provided between the first electrode and the second electrode on the second nitride semiconductor layer, the first insulating film being in connect with the second nitride semiconductor layer and including a first insulating material, a second insulating film provided on the second nitride semiconductor layer between the first electrode and the first insulating film, on the first insulating film, and on the second nitride semiconductor layer between the first insulating film and the second electrode, the second insulating film including a second insulating material, a third electrode provided on the second insulating film between the first electrode and the first insulating film, and a fourth electrode including a first electrode portion and a second electrode portion, the first electrode portion being provided on the second insulating film between the third electrode and the first insulating film, and the second electrode portion being provided on the second insulating film on the first insulating film and being electrically connected to the first electrode portion.

The invention relates to a P-type GaN LED epitaxial structure based on segmented annealing and compensation doping and a preparation method thereof, and belongs to the technical field of nitride semiconductor epitaxial growth and doping activation. The epitaxial structure sequentially comprises a buffer layer, a non-doped GaN layer, an N-type GaN layer, a multi-quantum well active layer, a P-type AlGaN electron barrier layer, a P-type GaN layer and an MgN compensation layer which are arranged on the substrate layer; wherein the MgN compensation layer is a high-concentration magnesium-doped nitride semiconductor layer, is arranged on the P-type GaN layer, and is used for compensating Mg loss and inhibiting nitrogen vacancy formation in the subsequent annealing process. The preparation method comprises the steps of performing multi-stage annealing treatment on the P-type GaN layer, performing epitaxial growth and annealing on the compensation layer, and finally performing low-temperature post-treatment annealing to form a surface passivation region. According to the structure, the Mg activation efficiency and the hole concentration are remarkably improved through an in-vivo activation and surface compensation synergistic mechanism, the contact resistance is reduced, the conductivity and the light-emitting performance of an LED device are improved, and the structure has excellent implementability and industrialization prospects.

The present invention is a substrate for a high-frequency device in which a nitride semiconductor film is formed on an SOI substrate, the SOI substrate being a TRSOI substrate in which a trap-rich layer formed on a base substrate and an SOI layer comprising single crystal silicon are bonded with an oxide film interposed therebetween, the SOI layer having a resistivity of 1 k [omega] * cm or more and a crystal plane orientation of (111). And the oxygen concentration is 14.8 ppma or less. As a result, a substrate for a high-frequency device having excellent high-frequency characteristics and a method for manufacturing the same are provided.

A semiconductor device includes a substrate, a buffer layer over the substrate, an n-type electrode overlapping the buffer layer, and an electron injection layer in contact with the n-type electrode over the buffer layer. The electron injection layer includes an n-type dopant and a first nitride semiconductor containing gallium. The first nitride semiconductor further contains at least one element of aluminum and indium.

The invention discloses a method for manufacturing a high-power nitride semiconductor microwave transistor on a gallium nitride substrate. The method mainly solves the problems that an existing device has a parasitic electric leakage channel at a homoepitaxial interface and is low in breakdown voltage. According to the scheme, the method comprises the following steps: firstly, selecting a p-type gallium nitride single-crystal substrate, carrying out surface pretreatment on the p-type gallium nitride single-crystal substrate to obtain a p-type gallium nitride single-crystal substrate containing a p-type AlN electric leakage isolation layer, and then sequentially growing a GaN channel layer, an AlN insertion layer and a barrier layer on the pretreated substrate; and finally, preparing an insulated gate dielectric layer and a gate electrode on the barrier layer, and manufacturing a source electrode and a drain electrode on two sides to complete device manufacturing. Through in-situ compensation of donor impurities based on the p-type AlN electric leakage isolation layer and ion implantation, complete isolation of a parasitic electric leakage channel at a homoepitaxial interface and a 2DEG conductive channel at a homoepitaxial GaN heterojunction interface is realized, transverse electric leakage of the device is effectively inhibited, and the voltage endurance capability and the output power of the device are improved.

The present invention relates to a method for manufacturing a Group III nitride semiconductor template and a Group III nitride semiconductor template manufactured thereby and, more specifically, to a method for manufacturing a Group III nitride semiconductor template and a Group III nitride semiconductor template manufactured thereby, wherein a seed layer is formed of a single-crystal metal oxide having a corundum crystal structure so that a high-quality Group III nitride semiconductor device active layer can be re-grown.

A new semiconductor structure is disclosed. The semiconductor structure includes patterned dielectric layers disposed between the field plates and the channel layer. These patterned dielectric layers serve to further shape the electric field in the channel layer. This structure is not only applicable to III-nitride semiconductor devices, such as transistors, diodes or any other devices, but also is applicable to other semiconductor devices, such as Si LDMOS, SiC transistors, GaAs transistors.

A light emitting element includes, successively from a lower side to an upper side, a first light emitting part having a first active layer, a tunnel junction part, and a second light emitting part having a second active layer. The first active layer includes a plurality of first well layers, and a first barrier layer positioned between two adjacent first well layers among the first well layers. The second active layer includes a plurality of second well layers, and a second barrier layer positioned between two adjacent second well layers among the second well layers. The second barrier layer is a nitride semiconductor layer containing an n-type impurity and gallium, and has an n-type impurity concentration higher than that of the first barrier layer. An n-type impurity concentration peak in the second barrier layer is located on a first light emitting part side.

To provide a liquid dispensing device that can increase the frequency of the drive signal. [Solution] A capacitive load drive circuit that outputs a drive signal to displace a capacitive load comprises: an amplification circuit that outputs an amplified modulated signal by driving a first transistor that is driven in accordance with a first gate drive signal corresponding to a modulated signal obtained by modulating a base drive signal output by a modulation circuit, and a second transistor that is driven in accordance with a second gate drive signal corresponding to the modulated signal; and a demodulation circuit that outputs a drive signal obtained by demodulating the amplified modulated signal, wherein at least one of the first transistor and the second transistor comprises a first layer containing a first nitride semiconductor and a second layer containing a second nitride semiconductor having a larger band gap than the first nitride semiconductor, with the second layer positioned above the first layer, in a liquid dispensing device.

Provided is an n-type GaN crystal, in which a donor impurity contained at the highest concentration is Ge, and which has a room-temperature resistivity of lower than 0.03 Ω·cm and a (004) XRD rocking curve FWHM of less than 20 arcsec. The n-type GaN crystal has two main surfaces, each having an area of 3 cm2 or larger. One of the two main surfaces can have a Ga polarity and can be inclined at an angle of 0° to 10° with respect to a (0001) crystal plane. Further, the n-type GaN crystal can have a diameter of 20 mm or larger.

A nitride semiconductor layer includes a first layer, a second layer, and a p-type semiconductor layer. The p-type semiconductor layer includes a connection part connected with a source electrode, and an extension part extending in a first direction through the nitride semiconductor layer from the connection part. The extension part is positioned between a first interface between the first layer and the second layer, and a second interface between a substrate and the nitride semiconductor layer. An end of the extension part is positioned between a position of an end of a gate electrode at a drain electrode side in the first direction and a position of an end of the drain electrode at the gate electrode side in the first direction.

The invention provides a nitride semiconductor laser. The laser comprises a substrate, a lower coating layer, a lower waveguide layer, an active layer, an upper waveguide layer, an electron blocking layer and an upper coating layer which are sequentially arranged from bottom to top. And the lower waveguide layer comprises any one or a combination of more of InGaN, GaN, InN, AlInGaN, an InGaN / GaN superlattice, an InGaN / AlGaN superlattice, an InGaN / AlGaN superlattice, an InGaN / AlInN superlattice and an InGaN / AlInGaN superlattice. The peak rate electric field distribution of the lower waveguide layer has an arc distribution, and the peak rate electric field distribution has a curve distribution of a function y = logax (a > 1). The drift rate distribution of the saturated electrons of the lower waveguide layer has an arc-shaped distribution, and the drift rate distribution of the saturated electrons has a curve distribution of a third quadrant of a function y = x-b (b > 1, b is an odd number). The density distribution of valence band effective states of the lower waveguide layer has a curve distribution of a third quadrant of a function y = (cx + 1) / (cx-1) (c > 1).

[Task] A semiconductor laser element with reduced light loss is provided. [Solution] A semiconductor laser element emits ultraviolet light and includes an n-side cladding layer, an n-side guide layer, an active layer, a p-side guide layer, and a p-side cladding layer, each made of a nitride semiconductor, in this order upwards. The semiconductor laser element includes a first surface and a ridge portion protruding upwards from the first surface. The first surface is located at the top with respect to a lower end of the p-side guide layer and at the bottom with respect to an upper end of the p-side guide layer. A thickness of the n-side guide layer is thinner than a thickness of the n-side cladding layer. An Al composition ratio of the n-side guide layer is smaller than an Al composition ratio of the n-side cladding layer.a thickness of the p-side guide layer is thinner than a thickness of the p-side cladding layer and thinner than the thickness of the n-side guide layer, and an Al composition ratio of the p-side guide layer is smaller than an Al composition ratio of the p-side cladding layer.,

A surface-emitting laser element includes: a first guide layer including a photonic crystal layer that is formed on a c plane of a group-3 nitride semiconductor and includes air holes arranged with two-dimensional periodicity in a plane parallel to the photonic crystal layer, and an embedding layer that is formed on the photonic crystal layer and closes the air holes; an active layer formed on the first guide layer; and a second guide layer formed on the active layer, wherein an air hole set including at least a main air hole and a sub-air hole smaller in size than the main air hole is arranged at each square lattice point in the plane parallel to the photonic crystal layer, and wherein the main air hole has a regular-hexagonal prism shape, a long-hexagonal prism shape, or an elliptic cylindrical shape with a major axis parallel to a <11-20> axis.

A semiconductor device, comprising, a semiconductor substrate, a III-N semiconductor layer over the semiconductor substrate, a contact pad on the III-N semiconductor layer, a first dielectric layer over the III-N semiconductor layer, a first metal contact through the first dielectric layer and contacting the contact pad, and a second metal contact, including a first side contacting the first dielectric layer and a second side contacting a second dielectric layer, and contacting the semiconductor substrate.

A new transistor structure for use with III-Nitride semiconductor structures is disclosed. The transistor includes heavily doped n++ layers located in the source region and the drain region. The source and drain electrodes are disposed on their respective heavily doped n++ layer. Further, in some embodiments, a portion of the gate electrode may be disposed on one or both of the heavily doped n++ regions. These regions improve the on-resistance of the transistor, especially for low voltage applications.

According to the nitride semiconductor device and the power device based on the nitride semiconductor material, grooves which are periodically arranged in the Z direction are formed in a nitride semiconductor layer between a grid electrode structure and a drain electrode contact hole, when the device is turned on, the current direction is the X direction, the current path area in the Y-Z plane is increased, and resistance can be reduced.

Provided is an n-type GaN crystal, which has two main surfaces facing opposite directions from each other. One of the two main surfaces has a Ga polarity and is inclined at an angle of 0° to 10° with respect to the (0001) crystal plane. The n-type GaN crystal yields at least one X-ray anomalous transmission image having a square area of 10 mm×10 mm, preferably 15 mm×15 mm, and more preferably 20 mm×20 mm. In addition, the n-type GaN crystal has a Si concentration of 5×1016 atoms / cm3 or higher, O concentration of 3×1016 atoms / cm3 or lower, and / or a H concentration of 1×1017 atoms / cm3 or lower.

This semiconductor device includes a substrate, a channel layer provided on one side of a surface of the substrate and including a first nitride semiconductor having a first bandgap, a barrier layer provided on an opposite side of the channel layer from the substrate and including a second nitride semiconductor that includes Alx1Iny1Ga(1−x1−y1)N (0<x1<1, 0<y1<1) and has a second bandgap larger than the first bandgap of the first nitride semiconductor, and an intermediate layer provided in the barrier layer and including a third nitride semiconductor that includes Alx2Iny2Ga(1−x2−y2)N (0≤x2<1, 0≤y2<1), and the semiconductor device satisfies (1−x1−y1)<(1−x2−y2).

A semiconductor device includes: a substrate; a channel layer; a nitride semiconductor layer that includes a barrier layer; a source electrode; a drain electrode; a gate electrode; and an insulating layer. The gate electrode includes a junction portion and a drain-side protruding portion. The insulating layer includes an in-situ Si3N4 film and an ex-situ Si3N4 film. At least one of the following is satisfied: (a) the halogen concentration of the in-situ Si3N4 film is lower than the halogen concentration of the ex-situ Si3N4 film; or (b) the interface oxygen concentration between the in-situ Si3N4 film and the nitride semiconductor layer is lower than the interface oxygen concentration between the ex-situ Si3N4 film and the in-situ Si3N4 film.

A composite substrate has a group 13 nitride semiconductor substrate having a first main surface and a second main surface and a supporting substrate having a bonding surface bonded with the first main surface of the group 13 nitride semiconductor substrate. The supporting substrate has a bonding region composed of silicon carbide having an average micropipe density of 10 cm−2 or higher and 100 cm−2 or lower at the bonding surface of the supporting substrate or composed of synthetic diamond having an atomic ratio of nitrogen to carbon atoms of 500 ppm or higher and 2000 ppm or lower.

This nitride semiconductor device includes: a conductive substrate having a substrate upper surface; a high-resistance layer; a nitride semiconductor layer formed on the high-resistance layer; a first electrode (source electrode) formed on the nitride semiconductor layer; and a via. The high-resistance layer is formed on the substrate upper surface, and has a higher resistance value than does the conductive substrate. The via is electrically connected to the first electrode (source electrode), is provided so as to pass through the nitride semiconductor layer and the high-resistance layer, and contacts the substrate upper surface.

A nitride semiconductor device (10) is provided with a first nitride semiconductor layer (16), a second nitride semiconductor layer (18) formed on the first nitride semiconductor layer (16) and having a band gap larger than that of the first nitride semiconductor layer (16), and a gate electrode (32), a source electrode (24), and a drain electrode (26) formed above the second nitride semiconductor layer (18). The first nitride semiconductor layer (16) is a layer containing GaN. The first nitride semiconductor layer (16) has a half-value width of an X-ray rocking curve with respect to the (102) plane of from 1100 arcsec to 1400 arcsec (inclusive).

An n-type ohmic electrode 30 is provided on an n-type group III nitride semiconductor layer 10. The n-type ohmic electrode 30 has an Al layer 33 and a second direction-side Al-Ti region 34 located, relative to the Al layer 33, in a second direction opposite to a first direction which is toward the n-type group III nitride semiconductor layer 10. The second direction-side Al-Ti region 34 contains 50 at% or more of Al, 5-30 at% of Ti, and 10 at% or less of O.

The application provides a nitride semiconductor laser with an optical field regulation layer, comprising, from bottom to top, a substrate, a lower limiting layer, a lower waveguide layer, an active layer, an upper waveguide layer, an electron blocking layer and an upper limiting layer, wherein the lower waveguide layer comprises a first lower waveguide layer and a second lower waveguide layer, the first lower waveguide layer is located below the second lower waveguide layer, a first optical field regulation layer is arranged between the first lower waveguide layer and the lower limiting layer, a second optical field regulation layer is arranged between the first lower waveguide layer and the second lower waveguide layer, the first lower waveguide layer, the second lower waveguide layer and the second optical field regulation layer all have an In element concentration variation trend, and the first optical field regulation layer has an Al element concentration variation trend. The application can inhibit the refractive index dispersion of the laser, reduce the influence of the high-concentration carrier concentration fluctuation of the lower waveguide layer on the refractive index variation of the active layer and the lower waveguide layer, improve the confinement factor of the laser and enhance the mode gain of the laser.

A light emitting diode includes an n-type nitride semiconductor layer, a V-pit generation layer disposed on the n-type nitride semiconductor layer and having V-pits, an active layer disposed on the V-pit generation layer and including a first well region formed along a flat surface of the V-pit generation layer and a second well region formed in the V-pit of the V-pit generation layer, a p-type nitride semiconductor layer disposed on the active layer and a sub-emission layer interposed between the n-type nitride semiconductor layer and the p-type nitride semiconductor layer and disposed near the active layer. The sub-emission layer may emit light having a peak wavelength within a range of wavelengths shorter than a peak wavelength of the first well region, and light emitted from the light emitting diode is within a range of 0.205≤X≤0.495 and 0.265≤Y≤0.450 in CIE color coordinates (X, Y).

The present application relates to a manufacturing method of a nitride semiconductor substrate, a nitride semiconductor substrate, and a laminated structure. The manufacturing method has a process of preparing a base substrate; a first process of directly epitaxially growing a single crystal of a Group III nitride semiconductor having a top surface with a (0001) surface exposed on a main surface of the base substrate, causing the top surface to have a plurality of recesses composed of inclined interfaces other than the (0001) surface, causing the inclined interfaces to gradually expand as they go upward from the main surface of the base substrate, and causing the (0001) surface to disappear from the top surface, thereby growing a first layer having a surface composed only of the inclined interfaces; and a second process of epitaxially growing a single crystal of the Group III nitride semiconductor on the first layer, causing the inclined interfaces to disappear, and growing a second layer having a mirror-finished surface.

The present invention relates to a method of manufacturing a group 3 nitride semiconductor template with improved bonding layer quality, and more specifically, to a method of manufacturing a group 3 nitride semiconductor template having a high-quality group 3 nitride semiconductor seed layer, which can significantly improve the quality of a bonding layer by performing annealing on the bonding layer in two stages depending on a temperature.