567 results about "Nitride semiconductors" patented technology

The present invention relates to a method for manufacturing a group 3 nitride semiconductor template and a semiconductor template manufactured thereby, wherein a laser lift-off technique and a chemical lift-off technique are used so that a high-quality group 3 nitride semiconductor layer can be formed on the top of a high heat dissipation support substrate having the same or a similar lattice constant and thermal expansion coefficient.

A nitride semiconductor device includes a semiconductor layered structure including a substrate, a channel layer, and a barrier layer. The channel layer is formed above the substrate and made of a nitride semiconductor layer. The barrier layer is formed on the channel layer, has a wider band gap than the channel layer, and is made of a nitride semiconductor layer. The semiconductor layered structure includes an isolation region in which impurities are implanted. The position of an impurity concentration peak in the depth direction in the isolation region is deeper than the interface between the barrier layer and the channel layer. The concentration of the impurities at the interface between the barrier layer and the channel layer in the isolation region is lower than the concentration at the impurity concentration peak.

The invention relates to a P-type GaN LED epitaxial structure based on segmented annealing and compensation doping and a preparation method thereof, and belongs to the technical field of nitride semiconductor epitaxial growth and doping activation. The epitaxial structure sequentially comprises a buffer layer, a non-doped GaN layer, an N-type GaN layer, a multi-quantum well active layer, a P-type AlGaN electron barrier layer, a P-type GaN layer and an MgN compensation layer which are arranged on the substrate layer; wherein the MgN compensation layer is a high-concentration magnesium-doped nitride semiconductor layer, is arranged on the P-type GaN layer, and is used for compensating Mg loss and inhibiting nitrogen vacancy formation in the subsequent annealing process. The preparation method comprises the steps of performing multi-stage annealing treatment on the P-type GaN layer, performing epitaxial growth and annealing on the compensation layer, and finally performing low-temperature post-treatment annealing to form a surface passivation region. According to the structure, the Mg activation efficiency and the hole concentration are remarkably improved through an in-vivo activation and surface compensation synergistic mechanism, the contact resistance is reduced, the conductivity and the light-emitting performance of an LED device are improved, and the structure has excellent implementability and industrialization prospects.

A semiconductor device includes a substrate, a buffer layer over the substrate, an n-type electrode overlapping the buffer layer, and an electron injection layer in contact with the n-type electrode over the buffer layer. The electron injection layer includes an n-type dopant and a first nitride semiconductor containing gallium. The first nitride semiconductor further contains at least one element of aluminum and indium.

A light emitting element includes, successively from a lower side to an upper side, a first light emitting part having a first active layer, a tunnel junction part, and a second light emitting part having a second active layer. The first active layer includes a plurality of first well layers, and a first barrier layer positioned between two adjacent first well layers among the first well layers. The second active layer includes a plurality of second well layers, and a second barrier layer positioned between two adjacent second well layers among the second well layers. The second barrier layer is a nitride semiconductor layer containing an n-type impurity and gallium, and has an n-type impurity concentration higher than that of the first barrier layer. An n-type impurity concentration peak in the second barrier layer is located on a first light emitting part side.

To provide a liquid dispensing device that can increase the frequency of the drive signal. [Solution] A capacitive load drive circuit that outputs a drive signal to displace a capacitive load comprises: an amplification circuit that outputs an amplified modulated signal by driving a first transistor that is driven in accordance with a first gate drive signal corresponding to a modulated signal obtained by modulating a base drive signal output by a modulation circuit, and a second transistor that is driven in accordance with a second gate drive signal corresponding to the modulated signal; and a demodulation circuit that outputs a drive signal obtained by demodulating the amplified modulated signal, wherein at least one of the first transistor and the second transistor comprises a first layer containing a first nitride semiconductor and a second layer containing a second nitride semiconductor having a larger band gap than the first nitride semiconductor, with the second layer positioned above the first layer, in a liquid dispensing device.

A nitride semiconductor layer includes a first layer, a second layer, and a p-type semiconductor layer. The p-type semiconductor layer includes a connection part connected with a source electrode, and an extension part extending in a first direction through the nitride semiconductor layer from the connection part. The extension part is positioned between a first interface between the first layer and the second layer, and a second interface between a substrate and the nitride semiconductor layer. An end of the extension part is positioned between a position of an end of a gate electrode at a drain electrode side in the first direction and a position of an end of the drain electrode at the gate electrode side in the first direction.

The invention provides a nitride semiconductor laser. The laser comprises a substrate, a lower coating layer, a lower waveguide layer, an active layer, an upper waveguide layer, an electron blocking layer and an upper coating layer which are sequentially arranged from bottom to top. And the lower waveguide layer comprises any one or a combination of more of InGaN, GaN, InN, AlInGaN, an InGaN / GaN superlattice, an InGaN / AlGaN superlattice, an InGaN / AlGaN superlattice, an InGaN / AlInN superlattice and an InGaN / AlInGaN superlattice. The peak rate electric field distribution of the lower waveguide layer has an arc distribution, and the peak rate electric field distribution has a curve distribution of a function y = logax (a > 1). The drift rate distribution of the saturated electrons of the lower waveguide layer has an arc-shaped distribution, and the drift rate distribution of the saturated electrons has a curve distribution of a third quadrant of a function y = x-b (b > 1, b is an odd number). The density distribution of valence band effective states of the lower waveguide layer has a curve distribution of a third quadrant of a function y = (cx + 1) / (cx-1) (c > 1).

[Task] A semiconductor laser element with reduced light loss is provided. [Solution] A semiconductor laser element emits ultraviolet light and includes an n-side cladding layer, an n-side guide layer, an active layer, a p-side guide layer, and a p-side cladding layer, each made of a nitride semiconductor, in this order upwards. The semiconductor laser element includes a first surface and a ridge portion protruding upwards from the first surface. The first surface is located at the top with respect to a lower end of the p-side guide layer and at the bottom with respect to an upper end of the p-side guide layer. A thickness of the n-side guide layer is thinner than a thickness of the n-side cladding layer. An Al composition ratio of the n-side guide layer is smaller than an Al composition ratio of the n-side cladding layer.a thickness of the p-side guide layer is thinner than a thickness of the p-side cladding layer and thinner than the thickness of the n-side guide layer, and an Al composition ratio of the p-side guide layer is smaller than an Al composition ratio of the p-side cladding layer.,

A surface-emitting laser element includes: a first guide layer including a photonic crystal layer that is formed on a c plane of a group-3 nitride semiconductor and includes air holes arranged with two-dimensional periodicity in a plane parallel to the photonic crystal layer, and an embedding layer that is formed on the photonic crystal layer and closes the air holes; an active layer formed on the first guide layer; and a second guide layer formed on the active layer, wherein an air hole set including at least a main air hole and a sub-air hole smaller in size than the main air hole is arranged at each square lattice point in the plane parallel to the photonic crystal layer, and wherein the main air hole has a regular-hexagonal prism shape, a long-hexagonal prism shape, or an elliptic cylindrical shape with a major axis parallel to a <11-20> axis.

According to the nitride semiconductor device and the power device based on the nitride semiconductor material, grooves which are periodically arranged in the Z direction are formed in a nitride semiconductor layer between a grid electrode structure and a drain electrode contact hole, when the device is turned on, the current direction is the X direction, the current path area in the Y-Z plane is increased, and resistance can be reduced.

Provided is an n-type GaN crystal, which has two main surfaces facing opposite directions from each other. One of the two main surfaces has a Ga polarity and is inclined at an angle of 0° to 10° with respect to the (0001) crystal plane. The n-type GaN crystal yields at least one X-ray anomalous transmission image having a square area of 10 mm×10 mm, preferably 15 mm×15 mm, and more preferably 20 mm×20 mm. In addition, the n-type GaN crystal has a Si concentration of 5×1016 atoms / cm3 or higher, O concentration of 3×1016 atoms / cm3 or lower, and / or a H concentration of 1×1017 atoms / cm3 or lower.

This semiconductor device includes a substrate, a channel layer provided on one side of a surface of the substrate and including a first nitride semiconductor having a first bandgap, a barrier layer provided on an opposite side of the channel layer from the substrate and including a second nitride semiconductor that includes Alx1Iny1Ga(1−x1−y1)N (0<x1<1, 0<y1<1) and has a second bandgap larger than the first bandgap of the first nitride semiconductor, and an intermediate layer provided in the barrier layer and including a third nitride semiconductor that includes Alx2Iny2Ga(1−x2−y2)N (0≤x2<1, 0≤y2<1), and the semiconductor device satisfies (1−x1−y1)<(1−x2−y2).

A semiconductor device includes: a substrate; a channel layer; a nitride semiconductor layer that includes a barrier layer; a source electrode; a drain electrode; a gate electrode; and an insulating layer. The gate electrode includes a junction portion and a drain-side protruding portion. The insulating layer includes an in-situ Si3N4 film and an ex-situ Si3N4 film. At least one of the following is satisfied: (a) the halogen concentration of the in-situ Si3N4 film is lower than the halogen concentration of the ex-situ Si3N4 film; or (b) the interface oxygen concentration between the in-situ Si3N4 film and the nitride semiconductor layer is lower than the interface oxygen concentration between the ex-situ Si3N4 film and the in-situ Si3N4 film.

This nitride semiconductor device includes: a conductive substrate having a substrate upper surface; a high-resistance layer; a nitride semiconductor layer formed on the high-resistance layer; a first electrode (source electrode) formed on the nitride semiconductor layer; and a via. The high-resistance layer is formed on the substrate upper surface, and has a higher resistance value than does the conductive substrate. The via is electrically connected to the first electrode (source electrode), is provided so as to pass through the nitride semiconductor layer and the high-resistance layer, and contacts the substrate upper surface.

An n-type ohmic electrode 30 is provided on an n-type group III nitride semiconductor layer 10. The n-type ohmic electrode 30 has an Al layer 33 and a second direction-side Al-Ti region 34 located, relative to the Al layer 33, in a second direction opposite to a first direction which is toward the n-type group III nitride semiconductor layer 10. The second direction-side Al-Ti region 34 contains 50 at% or more of Al, 5-30 at% of Ti, and 10 at% or less of O.

The application provides a nitride semiconductor laser with an optical field regulation layer, comprising, from bottom to top, a substrate, a lower limiting layer, a lower waveguide layer, an active layer, an upper waveguide layer, an electron blocking layer and an upper limiting layer, wherein the lower waveguide layer comprises a first lower waveguide layer and a second lower waveguide layer, the first lower waveguide layer is located below the second lower waveguide layer, a first optical field regulation layer is arranged between the first lower waveguide layer and the lower limiting layer, a second optical field regulation layer is arranged between the first lower waveguide layer and the second lower waveguide layer, the first lower waveguide layer, the second lower waveguide layer and the second optical field regulation layer all have an In element concentration variation trend, and the first optical field regulation layer has an Al element concentration variation trend. The application can inhibit the refractive index dispersion of the laser, reduce the influence of the high-concentration carrier concentration fluctuation of the lower waveguide layer on the refractive index variation of the active layer and the lower waveguide layer, improve the confinement factor of the laser and enhance the mode gain of the laser.

A light emitting diode includes an n-type nitride semiconductor layer, a V-pit generation layer disposed on the n-type nitride semiconductor layer and having V-pits, an active layer disposed on the V-pit generation layer and including a first well region formed along a flat surface of the V-pit generation layer and a second well region formed in the V-pit of the V-pit generation layer, a p-type nitride semiconductor layer disposed on the active layer and a sub-emission layer interposed between the n-type nitride semiconductor layer and the p-type nitride semiconductor layer and disposed near the active layer. The sub-emission layer may emit light having a peak wavelength within a range of wavelengths shorter than a peak wavelength of the first well region, and light emitted from the light emitting diode is within a range of 0.205≤X≤0.495 and 0.265≤Y≤0.450 in CIE color coordinates (X, Y).

The present application relates to a manufacturing method of a nitride semiconductor substrate, a nitride semiconductor substrate, and a laminated structure. The manufacturing method has a process of preparing a base substrate; a first process of directly epitaxially growing a single crystal of a Group III nitride semiconductor having a top surface with a (0001) surface exposed on a main surface of the base substrate, causing the top surface to have a plurality of recesses composed of inclined interfaces other than the (0001) surface, causing the inclined interfaces to gradually expand as they go upward from the main surface of the base substrate, and causing the (0001) surface to disappear from the top surface, thereby growing a first layer having a surface composed only of the inclined interfaces; and a second process of epitaxially growing a single crystal of the Group III nitride semiconductor on the first layer, causing the inclined interfaces to disappear, and growing a second layer having a mirror-finished surface.

The present invention relates to a method of manufacturing a group 3 nitride semiconductor template with improved bonding layer quality, and more specifically, to a method of manufacturing a group 3 nitride semiconductor template having a high-quality group 3 nitride semiconductor seed layer, which can significantly improve the quality of a bonding layer by performing annealing on the bonding layer in two stages depending on a temperature.

A nitride semiconductor and method of making the same are provided. In embodiments, a method for manufacturing a nitride semiconductor includes: providing a nitride semiconductor material including at least one main dopant defining a p-type portion; doping the nitride semiconductor material with at least one co-dopant co-located with the main dopant, wherein the co-dopant reduces gas-enhanced diffusion of the main dopant by a component in an ambient gas during annealing; and annealing the nitride semiconductor material under pressure, thereby producing an annealed nitride semiconductor material with an activated main dopant. In implementations, a nitride semiconductor is produced including an annealed nitride semiconductor material doped with magnesium (Mg) and oxygen (O) in an activated p-type portion, wherein the Mg and O are present at a ratio of 2:1.

The present disclosure provides a nitride semiconductor transistor capable of improving distortion characteristics. The nitride semiconductor transistor includes: a nitride semiconductor layer having a channel layer and a barrier layer overlapping each other and having a first polarization in a first direction; a source electrode, a drain electrode, and a gate electrode in contact with the nitride semiconductor layer; a ferroelectric layer between the gate electrode and the drain electrode in plan view and having a second polarization in a second direction opposite to the first direction; the field plate is electrically connected to the source electrode and located above the nitride semiconductor layer, and the ferroelectric layer is located between the nitride semiconductor layer and the field plate.

This invention provides a nitride LED epitaxial wafer, its fabrication method, and its application. The nitride LED epitaxial wafer includes a substrate, a composite buffer layer, a nitride buffer layer, a first nitride semiconductor layer, a nitride light-emitting layer, and a second nitride semiconductor layer stacked together. The composite buffer layer comprises n sets of stacked composite buffer sublayers. The first to (n-1)th sets of composite buffer sublayers respectively include a modulation sublayer, a first capping sublayer, a composite structure sublayer, and a second capping sublayer stacked together. The nth set of composite buffer sublayers includes a modulation sublayer, a first capping sublayer, and a composite structure sublayer stacked together, where n ≥ 2. The composite structure sublayer has a nanostructured pattern. By employing the solution provided by this invention, the problems of dislocations or defects caused by lattice constant and thermal mismatch can be overcome, enabling the development of multifunctional buffer technology.

This nitride semiconductor device (1) comprises a power FET (11), an ESD protection FET (12), a diode (13), and a resistor element (14). A gate structure (50G) of the power FET (11) includes a p-type semiconductor layer (52G) and a gate electrode (54G) that is Schottky-connected to the p-type semiconductor layer (52G). An anode structure (50A) of the diode (13) includes a p-type semiconductor layer (52A). The gate structure (50G), a drain structure (51D) of the ESD protection FET (12), and the anode structure (50A) are electrically connected to each other. A source structure (50S) of the power FET (11), a source structure (51S) of the ESD protection FET (12), and a terminal structure (50R) of the resistor element (14) are electrically connected to each other. A gate structure (51G) of the ESD protection FET (12), a cathode structure (50K) of the diode (13), and a terminal structure (51R) of the resistor element (14) are electrically connected to each other.

A semiconductor laser element capable of achieving a single or nearly single longitudinal mode of an oscillation wavelength is provided. A semiconductor laser element includes a nitride semiconductor laminate including a first end surface, a second end surface, and an optical waveguide. The nitride semiconductor laminate includes a first n-side nitride semiconductor layer, a second n-side nitride semiconductor layer, an active layer, and a p-side nitride semiconductor layer. The first n-side nitride semiconductor layer includes a diffraction grating region provided with a periodic structure in which a refractive index changes periodically along a resonance direction of the optical waveguide, and a non-diffraction grating region located between the diffraction grating region and the first end surface and not provided with the periodic structure.wherein the active layer includes an n-side well layer and an n-side barrier layer, wherein the second n-side nitride semiconductor layer is a nitride semiconductor layer containing In and Ga, and wherein a thickness of the second n-side nitride semiconductor layer is greater than a thickness of the n-side barrier layer.,

To suppress the decrease in reliability of connection in a drain electrode pad, a source electrode pad, and a gate electrode pad.SOLUTION: A nitride semiconductor device includes a nitride transistor, a first surface 21 where a drain pad 71, a source pad 72, and a gate pad 73 are provided, and an organic insulating layer 90 that covers the first surface 21. The organic insulating layer 90 includes a drain opening part 91, a source opening part 92, and a gate opening part 93. Each of the pads 71 to 73 includes a first metal layer 81 provided on the first surface 21, and a second metal layer 82 that is formed of a material that is oxidized less easily than the first metal layer 81 and that covers the first metal layer 81. A part of the gate pad 73 that is exposed by the gate opening part 93, a part of the source pad 72 that is exposed by the source opening part 92, and a part of the drain pad 71 that is exposed by the drain opening part 91 correspond to the second metal layer 82.SELECTED DRAWING: Figure 9

To reduce an on-resistance while maintaining a gate-drain breakdown voltage, in a bidirectional switch.SOLUTION: A nitride semiconductor device 10 includes a bidirectional switch 12. The bidirectional switch 12 includes a semiconductor substrate 40, a first nitride semiconductor layer 42, a second nitride semiconductor layer 44 having a bandgap larger than that of the first nitride semiconductor layer 42, a first drain electrode 28 and a second drain electrode 30 which contact the second nitride semiconductor layer 44, a third nitride semiconductor layer 50 containing acceptor-type impurities, and a gate electrode 26 located above the third nitride semiconductor layer 50. The third nitride semiconductor layer 50 includes a ridge part 54 contacting the gate electrode 26 and an extension part 56 thinner than the ridge part 54. The extension part 56 includes a first extension region 56A extending from the ridge part 54 toward the first drain electrode 28, and a second extension region 56b extending from the ridge part 54 toward the second drain electrode 30.SELECTED DRAWING: Figure 5

A power transistor comprising: a heterojunction formed between two III-nitride semiconductor layers, the heterojunction being configured to allow the formation of a two-dimensional carrier gas at the heterojunction and thereby define an active area of the power transistor; a drain terminal; a source terminal comprising a plurality of source contact regions spaced apart from the drain terminal in a first direction, wherein the source contact regions are spaced apart from each other in a second direction, perpendicular to the first direction; a gate terminal comprising a plurality of gate contact regions; a plurality of first doped III-nitride regions, each of the first doped III-nitride regions surrounding a respective source contact region; and a plurality of isolation regions located inside a boundary of the active area, each isolation region being situated between a pair of first doped III-nitride regions.

The present disclosure provides a nitride semiconductor transistor capable of improving current density. The nitride semiconductor transistor includes: a first channel layer having a first upper surface having nitrogen polarity; the ferroelectric nitride semiconductor layer is positioned on the first upper surface and is provided with a second upper surface with metal polarity; the second channel layer is positioned on the second upper surface and is provided with a third upper surface with metal polarity; and the first barrier layer is positioned on the third upper surface and is provided with a fourth upper surface with metal polarity.

An epitaxial wafer for a GaN HEMT having enhanced electrical insulation and a method of manufacturing the same are provided according to an embodiment of the present invention, the epitaxial wafer comprising: a growth substrate; a nucleation region, wherein the nucleation region is grown on the growth substrate; and a high resistance region having high resistance characteristics, the high resistance region including a high resistance cell region defined by a first region grown as a group III nitride semiconductor doped with carbon and a second region grown as a group III nitride semiconductor on the first region, the high-resistance region is arranged on the nucleation region; and an active region including a channel region grown on the high resistance region and a barrier region grown on the channel region.