10466 results about "Wafering" patented technology

An in situ method for forming a HfO₂ high-k dielectric layer in a batch wafer processing system. The method comprises first loading a plurality of wafers into a process chamber, and then pre-treating the plurality of wafers in the process chamber with a first oxidizer. After pre-treating the wafers, and without removing the wafers from the process chamber, the method then comprises depositing HfO₂ on the plurality of wafers by atomic layer deposition, which comprises a plurality of deposition cycles, each cycle comprising alternating exposure of the plurality of wafers in the process chamber to a second oxidizer and a hafnium precursor. The hafnium precursor is selected from hafnium tert-butoxide (HTB) or hafnium tetra-diethylamide (TDEAH).

A vacuum assembly used for warming processed substrates above the dew point to prevent unwanted moisture on the processed substrate surfaces as well as reducing negative impact on manufacturing throughput. The vacuum assembly includes a processing chamber, a substrate handling robot, and a heater which may be an optical heater. The processing chamber is configured to cryogenically process one or more substrates. The transfer chamber is connected to the processing chamber and houses the substrate handling robot. The substrate handling robot is configured to displace one or more substrates from the processing chamber to the transfer chamber. The heater is connected to the transfer chamber above the substrate handling robot such that the heater emits energy incident on the substrate when the substrate handling robot displaces the substrate in the transfer chamber.

An apparatus used for an epitaxial vapor growing arrangement and for detecting whether a wafer is properly seated within a susceptor contained therein. The apparatus includes a semiconductor laser element that generates a laser beam which irradiates the wafer's surface. The apparatus, further, includes a combination of a stop mechanism, a condenser lens and a photo diode, which detects the laser beam reflected from the wafer surface and an operation circuit, which determines the wafer's posture on the susceptor. During operation, the reflected laser beam focuses on a receiving surface of the photo diode through the condenser lens. The operation circuit then compares the output signal from the photo diode with a preset reference value for discriminating the slope of the wafer.

A technique for low-temperature ion implantation is disclosed. In one particular exemplary embodiment, the technique may be realized as an apparatus for low-temperature ion implantation. The apparatus may comprise a pre-chill station located in proximity to an end station in an ion implanter. The apparatus may also comprise a cooling mechanism within the pre-chill station. The apparatus may further comprise a loading assembly coupled to the pre-chill station and the end station. The apparatus may additionally comprise a controller in communication with the loading assembly and the cooling mechanism to coordinate loading a wafer into the pre-chill station, cooling the wafer down to a predetermined temperature range, and loading the cooled wafer into the end station where the cooled wafer undergoes an ion implantation process.

The robot arm of the present application is a robot arm that transports semiconductor wafers. The robot arm includes a hand, a lower arm link, and an upper arm link. The hand is connected to the lower arm link via a first joint. The upper arm link is connected to the lower arm link via a second joint. In the robot arm of the present application, the lower arm link is capable of being separated at a location between the first joint and the second joint.

Provided is a susceptor 13 for manufacturing an epitaxial wafer, comprising a mesh-like groove 13b on a mount face on which a silicon substrate W is to be mounted, wherein a coating H of silicon carbide is formed on the mount face, and the coating has a surface roughness of 1 μm or more in centerline average roughness Ra and a maximum height of a protrusion 13p generated in forming the coating H of 5 μm or less. Thus, defects such as warping and slip as well as adhesion of the silicon substrate to the susceptor are prevented.

An apparatus and method for reducing moisture within a wafer handling chamber is disclosed. The moisture reduction results in reduced oxidation of a wafer. The moisture reduction is made possible through use of valves and purging gas. Operation of the valves may result in improved localized purging.

A method and apparatus for growing low defect, optically transparent, colorless, crack-free, substantially flat, single crystal Group III nitride epitaxial layers with a thickness of at least 10 microns is provided. These layers can be grown on large area substrates comprised of Si, SiC, sapphire, GaN, AlN, GaAs, AlGaN and others. In one aspect, the crack-free Group III nitride layers are grown using a modified HVPE technique. If desired, the shape and the stress of Group III nitride layers can be controlled, thus allowing concave, convex and flat layers to be controllably grown. After the growth of the Group III nitride layer is complete, the substrate can be removed and the freestanding Group III nitride layer used as a seed for the growth of a boule of Group III nitride material. The boule can be sliced into individual wafers for use in the fabrication of a variety of semiconductor structures (e.g., HEMTs, LEDs, etc.).

A chamber passivation method particularly useful for hydrogen plasma cleaning of low-k dielectrics prior to coating a barrier layer into a via hole with hydrogen radicals are provided from a remote plasma source. For each wafer, the chamber is passivated with water vapor (or other gas even more chemabsorbed on plasma facing walls) passed through the remote plasma source prior to the ignition of the hydrogen plasma. The water vapor is absorbed on walls, such as alumina and quartz parts of the remote plasma source, and forms a protective mono-layer that endures sufficiently long to protect the walls during the generation of the hydrogen plasma. Thereby, the plasma facing walls, particularly of a dielectric such as alumina, are protected from etching.

A method for producing a direct bonded wafer comprising: forming a thermal oxide film or a CVD oxide film on a surface of at least one of a bond wafer and a base wafer, and bonding the wafer to the other wafer via the oxide film; subsequently thinning the bond wafer to prepare a bonded wafer; and thereafter conducting a process of annealing the bonded wafer under an atmosphere including any one of an inert gas, hydrogen and a mixed gas of an inert gas and hydrogen so that the oxide film between the bond wafer and the base wafer is removed to bond the bond wafer directly to the base wafer. Thereby, there is provided a method for producing a direct bonded wafer in which generation of voids is reduced, and a direct bonded wafer with a low void count.

One aspect of this disclosure relates to a method for forming a wafer with a strained semiconductor. In various embodiments of the method, a predetermined contour is formed in one of a semiconductor membrane and a substrate wafer. The semiconductor membrane is bonded to the substrate wafer and the predetermined contour is straightened to induce a predetermined strain in the semiconductor membrane. In various embodiments, a substrate wafer is flexed into a flexed position, a portion of the substrate wafer is bonded to a semiconductor layer when the substrate wafer is in the flexed position, and the substrate wafer is relaxed to induce a predetermined strain in the semiconductor layer. Other aspects and embodiments are provided herein.

A coating and a method to form the coating is proposed for a semiconductor film pre-clean and etch apparatus. The coating may be employed in environments where it is difficult to use a traditional coating or coating method. The coatings provide advantages including: an ability to effectively deliver hydrogen radicals and fluorine radicals to a wafer surface in one apparatus or individually in two apparatuses; a coverage of high aspect ratio features on critical components; an operability in high temperatures exceeding 150° C.; and a protection of a part with high aspect ratio features underneath the coating, thereby preventing metal and particles on a processed wafer.

The present disclosure discloses a MOSFET and a method for manufacturing the same, wherein the MOSFET comprises: an SOI wafer which comprises a semiconductor substrate, a buried insulating layer, and a semiconductor layer, the buried insulating layer being on the semiconductor substrate, and the semiconductor layer being on the buried insulating layer; a gate stack on the semiconductor layer; a source region and a drain region, which are in the semiconductor layer and on opposite sides of the gate stack; and a channel region, which is in the semiconductor layer and sandwiched by the source region and the drain region, wherein the MOSFET further comprises a back gate, the back gate being located in the semiconductor substrate and having a first doped region in a lower portion of the back gate and a second doped region in an upper portion of the back gate. The MOSFET can adjust the threshold voltage by changing the doping type and doping concentration of the anti-doped region.

In an atmosphere of processing gas, on a wafer W consisting mainly of silicon, through a planar-array antenna RLSA 60 having a plurality of slits, microwaves are irradiated to generate plasma containing oxygen, or nitrogen, or oxygen and nitrogen and to implement therewith on the surface of the wafer W direct oxidizing, nitriding, or oxy-nitriding to deposit an insulator film 2 of a thickness of 1 nm or less in terms of oxide film. A manufacturing method and apparatus of semiconductors that can successfully regulate film quality of the interface between a silicon substrate and a SiN film and can form SiN film of high quality in a short time can be obtained.

A wafer cap protects micro electromechanical system ("MEMS") structures during a dicing of a MEMS wafer to produce individual MEMS dies. A MEMS wafer is prepared having a plurality of MEMS structure sites thereon. Upon the MEMS wafer, the wafer cap is mounted to produce a laminated MEMS wafer. The wafer cap is recessed in areas corresponding to locations of the MEMS structure sites on the MEMS wafer. The capped MEMS wafer can be diced into a plurality of MEMS dies without causing damage to or contaminating the MEMS die.

A susceptor for holding semiconductor wafers in an MOCVD reactor during growth of epitaxial layers on the wafers is disclosed. The susceptor comprises a base structure made of a material having low thermal conductivity at high temperature, and has one or more plate holes to house heat transfer plugs. The plugs are made of a material with high thermal conductivity at high temperatures to transfer heat to the semiconductor wafers. A metalorganic organic chemical vapor deposition reactor is also disclosed utilizing a susceptor according to the present invention.

A susceptor for supporting a semiconductor wafer during deposition of a layer on a front side of the semiconductor wafer, the semiconductor wafer having a diameter D and, at its edge, a notch having a depth T, comprising:

• • a ring-shaped placement area having an internal diameter d for the placement of the semiconductor wafer in the edge region of a rear side of the semiconductor wafer, wherein, with the semiconductor wafer having been placed, the relationship (D−d)/2<T is satisfied; and
  • a protrusion of the area for the placement of semiconductor wafer in the region of the notch of the semiconductor wafer extending the placement area inward, and which completely underlays the notch of the semiconductor wafer.