5023 results about "Wafering" patented technology

Process condition management facilitates the combination of dry development and etching into a single process chamber; eliminating the necessity for a post-dry development bake step during semiconductor manufacturing. Methods and apparatuses for rapidly instituting a large drop in process chamber pressure allow thermal dry development and an O2 flash treatment or thermal dry development and plasma hardmask open operations to take place without wafer transfer.

A method for detecting printing defects in a photolithography mask that will print on a wafer when using the photolithography mask in a specific photolithography system to print semiconductor structures on the wafer, the method comprising: acquiring a first aerial image of the photolithography mask using a mask inspection system; generating a second aerial image of the photolithography mask by applying a machine learning model (26) to the first aerial image, wherein the machine learning model is trained to map a first aerial image acquired by a mask inspection system to a second aerial image that emulates the application of the specific photolithography system to the photolithography mask; and detecting printing defects in the photolithography mask by comparing the second aerial image to a reference image.

The invention provides a packaging structure and a packaging method. The package structure includes a substrate, a wafer disposed on the substrate and having a backside surface remote from the substrate, a heat sink disposed over the substrate and having a surface facing the backside surface, and a thermal interface material disposed between the wafer and the heat sink, wherein there is no organic adhesive between the wafer and the heat sink.

The technology described herein is directed towards a metasurface arranged with unit cells for narrowband sound absorption, in which the unit cells are based on Helmholtz resonators that can have their resonant frequencies adjusted via MEMS actuators. A sound absorbing unit-cell is designed and constructed based on a general resonance frequency, and includes a neck portion and air chamber dimensioned to resonate close to the desired resonance frequency and thereby inverse phase cancel corresponding narrowband frequencies of incoming sound waves. A bimorph MEMS actuator and / or moveable part in the resonators, controlled by a controller, facilitates changing of the airflow the unit cells to adjust the resonant frequencies thereof, to cancel acoustic waves of different frequencies corresponding to noise, which can change over time. The unit cells can be distributed as part of a metasurface, which can be positioned proximate to a noise source to phase cancel the noise.

An adjustment method of a laser processing apparatus includes a spatial light modulator adjustment step of adjusting a spatial light modulator into a state ready for splitting a laser beam emitted from a laser oscillator and applying a plurality of laser beams such that laser beams will have a desired positional relation, a processing mark formation step of operating the laser oscillator to apply the laser beams to a wafer such that a plurality of processing marks is formed, an imaging step of stopping the laser oscillator, and imaging the processing marks formed at the wafer, and an aberration correction step of correcting aberration of the condenser by comparing the desired positional relation and a positional relation among the imaged processing marks, and adjusting the spatial light modulator such that the positional relation among the processing marks conforms to the desired positional relation.

The invention provides a crystal growth device and a crystal growth method, and solves the technical problems of low wafer utilization rate, low crystal growth speed, low efficiency, poor uniformity and the like in the existing chip manufacturing process. According to the invention, a traditional cylindrical ampoule structure is abandoned, and the annular ampoule design is innovatively adopted, so that the crystal grows into an inner hollow cylinder shape which is highly matched with the specification of a target wafer; the heater is arranged on the inner side of the ampoule, a traditional outer side heating mode is replaced, and heat is intensively acted on crystals in cooperation with an adjusting center of a heat preservation material during crystal growth, so that heat loss is reduced; the periphery of the heater is made of heat insulation materials, heat radiation leakage is effectively restrained, meanwhile, the ampoule supporting structure is adjusted, and the whole device is simple, low in cost and light in weight.

The invention relates to the field of semiconductor processing, and discloses a semiconductor processing contour information extraction method, device and equipment and a storage medium, and the semiconductor processing contour information extraction method comprises the steps: obtaining a to-be-processed TEM graph and a design layout of a to-be-detected wafer; searching and determining a local layout corresponding to the TEM graph to be processed in the design layout; according to the contour distribution position in the local layout, determining a corresponding preliminary screening contour imaging area in the TEM graph to be processed; and contour edge detection is carried out according to the pixel value of each pixel point in the preliminary screening contour imaging area, and contour information of the processing contour of the to-be-detected wafer in the to-be-processed TEM graph is obtained. According to the method, the accuracy and reliability of contour information extraction in the TEM graph are realized by means of the design layout of the wafer to be tested, and a reliable data basis is provided for analysis of semiconductor process quality.

The invention discloses a crystal resonator sputter coating device and a preparation method of a crystal resonator, and belongs to the field of electronic components, the crystal resonator sputter coating device comprises a bottom plate, a lower electrode mask plate, a positioning plate, an upper electrode mask plate and a magnetic cover plate in sequence, the positioning plate is provided with a wafer positioning groove, a wafer is installed in the wafer positioning groove, and the magnetic cover plate is provided with a magnet. The upper electrode mask plate and the lower electrode mask plate are both provided with electrode holes, the thickness of the positioning plate is recorded as h < definite >, and one surface of at least one of the upper electrode mask plate and the lower electrode mask plate, which faces a wafer, is provided with a diffusion prevention bulge for preventing diffusion of electrode particles during film coating, and the thickness of the diffusion prevention bulge is recorded as h < definite >. The size of the dispersion preventing protrusion is matched with the size of the wafer positioning groove, the dispersion preventing protrusion is located in the wafer positioning groove during assembly, the thickness of the wafer is recorded as h wafer, and h wafer lt is smaller than or equal to 0.017 mm; and h, setting. The sputtering coating device solves the problem of electrode diffusion of the high-frequency crystal resonator in the existing sputtering coating device for the crystal resonator due to too small wafer thickness.

The invention relates to the technical field of semiconductor equipment, and provides vertical epitaxy equipment and an epitaxy method. The apparatus comprises: a vertical reaction chamber; the wafer boat is used for vertically loading a plurality of wafers at intervals; the driving device is used for driving the boat to enter / exit the vertical reaction cavity; the material supply assembly comprises a process supply pipeline and a switching unit; the process material source comprises a cleaning material source for removing an oxide layer on the surface of the wafer and an epitaxial material source for executing an epitaxial process; the process monitoring device is used for monitoring process end points of the cleaning process and the epitaxial process; and the control device is in communication connection with the switching unit and the process monitoring device, and controls the switching unit to switch the supply of the material source according to the monitoring result of the process monitoring device. According to the vertical epitaxial equipment, the epitaxial process can be continuously executed without transferring the wafers after the oxide removal process of the plurality of wafers is executed in situ in the equipment, so that the output rate and the yield of the equipment are improved, the cost is reduced, and the fragment and pollution risks are reduced.

The utility model discloses a wafer processing device, and belongs to the technical field of semiconductors. The wafer processing device comprises a carrying table, a shock insulation pad and an ultrasonic device, wherein the carrying table is used for carrying a crystal ingot with a modified layer; the ultrasonic device is arranged above the carrying table, the ultrasonic device can generate transverse vibration waves, and the transverse vibration waves are used for vibrating along the crystal ingot and enabling cracks of the modified layer to extend in the transverse direction; and the bottom of the carrying table is fixedly arranged on the shock insulation pad. According to the utility model, the cracks of the modified layer formed on the crystal ingot by the laser pulse grow and are connected along the transverse direction, the longitudinal growth of the cracks is avoided, the production efficiency of the modified layer is improved, the laser pulse does not need to be intensively emitted, and the wafer processing period is shortened.

The invention discloses a high-efficiency low-loss preparation method of a single crystal silicon carbide wafer. The method comprises the following steps: A, grinding the surface of a single crystal silicon carbide ingot; b, the ultrafast pulse laser is modulated into N light spots, the N light spots are focused in the crystal ingot and distributed in the axial direction of the crystal ingot according to preset depth positions, and all the light spots are parallel to the horizontal direction; all the light spots are scanned at the same time, the scanning surface formed by the same light spot covers the cross section of the single crystal silicon carbide crystal ingot in the horizontal direction, and N laser modified layers are formed after scanning; c, carrying out stress-induced separation on the single crystal silicon carbide crystal ingot in the step B; and D, grinding the cutting surface of the single crystal silicon carbide wafer. According to the high-efficiency and low-loss preparation method of the single-crystal silicon carbide wafer, the preparation efficiency of the silicon carbide wafer is improved, meanwhile, the material loss of the single-crystal silicon carbide ingot is reduced, and the yield of the single-crystal silicon carbide ingot is improved.

In a general aspect, modular quantum processor configurations and methods, including integrating superconducting circuit quantum processor chips with a module integration plate that includes inter-module connections to form modular quantum processors are presented. In some cases, a quantum processing unit includes quantum processor chips, a module integration plate, and one or more caps. Each quantum processor chip includes a plurality of qubit devices. The quantum processor chips are disposed between the module integration plate and the one or more caps. The module integration plate includes recesses that house respective subsets of the quantum processor chips; and inter-module coupler devices that provide communication between the subsets of quantum processor chips housed in distinct recesses. The one or more cap wafers each includes signal lines that provide communication between at least one of the quantum processor chips and a control system.

An electrostatic chuck (ESC) pedestal heater that includes a pedestal body and a surface on the pedestal body for receiving a substrate such as a high bow wafer. An electrode is embedded in the pedestal body to selectively generate an electrostatic force. The ESC pedestal heater includes a substrate contact surface that is raised to a height above the surface on the pedestal body and includes an inner seal band, an intermediate seal band, and an outer seal band extending. In the substrate contact surface, main spokes are provided that extend outward from the inner seal band to the outer seal band, and ancillary spokes may be provided between the main spokes in the region between the intermediate and outer seal bands. Additionally, contact areas or dots are provided in the substrate contact surface in the spaces between the bands and spokes.

Provided is a pattern inspection system, including a scanning electron microscope (SEM) including an electron gun configured to generate a first electron beam and emit the generated first electron beam toward a first wafer, a detector configured to detect electrons emitted from the first wafer based on the first electron beam emitted toward the first wafer, and at least one processor configured to generate a first SEM image including a plurality of pixels based on the detected electrons, and determine, based on a period of a pattern extracted from the first SEM image, a pixel size of a second SEM image to be generated by the SEM with respect to a second wafer.

Embodiments of the present disclosure provide a semiconductor device structure having vertically stacked complementary field effect transistors (CFETs). The CFETs are formed by bonding two substrates having semiconductor stacks formed thereon. A bonding structure is formed between the semiconductor stacks using wafer bonding technology. Embodiments of the resent disclosure enable the flexibility of choosing different N / P channel properties, provide a simple way to form the N / P channel isolation structure, and reduce potential leakage path and defects in stacked CFETs.

A system for detecting the presence of a wafer on a wafer handling robot. The system includes a robot having an end effector with a ledge portion having an opening; a vacuum pump; a conduit fluidly coupling the vacuum pump to the opening in the ledge portion; a pressure sensor located along the conduit to determine whether a measured pressure is within a target pressure range; and a wafer configured to be supported by the at least one end effector and spaced apart from the ledge portion by an air gap. When the wafer is supported by the at least one end effector in a proper position, the measured pressure is within the target pressure range. When the wafer is not supported by the wafer support structure or is supported by the wafer support structure in an improper position, the measured pressure is outside of the target pressure range.

The invention discloses a wafer automatic orientation stacking device based on visual identification, and belongs to the technical field of component manufacturing automation. The device comprises a control unit, a visual unit and a motion unit. The moving unit comprises a three-dimensional moving platform, a feeding disc, a receiving disc, a suction nozzle and a rotating motor; the visual unit comprises a light source and a camera. The camera is used for collecting images of the wafers in the feeding disc, the control unit is used for processing the images, the position and the direction of each wafer are accurately recognized, then the movement unit and the rotating motor are driven, the suction nozzle picks up the wafers and carries out rotation correction, and finally directional stacking is carried out on the receiving disc at the height calculated in a self-adaptive mode. The problems that manual stacking is low in efficiency and poor in consistency and existing equipment cannot carry out accurate directional stacking on wafers with similar lengths and widths are solved, and full automation, high precision and high stability of wafer stacking are achieved.

The utility model relates to the technical field of semiconductor wafers, and discloses a semiconductor wafer thickness measuring device, which comprises a moving assembly and a compression measuring assembly, the moving assembly is arranged below the compression measuring assembly, the moving assembly comprises a fixed bottom plate, the upper end of the fixed bottom plate is connected with a moving motor, and the moving motor is connected with the compression measuring assembly. The output end of the moving motor is fixedly connected with a threaded rod, the threaded rod is connected with a threaded block, the upper end of the threaded block is connected with a sliding block, and the sliding block is connected with a sliding groove. According to the utility model, the thickness information of a plurality of positions can be rapidly acquired, the flexibility during measurement is improved, the measurement work of the thickness of the whole wafer can be rapidly completed, the measurement efficiency is improved, different areas of the semiconductor wafer can be measured, the distribution condition of the thickness of the semiconductor wafer can be completely mastered, and the measurement accuracy is improved. And omission of areas possibly having abnormal thickness is avoided, so that the measurement is more comprehensive.

The invention discloses an industrial visual inspection method based on edge light scanning, which comprises the following steps of: initializing projector parameter setting, adjusting shooting frequency and exposure time of an industrial camera, acquiring defect images and forming an image sequence according to the size and the material of a detected piece and an expected defect type to be detected and based on an edge light scanning method; carrying out fusion operation on the image sequence, enhancing defect signals of the images through a weighted stacking algorithm by utilizing high-contrast characteristics of defect areas in multiple frames of images, and carrying out defect positioning and classification on the enhanced images by adopting an image segmentation technology, so as to realize visual detection on defects of the detected piece; by optimizing the design of an optical imaging system, edge light scanning of the quartz wafer is realized, defects are highlighted, surface defects can be quickly and accurately identified, the detection efficiency is greatly improved, defect characteristics are directly enhanced in an image acquisition stage, and quick and accurate defect detection is realized in combination with a sequence image analysis technology.

Techniques for dielectric isolation in bulk nanosheet devices are provided. In one aspect, a method of forming a nanosheet device structure with dielectric isolation includes the steps of: optionally implanting at least one dopant into a top portion of a bulk semiconductor wafer, wherein the at least one dopant is configured to increase an oxidation rate of the top portion of the bulk semiconductor wafer; forming a plurality of nanosheets as a stack on the bulk semiconductor wafer; patterning the nanosheets to form one or more nanowire stacks and one or more trenches between the nanowire stacks; forming spacers covering sidewalls of the nanowire stacks; and oxidizing the top portion of the bulk semiconductor wafer through the trenches, wherein the oxidizing step forms a dielectric isolation region in the top portion of the bulk semiconductor wafer. A nanowire FET and method for formation thereof are also provided.

A wafer suspension fork has a body and a cover. The body has a connection portion having multiple inlets and two arms being symmetrical in shape and protruding from the connection portion. Each arm has a holding surface, a flowing surface, multiple inner and outer inclined holes formed in the holding surface arranged along a protruding direction, an inner flowing channel formed in the flowing surface and communicating with the inner inclined holes and the inlets, and an outer flowing channel formed in the flowing surface and communicating with the outer inclined holes and the inlets. The cover is fixed to a bottom surface of the body. A wafer is able to be suspended and held above the two arms by adjusting pressure of gas flowing out from the inner and outer inclined holes and is able to be moved free from being scratched.

The invention relates to the technical field of semiconductor processing technologies, and discloses an optical proximity correction method, device and equipment of a mask pattern and a storage medium, and the optical proximity correction method of the mask pattern comprises the steps: carrying out the morphology prediction of a polished surface of a to-be-processed wafer, and obtaining the morphology information of the polished surface; correcting focal plane parameters in a simulation optical model according to the shape information of the polished surface; and performing optical proximity correction on the initial mask pattern by using the corrected simulation optical model to obtain a corrected mask pattern. According to the method, the shape information of the polished surface of the to-be-processed wafer is predicted, and the focal plane parameters in the simulation optical model are corrected on the basis of the shape information, so that the accuracy and reliability of optical proximity correction of the initial mask pattern based on the simulation optical model are ensured; and the processing precision of semiconductor photoetching based on the mask pattern can be improved.

Provided is a GaAs wafer that can suitably be used to produce LiDAR sensors in particular and a method of producing a GaAs ingot that can be used to obtain such a GaAs wafer. The GaAs wafer has a silicon concentration of 5.0×1017 cm−3 or more and less than 3.5×1018 cm−3, an indium concentration of 3.0×1017 cm−3 or more and less than 3.0×1019 cm−3, and a boron concentration of 1.0×1018 cm−3 or more. The average dislocation density of the GaAs wafer is 1500 / cm2 or less.

The invention relates to the technical field of semiconductor manufacturing, in particular to a photo-assisted catalytic diamond chemical mechanical polishing device, which solves the problems of low photocatalytic efficiency and low processing efficiency in the prior art, and comprises a bracket, a rotating platform and a working turntable for loading diamond wafers are arranged on the bracket, and an annular baffle plate is arranged on the outer side of the rotating platform. The rotating platform and the annular baffle are matched to form a containing groove, an annular polishing pad and a middle ultraviolet light source are arranged on the rotating platform, the middle ultraviolet light source is located in the center of the annular polishing pad, a side edge ultraviolet light source is arranged on the inner side of the annular baffle, and the annular polishing pad and the middle ultraviolet light source both correspond to the working rotary table in position; the containing groove is filled with polishing liquid, and the annular polishing pad, the side edge ultraviolet light sources and the middle ultraviolet light source are all immersed in the polishing liquid. The device has the beneficial effects that the design that the middle ultraviolet light source and the side ultraviolet light sources cooperatively irradiate is adopted, and the promoting effect of photocatalysis on the chemical reaction on the surface of the diamond is enhanced.

A wafer processing method and system are provided. The wafer processing system includes an isopropyl alcohol (IPA) evaporation system, an IPA condensation system, and a process chamber. The IPA evaporation system evaporates liquid IPA into IPA vapor. The IPA condensation system condenses a portion of the IPA vapor into distilled high purity liquid IPA. The process chamber rinses a semiconductor wafer in the process chamber using the distilled high purity liquid IPA, and displaces the distilled high purity liquid IPA using a remaining portion of the IPA vapor to dry the semiconductor wafer.

The invention relates to the field of silicon carbide wafer preparation, in particular to a semi-insulating silicon carbide wafer annealing device and method, the annealing device comprises a crucible cover and a graphite crucible which are detachably connected, an annealing chamber is arranged in the graphite crucible, the annealing chamber comprises a wafer supporting area and a powder area, and the powder area is arranged in the crucible cover. The gas pressure control assembly is used for controlling gas components and pressure intensity in the annealing chamber; the heating device is used for heating the annealing chamber in a partitioned manner; and the heat preservation system is arranged outside the crucible cover and the graphite crucible in a sleeving manner. By means of the annealing device, the problems of silicon carbide wafer intrinsic point defect screening and concentration control can be effectively solved, the Fermi energy level is controlled at the EH6 / 7 energy level position, and the silicon carbide wafer obtained through annealing finally achieves control over the electrical resistivity larger than 1E12 ohm cm.

Provided are methods and structures for keeping the integrity of layers deposited on a semiconductor wafer through a thermal cycle. Deposition of a second backside layer, or a cap, with an internal stress opposite to a first backside layer may be used to reduce bow shift of a wafer during a thermal cycle. The first backside layer may have a tensile internal stress or a compressive internal stress. The second backside layer has an internal stress opposite to the first backside layer. Each of the backside layers may be deposited by a backside deposition apparatus.

The invention discloses a non-contact measurement system and method for the longitudinal distance between objects, and the method comprises the steps: measuring the position distance between an object and an adjacent object in a size-limited space: placing a light source on the surface of a workpiece, projecting an electromagnetic beam with a set divergence angle to a reference object, and forming an amplified light spot; image information, especially light intensity information, of the light spot and a part of reference object where the light spot is located at the projection position is received through a light receiver; and then the processor processes the image information to obtain geometric data of the light spots, including the positions of the light spots on the reference object, the lengths of the obtained light spots or the distances between different light spots, namely the projection lengths, the projection height from the light source to the reference object is calculated in combination with the divergence angle, and the longitudinal distance between the workpiece and the reference object is obtained in combination with the height of the light source. As long as the size of the light source is small enough and the light source can be placed into the chamber for processing the wafer, the longitudinal distance between the wafer and the top of the chamber can be accurately measured at any time, and the measurement accuracy related to wafer manufacturing is greatly guaranteed.

A system for sequencing a polynucleotide strand including a device with a layer stack on a silicon wafer. The layer stack may include a first electrode and a second electrode separated by a dielectric insulating layer and a nanohole drilled through the layer stack so that the first and second electrodes are rotationally arranged around the nanohole. A polynucleotide strand with at least one nucleotide and at least one electroactive label may be pulled through the nanohole. The system may additionally include a controller that may apply an electrical signal to the first and second electrodes, measure a current (I) as a function of an applied potential (V) when an electroactive label is guided through the nanohole of the device, and adjust an electrical voltage to pull the polynucleotide strand through the nanohole at a predetermined speed.

Disclosed is semiconductor manufacturing equipment. The semiconductor manufacturing equipment includes: a remote plasma source used configured to generate plasma; a reaction chamber coupled to the remote plasma source, and defining a space in which a wafer is processed; an exhaust pipeline coupled to the reaction chamber through an exhaust port, and configured to discharge by-products generated in the reaction chamber; a first pipeline coupled to the reaction chamber; a second pipeline coupled to the exhaust pipeline through the exhaust port; and an analyzer configured to analyze a first gas mixture received from the reaction chamber through the first pipeline.