8180 results about "Wafering" patented technology

Energy is locally supplied to a cutting surface that is formed in an outer circumferential region of a wafer in a trimming step, before a grinding step of grinding the wafer. This can remove or repair at least part of a damage layer formed in the outer circumferential region of the wafer due to the trimming step. As a result, breakage of the wafer that originates from the outer circumferential region in the grinding of the wafer which has been subjected to the edge trimming and generation of dust in a step after this grinding can be suppressed.

The invention belongs to the technical field of crystal processing, and relates to a method for obtaining a single crystal diamond (111) surface wafer by using double-pulse-width laser. Femtosecond laser and picosecond laser are adopted for machining and stripping the blocky single crystal diamond to obtain a first crystal face (111), then femtosecond laser and picosecond laser are continuously adopted for machining and stripping the remaining blocky single crystal diamond, and the blocky single crystal diamond is obtained; the process for obtaining the crystal face (111) comprises the following steps of: scanning femtosecond laser on the crystal face (111) to process a plurality of graphitization modification lines which are full of the crystal face (111) and are parallel to each other, wherein the graphitization modification lines are parallel to the crystal orientation of a diagonal line [110] of the crystal face (001); carrying out scanning processing along the graphitization modification line by utilizing picosecond laser, so as to form a leap crack on the basis of the graphitization modification line of the crystal face (111); and then stripping is carried out. By means of the method, the wafer with the complete (111) face can be obtained through cutting in the ultra-thick (001) CVD monocrystal diamond.

In one aspect, a highly scalable diffusion-couple apparatus includes a transfer chamber configured to load a wafer into a process chamber. The process chamber is configured to receive the wafer substrate from the transfer chamber. The process chamber comprises a chamber for growth of a diffusion material on the wafer. A heatable bottom disk includes a first heating mechanism. The heatable bottom disk is fixed and heatable to a specified temperature. The wafer is placed on the heatable bottom disk. A heatable top disk comprising a second heating mechanism. The heatable top disk is configured to move up and down along an x axis and an x prime axis to apply a mechanical pressure to the wafer on the heatable bottom disk. While the heatable top disk applies the mechanical pressure, a chamber pressure is maintained at a specified low value. The first heating mechanism and the second heating mechanism can be independently tuned to any value in the working range.

The invention relates to the technical field of image analysis, in particular to a polishing effect detection method for an indium phosphide wafer, which comprises the following steps: evaluating the polishing quality through model comparison of three-dimensional images before and after polishing, analyzing the polishing retention difficulty according to the internal defect data and defect aggregation degree of the crystal before polishing, and determining the polishing retention difficulty of the indium phosphide wafer. And performing polishing damage analysis on the basis of the obtained internal defect data of the wafer before and after polishing, and analyzing the polishing effect according to the obtained polishing quality evaluation result, polishing maintenance difficulty analysis result and polishing damage, so that the polishing quality of the polishing equipment in the polishing process is accurately evaluated on the basis of model comparison of the three-dimensional images before and after polishing; and meanwhile, accurate analysis on damage and maintenance difficulty in the polishing process is considered, so that the polishing effect is comprehensively evaluated, and the accuracy and rationality of evaluation on the polishing effect are improved.

The invention relates to an aluminum oxide CMP polishing solution for rough polishing of silicon carbide wafers and a polishing method of the aluminum oxide CMP polishing solution, and the aluminum oxide CMP polishing solution comprises the following components in percentage by weight: 2-10wt% of nano aluminum oxide abrasive; 0.2 to 2 wt.% of a dispersant; 0.001 to 0.01 wt% of a pH regulator; the concentration of the oxidizing agent is 1-5wt.%. By adopting the compound oxidant, potassium permanganate is utilized to oxidize a reduction product manganese dioxide on the surface of the silicon carbide wafer to activate potassium persulfate, so that a large amount of sulfate free radicals are generated in the polishing solution, the oxidability of the sulfate free radicals is extremely high, the polishing solution can be promoted to generate chain oxidation reaction, and the surface of the silicon carbide wafer is further oxidized; and an oxide layer with low hardness is formed on the surface of the silicon carbide and is finally removed under the mechanical action of the aluminum oxide abrasive, so that the ultra-smooth and damage-free surface of the silicon carbide wafer is formed. The surface roughness of the obtained optimal silicon carbide wafer is 0.125 nm, and the material removal rate is 3.5 [mu] m / h. Compared with an existing aluminum oxide polishing solution, the polishing solution has the advantage that the surface quality and the polishing efficiency of the silicon carbide wafer are remarkably improved.

1. Name of the product of this design: Information display portion of an electronic device with a graphical user interface for displaying information. 2. Purpose of this design product: This product is an interface displayed in virtual reality, extended reality or composite reality, etc., and is used to display information such as guidelines or parameters related to the wafer cleaning device. The section you want to protect is used to display information such as guides or parameters. 3. The key points of the design of this product are the contents shown by the solid line. 4. The picture or photo that best illustrates the key points of the design: main view. 5. The rest of the parts are of conventional design, omitting the rear view, left view, right view, top view and bottom view. 6. Purpose of the graphical user interface: This interface is an interface displayed in virtual reality, extended reality or composite reality, etc., and through the user's click operation, it can display the interface of information such as instructions or parameters related to the wafer cleaning device. 7. Other circumstances that require explanation: The portion indicated by the solid line is the portion that you wish to protect.

Process condition management facilitates the combination of dry development and etching into a single process chamber; eliminating the necessity for a post-dry development bake step during semiconductor manufacturing. Methods and apparatuses for rapidly instituting a large drop in process chamber pressure allow thermal dry development and an O2 flash treatment or thermal dry development and plasma hardmask open operations to take place without wafer transfer.

A method for detecting printing defects in a photolithography mask that will print on a wafer when using the photolithography mask in a specific photolithography system to print semiconductor structures on the wafer, the method comprising: acquiring a first aerial image of the photolithography mask using a mask inspection system; generating a second aerial image of the photolithography mask by applying a machine learning model (26) to the first aerial image, wherein the machine learning model is trained to map a first aerial image acquired by a mask inspection system to a second aerial image that emulates the application of the specific photolithography system to the photolithography mask; and detecting printing defects in the photolithography mask by comparing the second aerial image to a reference image.

The invention belongs to the technical field of laser processing, and provides a quartz crystal etching solution which comprises the following components in volume concentration: 10-30% of hydrofluoric acid, 1-5% of sulfuric acid, 0.1-0.3% of surfactant and the balance of water. By optimizing the proportion, the manufacturing precision and the production and manufacturing efficiency of the tuning fork wafer are improved. And the stable etching rate and the optimal etching surface are obtained, and meanwhile, the cost is saved for process replacement. The invention further provides a method for cutting the tuning fork of the quartz crystal through the laser. The method comprises the steps that S1, the cutting contour line of the tuning fork is preset on the quartz crystal; s2, performing laser cutting on the quartz crystal based on a preset cutting contour line, and forming a tuning fork contour on the quartz crystal; and S3, integrally soaking the quartz crystal in the quartz crystal etching solution, and separating out the tuning fork. The machining process of the quartz crystal tuning fork is simplified, the cutting quality is optimized, the method is suitable for the large-piece manufacturing process, and the cutting efficiency and the yield are greatly improved.

The invention relates to a hydrogen storage pellet enabling the production of compact, modular, safe and energy-efficient hydrogen reservoirs. The pellet according to the invention comprises a peripheral ring (4) having an outer diameter of expanded natural graphite (ENG) of a determined height, surrounding a wafer of a metal hydride (5) in the form of compacted powder.

The invention relates to the technical field of wafer processing, in particular to a wafer surface grinding device and a grinding method thereof, and solves the problem that high grinding precision and high grinding efficiency cannot be both considered during wafer surface grinding. The polishing device comprises a workbench, a rotary table, a plurality of polishing pieces, an adjusting assembly, a visual identification piece and a control piece, and the adjusting assembly is configured to enable at least one polishing piece to be close to or far away from a surface to be polished in the vertical direction and enable at least one polishing piece to move in the horizontal direction to be close to or far away from an original point; the control part determines grinding data according to the recognition image and controls the adjusting assembly to drive at least one grinding part to move according to the grinding data, so that one protrusion in the preset area is ground by one grinding part under the condition that the rotary table is static, or at least one protrusion is ground by multiple grinding parts at the same time under the condition that the rotary table rotates. According to the wafer surface grinding device and the grinding method thereof provided by the invention, the grinding precision and the grinding efficiency of the wafer surface can be improved.

The utility model relates to the technical field of acceleration sensors, in particular to a piezoelectric acceleration sensor, which comprises a shell, a mounting cavity is arranged in the shell, a shielding shell is fixedly connected in the mounting cavity, a crystal base is fixedly connected at the bottom end in the shielding shell, a PCB (printed circuit board) is arranged at the upper part in the shielding shell, and the crystal base is fixedly connected with the crystal base. An external force is applied along the polarization direction of the ceramic wafer to deform the ceramic wafer, the inside of the ceramic wafer is polarized, charges with opposite polarities appear on the two stressed end faces, and the ceramic wafer is recovered to an initial state if the external force is removed, so that mechanical energy is converted into electric energy by utilizing the direct piezoelectric effect of the ceramic wafer, and then the electric energy is subjected to signal processing; the sensor outputs 100mv / g alternating current voltage, so that vibration acceleration signals are measured, triangular shearing is adopted by a measuring element, a two-core shielding cable is adopted by a cable, and the sensor is small in size, light in weight and high in applicability.

To provide a ceramic board which has good heat dissipation, and in which an integration density is high.SOLUTION: According to an embodiment, the present invention discloses a manufacturing method of an ultrathin high-density multilayer interconnection ceramic board, containing steps of: preparing a ceramic wafer, performing a laser punching to the ceramic wafer, and forming a via hole; performing a vacuum magnetron sputtering to the ceramic wafer, and forming a seed titan layer and a copper layer onto a front surface of the ceramic wafer and on a wall of the via hole by the sputtering; manufacturing a ceramic double-layer core plate; manufacturing a multilayer substrate; manufacturing a vertical interconnection multilayer substrate; and manufacturing a high-end multilayer HDI ceramic board. The multilayer ceramic plate manufactured in the above mentioned processing can be easily processed as compared with LTCC and HTCC, and an energy consumption amount for the processing is deteriorated. A heat conductivity of a finished product is improved. A wiring is more accurate; a conductive resistance is low; and a signal transmission loss is low.SELECTED DRAWING: Figure 1

The invention belongs to the technical field of chips, and discloses a vehicle gauge-level SMD chip crystal and a processing method thereof, and the method comprises the steps: forming a gradient doped region on the surface layer of a quartz wafer through an ion implantation technology, and carrying out the recognition of the surface defects of the wafer and the etching of an anchor point groove based on a visual detection system; the etched doped quartz wafer is subjected to micro-electro-mechanical processing, a double-cantilever supporting structure is formed, a three-dimensional electromagnetic shielding layer is constructed on the surface of the wafer subjected to cantilever processing, a ceramic substrate and a metal conducting layer are alternately deposited through an additive manufacturing process, a polyimide-silicon dioxide colloid material is provided, and the three-dimensional electromagnetic shielding layer is formed; gradient distribution of an adhesive layer is realized through a micro-droplet jetting technology, a polyimide-silicon dioxide composite stress buffer layer is coated on a ceramic substrate, alignment and patch packaging are carried out on a processed crystal and a substrate, and through material modification and process collaborative optimization, the method is suitable for application in a high-temperature environment; the reliability problem in the extreme environment of the vehicle gauge is solved, and meanwhile the yield is improved.

A placement stage includes: a wafer placement part having a placement surface and a first through hole; a base bonded to a rear surface of the wafer placement part by a first adhesive layer, and including a second through hole formed in the base, the second through hole communicating with the first through hole; a sleeve installed in the second through hole to be detachable from the base; and the sealing member installed between the rear surface and the sleeve to be spaced apart from the first adhesive layer so as to seal the first adhesive layer. A convex portion is formed to extend on an outer circumference or an inner circumference of a tip end of the sleeve, and the sealing member is pressed against a tip end surface of the sleeve to expand and contract.

The invention provides a packaging structure and a packaging method. The package structure includes a substrate, a wafer disposed on the substrate and having a backside surface remote from the substrate, a heat sink disposed over the substrate and having a surface facing the backside surface, and a thermal interface material disposed between the wafer and the heat sink, wherein there is no organic adhesive between the wafer and the heat sink.

The present disclosure provides a method, apparatus, medium and device for calculating the wafer layout of a wafer, belonging to the field of semiconductor technology. The method includes: based on the distribution array of each wafer, taking any wafer as a reference wafer, moving the wafer center in a preset area according to a first step length to determine the first coverage area after each movement, and determining the feasible area of the reference wafer according to the number of complete wafers in the coverage area; moving the wafer center in the feasible area according to a second step length to determine the second coverage area after each movement, and determining the maximum number of complete wafers in the coverage area; placing the reference wafer at different positions in the single-exposure area in turn according to the wafer position distribution pattern of the single-exposure area of the lithography machine to determine the minimum number of exposures for exposing all wafers; determining the positions of each wafer according to the maximum number and the minimum number of exposures to generate a wafer layout. The present disclosure can improve the accuracy and efficiency of calculating the maximum number of wafers.

The technology described herein is directed towards a metasurface arranged with unit cells for narrowband sound absorption, in which the unit cells are based on Helmholtz resonators that can have their resonant frequencies adjusted via MEMS actuators. A sound absorbing unit-cell is designed and constructed based on a general resonance frequency, and includes a neck portion and air chamber dimensioned to resonate close to the desired resonance frequency and thereby inverse phase cancel corresponding narrowband frequencies of incoming sound waves. A bimorph MEMS actuator and / or moveable part in the resonators, controlled by a controller, facilitates changing of the airflow the unit cells to adjust the resonant frequencies thereof, to cancel acoustic waves of different frequencies corresponding to noise, which can change over time. The unit cells can be distributed as part of a metasurface, which can be positioned proximate to a noise source to phase cancel the noise.

An adjustment method of a laser processing apparatus includes a spatial light modulator adjustment step of adjusting a spatial light modulator into a state ready for splitting a laser beam emitted from a laser oscillator and applying a plurality of laser beams such that laser beams will have a desired positional relation, a processing mark formation step of operating the laser oscillator to apply the laser beams to a wafer such that a plurality of processing marks is formed, an imaging step of stopping the laser oscillator, and imaging the processing marks formed at the wafer, and an aberration correction step of correcting aberration of the condenser by comparing the desired positional relation and a positional relation among the imaged processing marks, and adjusting the spatial light modulator such that the positional relation among the processing marks conforms to the desired positional relation.

The invention provides a subsurface damage depth prediction and control method for ultra-precision grinding of a semiconductor wafer. The method comprises the following steps that the subsurface damage depth difference of ductile grinding and brittle grinding is analyzed; calculating the critical cutting depth of ductile-brittle transition; establishing the relationship between the subsurface damage depth and the normal force of a single abrasive particle; specifically, on the basis of the relation between the normal force of a single abrasive particle and the plastic radius of a plastic deformation area in ductile grinding and the median crack depth in brittle grinding, the relation between the subsurface damage depth of wafer grinding and the normal force of the single abrasive particle is obtained in combination with ductile-brittle transformation judgment conditions; establishing the relationship between the normal force of a single abrasive particle and the cutting depth of the abrasive particle; establishing the relationship between the abrasive particle cutting depth and the grinding process parameters; and establishing the relationship between the subsurface damage depth and the grinding process parameters. According to the method, the grinding process parameters are reversely solved based on the subsurface damage depth model, the grinding process can be formulated according to specific damage indexes, and the machining efficiency is improved on the basis of meeting the machining requirements.

The invention relates to the technical field of light emitting of LED lamp beads, and discloses a uniform control method and device for the light emitting color of the LED lamp beads and the LED lamp beads, and the method comprises the steps that LED wafers are placed in a triangular annular mode, and the LED lamp beads are prepared through centrifugal treatment of double-layer packaging glue; acquiring an initial optical parameter matrix after applying rated working parameters, and establishing a standard data model; monitoring the LED lamp beads in real time to obtain a monitoring data set; calculating a multi-dimensional deviation vector by using a spectral similarity algorithm, an Euclidean distance algorithm and a ratio algorithm; a comprehensive deviation evaluation value is obtained through weighted summation; and generating a correction amount based on the evaluation value to carry out closed-loop control until a control termination condition is reached. According to the method, accurate control over the light emitting colors of the LED lamp beads is achieved, and the uniformity and stability of the light emitting colors of the LED lamp beads are improved.

Systems and methods are described for collecting and combining multiple scan samples from a surface of a semiconducting wafer. A system embodiment includes, but is not limited to, a scan nozzle configured to introduce a first scan solution to a surface of a semiconducting wafer to remove impurities from the surface to provide a first scan sample and retrieve the first scan sample, the scan nozzle further configured to introduce a second scan solution to the surface of the semiconducting wafer to remove residual impurities from the surface to provide a second scan sample and retrieve the second scan sample; and a collection vessel in fluid communication with the scan nozzle, the collection vessel configured to receive each of the first scan sample and the second scan sample from the nozzle and to mix the first scan sample with the second scan sample to provide a combined scan sample.

The utility model relates to an automatic wafer unloading device suitable for porcelain dishes, which comprises a transmission track, a wafer unloading mechanism, a wafer unloading mechanism and a wafer unloading mechanism, and is characterized in that a transmission surface for transmitting wafers one by one from top to bottom is formed on the transmission track; the positioning unit comprises a positioning platform and a first driving part, the porcelain plate is flatly placed on the positioning platform, and the first driving part is used for driving the positioning platform and driving the wafers to be sequentially aligned with the feeding end of the transmission track; a wafer receiving groove connected with the discharging end of the transmission track is formed in the receiving unit; and a blade unit. According to the utility model, on one hand, on the basis of the state that the wafers are adhered to the porcelain plate, lossless stripping and unloading of the wafers are carried out through cooperation of the positioning platform, the scraper knife and the transmission track, so that the wafers are effectively prevented from deviating, accurate butt joint of the wafers and the transmission track is ensured, and the unloading success rate is greatly improved; on the other hand, the structure is simple and reliable, and implementation cost is low.

The invention discloses a recovery device and reutilization method for silicon in a waste photovoltaic module, the recovery device comprises an equipment base, an acid pickling recovery pool, a circulating liquid washing mechanism and a clamping seat, the acid pickling recovery pool is fixedly installed on the surface of the equipment base, a high-pressure air pump is fixedly installed on one side of the equipment base, and the high-pressure air pump is fixedly installed on the other side of the equipment base; an aerator communicated with the output end of the high-pressure air pump is arranged on the bottom face of the acid pickling recycling pool, a liquid injection end pipe and a circulation pipeline are arranged on the top face and one side of the acid pickling recycling pool respectively, and the circulation liquid washing mechanism is fixedly installed on the inner side of the acid pickling recycling pool. According to the invention, the automatic ultrasonic pickling structure is arranged, the pickling recovery pool is used for filling the chemical solvent, the cavitation effect is formed on the surface of the silicon wafer carried by the pickling solution through ultrasonic oscillation in solvent pickling, the silicon wafer and EVA are separated, more than 99% of polymer is removed from the PV module, and the processed silicon wafer is good in integrity; the silicon wafer is almost free of fracture damage, and the recovery value is improved.

The present invention relates to a vertically-laminated microdisplay panel requiring no color filter, the panel comprising: a back wafer, the top surface of which has multiple CMOS electrode pads aligned thereon; multiple LED laminates, each of which includes multiple light emitting units and multiple bonding layers vertically laminated on the back wafer, and which are aligned on the multiple CMOS electrode pads, respectively; and a common electrode formed on the multiple LED laminates, wherein each of the multiple LED laminates emits only a particular color by having a short passage formed through at least one light emitting unit among the multiple light emitting units to bypass current so as to prevent the current from being injected into the light emitting unit.

The invention provides a crystal growth device and a crystal growth method, and solves the technical problems of low wafer utilization rate, low crystal growth speed, low efficiency, poor uniformity and the like in the existing chip manufacturing process. According to the invention, a traditional cylindrical ampoule structure is abandoned, and the annular ampoule design is innovatively adopted, so that the crystal grows into an inner hollow cylinder shape which is highly matched with the specification of a target wafer; the heater is arranged on the inner side of the ampoule, a traditional outer side heating mode is replaced, and heat is intensively acted on crystals in cooperation with an adjusting center of a heat preservation material during crystal growth, so that heat loss is reduced; the periphery of the heater is made of heat insulation materials, heat radiation leakage is effectively restrained, meanwhile, the ampoule supporting structure is adjusted, and the whole device is simple, low in cost and light in weight.

The invention discloses a crystal ingot laser modification process and a laser processing device, and belongs to the technical field of semiconductors. The crystal ingot laser modification technology comprises the following steps that light gathering points of at least two modification laser beams with permeable wavelengths are positioned at the position with the preset depth from the first face of a crystal ingot, each light gathering point forms a corresponding modification part, at least two modification parts are arranged at intervals along the C face, cracks spread along the C face from the modification parts, and the cracks are formed in the first face of the crystal ingot. The cracks formed by the adjacent modified parts are mutually connected to form a group of cracks; a cutting laser beam is adopted for cutting between two adjacent groups of cracks to form a cutting part, and the two ends of the cutting part are connected with the two groups of cracks respectively. According to the invention, the production efficiency is improved by increasing the width of the crack, stripping by a pressing mechanism is not needed, and the yield of the wafer is improved.

The invention relates to the field of semiconductor processing, and discloses a semiconductor processing contour information extraction method, device and equipment and a storage medium, and the semiconductor processing contour information extraction method comprises the steps: obtaining a to-be-processed TEM graph and a design layout of a to-be-detected wafer; searching and determining a local layout corresponding to the TEM graph to be processed in the design layout; according to the contour distribution position in the local layout, determining a corresponding preliminary screening contour imaging area in the TEM graph to be processed; and contour edge detection is carried out according to the pixel value of each pixel point in the preliminary screening contour imaging area, and contour information of the processing contour of the to-be-detected wafer in the to-be-processed TEM graph is obtained. According to the method, the accuracy and reliability of contour information extraction in the TEM graph are realized by means of the design layout of the wafer to be tested, and a reliable data basis is provided for analysis of semiconductor process quality.

A cover for an infrared detector and a method of fabricating the cover are disclosed. The cover comprises a wafer comprising a material such as silicon that transmits infrared radiation. The wafer has a first surface and a second surface opposite the first surface. An antireflective region is formed in the wafer to enhance transmission of infrared radiation through the cover. The antireflective region comprises a first plurality of antireflective elements such as moth-eyes formed in the first surface. The first plurality of antireflective elements are sized and shaped and arranged relative to one another to form a region of graded refractive index at the first surface so as to reduce the amount of infrared radiation reflected by the cover at the antireflective region. The cover comprises a wall extending from the first surface and surrounding the antireflective region. The wall comprises a plurality of layers of material deposited on the wafer so that, when the cover is bonded to a sensor substrate via the wall, a cavity is formed that encapsulates a sensor region of the sensor substrate. The depth of the cavity may be adjusted by depositing the plurality of layers of material with a combined thickness equivalent to the desired depth of the cavity. A second plurality of antireflective elements may be formed in the second surface to enhance the antireflective properties of the antireflective region.

The invention discloses a crystal resonator sputter coating device and a preparation method of a crystal resonator, and belongs to the field of electronic components, the crystal resonator sputter coating device comprises a bottom plate, a lower electrode mask plate, a positioning plate, an upper electrode mask plate and a magnetic cover plate in sequence, the positioning plate is provided with a wafer positioning groove, a wafer is installed in the wafer positioning groove, and the magnetic cover plate is provided with a magnet. The upper electrode mask plate and the lower electrode mask plate are both provided with electrode holes, the thickness of the positioning plate is recorded as h < definite >, and one surface of at least one of the upper electrode mask plate and the lower electrode mask plate, which faces a wafer, is provided with a diffusion prevention bulge for preventing diffusion of electrode particles during film coating, and the thickness of the diffusion prevention bulge is recorded as h < definite >. The size of the dispersion preventing protrusion is matched with the size of the wafer positioning groove, the dispersion preventing protrusion is located in the wafer positioning groove during assembly, the thickness of the wafer is recorded as h wafer, and h wafer lt is smaller than or equal to 0.017 mm; and h, setting. The sputtering coating device solves the problem of electrode diffusion of the high-frequency crystal resonator in the existing sputtering coating device for the crystal resonator due to too small wafer thickness.