6431 results about "Wafering" patented technology

Process condition management facilitates the combination of dry development and etching into a single process chamber; eliminating the necessity for a post-dry development bake step during semiconductor manufacturing. Methods and apparatuses for rapidly instituting a large drop in process chamber pressure allow thermal dry development and an O2 flash treatment or thermal dry development and plasma hardmask open operations to take place without wafer transfer.

A method for detecting printing defects in a photolithography mask that will print on a wafer when using the photolithography mask in a specific photolithography system to print semiconductor structures on the wafer, the method comprising: acquiring a first aerial image of the photolithography mask using a mask inspection system; generating a second aerial image of the photolithography mask by applying a machine learning model (26) to the first aerial image, wherein the machine learning model is trained to map a first aerial image acquired by a mask inspection system to a second aerial image that emulates the application of the specific photolithography system to the photolithography mask; and detecting printing defects in the photolithography mask by comparing the second aerial image to a reference image.

The utility model relates to the technical field of acceleration sensors, in particular to a piezoelectric acceleration sensor, which comprises a shell, a mounting cavity is arranged in the shell, a shielding shell is fixedly connected in the mounting cavity, a crystal base is fixedly connected at the bottom end in the shielding shell, a PCB (printed circuit board) is arranged at the upper part in the shielding shell, and the crystal base is fixedly connected with the crystal base. An external force is applied along the polarization direction of the ceramic wafer to deform the ceramic wafer, the inside of the ceramic wafer is polarized, charges with opposite polarities appear on the two stressed end faces, and the ceramic wafer is recovered to an initial state if the external force is removed, so that mechanical energy is converted into electric energy by utilizing the direct piezoelectric effect of the ceramic wafer, and then the electric energy is subjected to signal processing; the sensor outputs 100mv / g alternating current voltage, so that vibration acceleration signals are measured, triangular shearing is adopted by a measuring element, a two-core shielding cable is adopted by a cable, and the sensor is small in size, light in weight and high in applicability.

The invention provides a packaging structure and a packaging method. The package structure includes a substrate, a wafer disposed on the substrate and having a backside surface remote from the substrate, a heat sink disposed over the substrate and having a surface facing the backside surface, and a thermal interface material disposed between the wafer and the heat sink, wherein there is no organic adhesive between the wafer and the heat sink.

The technology described herein is directed towards a metasurface arranged with unit cells for narrowband sound absorption, in which the unit cells are based on Helmholtz resonators that can have their resonant frequencies adjusted via MEMS actuators. A sound absorbing unit-cell is designed and constructed based on a general resonance frequency, and includes a neck portion and air chamber dimensioned to resonate close to the desired resonance frequency and thereby inverse phase cancel corresponding narrowband frequencies of incoming sound waves. A bimorph MEMS actuator and / or moveable part in the resonators, controlled by a controller, facilitates changing of the airflow the unit cells to adjust the resonant frequencies thereof, to cancel acoustic waves of different frequencies corresponding to noise, which can change over time. The unit cells can be distributed as part of a metasurface, which can be positioned proximate to a noise source to phase cancel the noise.

An adjustment method of a laser processing apparatus includes a spatial light modulator adjustment step of adjusting a spatial light modulator into a state ready for splitting a laser beam emitted from a laser oscillator and applying a plurality of laser beams such that laser beams will have a desired positional relation, a processing mark formation step of operating the laser oscillator to apply the laser beams to a wafer such that a plurality of processing marks is formed, an imaging step of stopping the laser oscillator, and imaging the processing marks formed at the wafer, and an aberration correction step of correcting aberration of the condenser by comparing the desired positional relation and a positional relation among the imaged processing marks, and adjusting the spatial light modulator such that the positional relation among the processing marks conforms to the desired positional relation.

The present invention relates to a vertically-laminated microdisplay panel requiring no color filter, the panel comprising: a back wafer, the top surface of which has multiple CMOS electrode pads aligned thereon; multiple LED laminates, each of which includes multiple light emitting units and multiple bonding layers vertically laminated on the back wafer, and which are aligned on the multiple CMOS electrode pads, respectively; and a common electrode formed on the multiple LED laminates, wherein each of the multiple LED laminates emits only a particular color by having a short passage formed through at least one light emitting unit among the multiple light emitting units to bypass current so as to prevent the current from being injected into the light emitting unit.

The invention provides a crystal growth device and a crystal growth method, and solves the technical problems of low wafer utilization rate, low crystal growth speed, low efficiency, poor uniformity and the like in the existing chip manufacturing process. According to the invention, a traditional cylindrical ampoule structure is abandoned, and the annular ampoule design is innovatively adopted, so that the crystal grows into an inner hollow cylinder shape which is highly matched with the specification of a target wafer; the heater is arranged on the inner side of the ampoule, a traditional outer side heating mode is replaced, and heat is intensively acted on crystals in cooperation with an adjusting center of a heat preservation material during crystal growth, so that heat loss is reduced; the periphery of the heater is made of heat insulation materials, heat radiation leakage is effectively restrained, meanwhile, the ampoule supporting structure is adjusted, and the whole device is simple, low in cost and light in weight.

The invention relates to the field of semiconductor processing, and discloses a semiconductor processing contour information extraction method, device and equipment and a storage medium, and the semiconductor processing contour information extraction method comprises the steps: obtaining a to-be-processed TEM graph and a design layout of a to-be-detected wafer; searching and determining a local layout corresponding to the TEM graph to be processed in the design layout; according to the contour distribution position in the local layout, determining a corresponding preliminary screening contour imaging area in the TEM graph to be processed; and contour edge detection is carried out according to the pixel value of each pixel point in the preliminary screening contour imaging area, and contour information of the processing contour of the to-be-detected wafer in the to-be-processed TEM graph is obtained. According to the method, the accuracy and reliability of contour information extraction in the TEM graph are realized by means of the design layout of the wafer to be tested, and a reliable data basis is provided for analysis of semiconductor process quality.

A cover for an infrared detector and a method of fabricating the cover are disclosed. The cover comprises a wafer comprising a material such as silicon that transmits infrared radiation. The wafer has a first surface and a second surface opposite the first surface. An antireflective region is formed in the wafer to enhance transmission of infrared radiation through the cover. The antireflective region comprises a first plurality of antireflective elements such as moth-eyes formed in the first surface. The first plurality of antireflective elements are sized and shaped and arranged relative to one another to form a region of graded refractive index at the first surface so as to reduce the amount of infrared radiation reflected by the cover at the antireflective region. The cover comprises a wall extending from the first surface and surrounding the antireflective region. The wall comprises a plurality of layers of material deposited on the wafer so that, when the cover is bonded to a sensor substrate via the wall, a cavity is formed that encapsulates a sensor region of the sensor substrate. The depth of the cavity may be adjusted by depositing the plurality of layers of material with a combined thickness equivalent to the desired depth of the cavity. A second plurality of antireflective elements may be formed in the second surface to enhance the antireflective properties of the antireflective region.

The invention discloses a crystal resonator sputter coating device and a preparation method of a crystal resonator, and belongs to the field of electronic components, the crystal resonator sputter coating device comprises a bottom plate, a lower electrode mask plate, a positioning plate, an upper electrode mask plate and a magnetic cover plate in sequence, the positioning plate is provided with a wafer positioning groove, a wafer is installed in the wafer positioning groove, and the magnetic cover plate is provided with a magnet. The upper electrode mask plate and the lower electrode mask plate are both provided with electrode holes, the thickness of the positioning plate is recorded as h < definite >, and one surface of at least one of the upper electrode mask plate and the lower electrode mask plate, which faces a wafer, is provided with a diffusion prevention bulge for preventing diffusion of electrode particles during film coating, and the thickness of the diffusion prevention bulge is recorded as h < definite >. The size of the dispersion preventing protrusion is matched with the size of the wafer positioning groove, the dispersion preventing protrusion is located in the wafer positioning groove during assembly, the thickness of the wafer is recorded as h wafer, and h wafer lt is smaller than or equal to 0.017 mm; and h, setting. The sputtering coating device solves the problem of electrode diffusion of the high-frequency crystal resonator in the existing sputtering coating device for the crystal resonator due to too small wafer thickness.

The utility model belongs to the technical field of vacuum evaporators, and discloses a crystal oscillator probe structure which comprises a crystal oscillator water pipe, a probe assembly is arranged at the bottom of the crystal oscillator water pipe, an installation structure is arranged on the inner wall of the probe assembly, and a driving assembly located outside the probe assembly is arranged at the top of the installation structure. A clamping structure is arranged in the probe assembly, the probe assembly comprises a mounting frame, and a detection head is movably sleeved with the mounting frame. According to the utility model, the detection head and the connecting plate are arranged, the reverse rotating block is rotated, and the whole detection head is limited through the clamping block, so that the screw rod is screwed out of the detection head, and the connecting plate, the protection plate, the limiting frame and the supporting frame are driven to move upwards and a wafer in the limiting frame is driven to move out of the mounting frame through the elastic force of the spring I; therefore, the wafer can be conveniently replaced by an operator, and the replacement efficiency of the wafer is improved.

The invention relates to the technical field of semiconductor equipment, and provides vertical epitaxy equipment and an epitaxy method. The apparatus comprises: a vertical reaction chamber; the wafer boat is used for vertically loading a plurality of wafers at intervals; the driving device is used for driving the boat to enter / exit the vertical reaction cavity; the material supply assembly comprises a process supply pipeline and a switching unit; the process material source comprises a cleaning material source for removing an oxide layer on the surface of the wafer and an epitaxial material source for executing an epitaxial process; the process monitoring device is used for monitoring process end points of the cleaning process and the epitaxial process; and the control device is in communication connection with the switching unit and the process monitoring device, and controls the switching unit to switch the supply of the material source according to the monitoring result of the process monitoring device. According to the vertical epitaxial equipment, the epitaxial process can be continuously executed without transferring the wafers after the oxide removal process of the plurality of wafers is executed in situ in the equipment, so that the output rate and the yield of the equipment are improved, the cost is reduced, and the fragment and pollution risks are reduced.

The utility model discloses a wafer processing device, and belongs to the technical field of semiconductors. The wafer processing device comprises a carrying table, a shock insulation pad and an ultrasonic device, wherein the carrying table is used for carrying a crystal ingot with a modified layer; the ultrasonic device is arranged above the carrying table, the ultrasonic device can generate transverse vibration waves, and the transverse vibration waves are used for vibrating along the crystal ingot and enabling cracks of the modified layer to extend in the transverse direction; and the bottom of the carrying table is fixedly arranged on the shock insulation pad. According to the utility model, the cracks of the modified layer formed on the crystal ingot by the laser pulse grow and are connected along the transverse direction, the longitudinal growth of the cracks is avoided, the production efficiency of the modified layer is improved, the laser pulse does not need to be intensively emitted, and the wafer processing period is shortened.

The invention belongs to the technical field of semiconductors, and relates to a silicon nitride film, a preparation method thereof and a semiconductor device. The preparation method of the silicon nitride film comprises the following steps: (1) introducing precursor gas into a cavity which is vacuumized, and preheating a wafer to a deposition temperature at the same time; (2) depositing a silicon nitride film on the surface of the wafer; (3) vacuumizing the cavity, introducing nitrogen, and performing plasma treatment on the silicon nitride film; and (4) vacuumizing the cavity, and cooling to finish the preparation. After the nitrogen is introduced in the step (3), the pressure in the cavity is 2.0 torr to 3.0 torr; the power of the plasma treatment is 450 W to 550 W. According to the invention, the silicon nitride film obtained by deposition is subjected to plasma treatment, and the plasma treatment process is optimized, so that the silicon nitride film with good uniformity and low roughness is prepared.

The invention provides a low-temperature bonding method for reducing surface damage and a bonding sheet thereof, and relates to the technical field of wafer bonding. In a high vacuum environment, the bonding surfaces of a first wafer and a second wafer which are to be bonded are subjected to first irradiation treatment by using a first atomic beam to obtain a first activation layer; s2, carrying out at least one second irradiation treatment on the bonding surface after the first irradiation treatment in the step S1 by adopting a second atomic beam to obtain a second activation layer; and carrying out ballasting bonding to obtain a bonding sheet. According to the low-temperature bonding method for reducing the surface damage, the bonding surface is activated in a gradient manner, so that the damage to the surface of the wafer caused by single activation can be reduced, the surface roughness is reduced, the probability of bubbles after bonding is reduced, and the bonding strength is improved.

Provided is a temperature measurement device for, in a situation where the temperature of a silicon wafer which is a measurement target is indirectly measured, removing, from actually measured radiance, the effects of radiance coming from a chamber member, and calculating the amount of change in the temperature of the measurement target. The temperature measurement device comprises: a chamber for accommodating a measurement target object; a heating unit; a chamber window at a position in the chamber opposite from the measurement target object; a temperature measurement unit for measuring the temperature of the measurement target object and the chamber window; and a computation unit for calculating the temperature of the measurement target object from detected values of the temperature measurement unit. The computation unit is provided with: a conversion unit for generating, from actually measured temperatures calculated from the detected values of the temperature measurement unit, conversion data pertaining to the amount of change in the temperature of the measurement target object corresponding to the amount of change in the temperature of the chamber window; a condition acquisition unit for acquiring a condition under which the measurement target object is heated; a detected value acquisition unit for acquiring a detected value of the temperature measurement unit; and a temperature correction unit for estimating the temperature of the measurement target object by using the conversion data to correct an actually measured temperature calculated from the detected value of the temperature measurement unit.

The invention discloses a high-efficiency low-loss preparation method of a single crystal silicon carbide wafer. The method comprises the following steps: A, grinding the surface of a single crystal silicon carbide ingot; b, the ultrafast pulse laser is modulated into N light spots, the N light spots are focused in the crystal ingot and distributed in the axial direction of the crystal ingot according to preset depth positions, and all the light spots are parallel to the horizontal direction; all the light spots are scanned at the same time, the scanning surface formed by the same light spot covers the cross section of the single crystal silicon carbide crystal ingot in the horizontal direction, and N laser modified layers are formed after scanning; c, carrying out stress-induced separation on the single crystal silicon carbide crystal ingot in the step B; and D, grinding the cutting surface of the single crystal silicon carbide wafer. According to the high-efficiency and low-loss preparation method of the single-crystal silicon carbide wafer, the preparation efficiency of the silicon carbide wafer is improved, meanwhile, the material loss of the single-crystal silicon carbide ingot is reduced, and the yield of the single-crystal silicon carbide ingot is improved.

In a general aspect, modular quantum processor configurations and methods, including integrating superconducting circuit quantum processor chips with a module integration plate that includes inter-module connections to form modular quantum processors are presented. In some cases, a quantum processing unit includes quantum processor chips, a module integration plate, and one or more caps. Each quantum processor chip includes a plurality of qubit devices. The quantum processor chips are disposed between the module integration plate and the one or more caps. The module integration plate includes recesses that house respective subsets of the quantum processor chips; and inter-module coupler devices that provide communication between the subsets of quantum processor chips housed in distinct recesses. The one or more cap wafers each includes signal lines that provide communication between at least one of the quantum processor chips and a control system.

A duplexer including a support substrate, a reception signal terminal, a transmit signal terminal, an antenna terminal, a receive side filter formed on the support substrate and electrically coupling the reception signal terminal to the antenna terminal, a transmit side filter formed on the support substrate and electrically coupling the transmit signal terminal to the antenna terminal, a side wall surrounding the receive side filter and the transmit side filter, and a cap wafer disposed on the side wall and enclosing the receive side filter and the transmit side filter in a cavity defined by the cap wafer, the side wall, and the support substrate, there being no post disposed on the antenna terminal and in contact with the cap wafer.

An electrostatic chuck (ESC) pedestal heater that includes a pedestal body and a surface on the pedestal body for receiving a substrate such as a high bow wafer. An electrode is embedded in the pedestal body to selectively generate an electrostatic force. The ESC pedestal heater includes a substrate contact surface that is raised to a height above the surface on the pedestal body and includes an inner seal band, an intermediate seal band, and an outer seal band extending. In the substrate contact surface, main spokes are provided that extend outward from the inner seal band to the outer seal band, and ancillary spokes may be provided between the main spokes in the region between the intermediate and outer seal bands. Additionally, contact areas or dots are provided in the substrate contact surface in the spaces between the bands and spokes.

A miniaturized interferometric integrated photonic gyroscope structure with top silicon oxide, middle silicon oxide and bottom silicon oxide deposited on a silicon substrate comprises broadband optical source or a semiconductor optical amplifier with silicon nitride ring resonator wavelength filter, connected with a thin film lithium niobate or piezoelectrically actuated silicon nitride phase modulator vertically coupled with a silicon nitride waveguide spiral loop. The silicon nitride waveguide spiral loop is patterned on thin bottom oxide layer with air trenches below it and connected with a germanium detector either through photonic wire bonding or vertically integrated through reflecting mirror embedded into silicon wafer. Various methods of coupling alternative materials are described and the potential of connecting several spiral waveguides for enhanced sensitivity in a gyroscope application.

A method of analyzing semiconductor wafers includes capturing a first image of a first crystalline material, etching a first surface of the first crystalline material to delineate etch defects in the first crystalline material, and capturing a second image of first crystalline material after etching the first surface of the first crystalline material. Based on the second image, labels of etch defects delineated in the first surface of the first crystalline material are generated. The first image and the labels of etch defects are spatially coordinated to form a defect map identifying one or more defects in the first image based on the delineated etch defects, and based on the defect map and nondestructive data obtained from a second crystalline material, defects in the second crystalline material are identified.

Provided is a pattern inspection system, including a scanning electron microscope (SEM) including an electron gun configured to generate a first electron beam and emit the generated first electron beam toward a first wafer, a detector configured to detect electrons emitted from the first wafer based on the first electron beam emitted toward the first wafer, and at least one processor configured to generate a first SEM image including a plurality of pixels based on the detected electrons, and determine, based on a period of a pattern extracted from the first SEM image, a pixel size of a second SEM image to be generated by the SEM with respect to a second wafer.

A laminated device wafer forming method includes a laminating step of laminating a first device wafer and a second device wafer to each other, the laminating step including a position adjusting step of imaging, by an imaging unit, a first predetermined line formed on a peripheral portion on the front surface side of the first device wafer and located outside rectangular regions corresponding to devices and a second predetermined line formed on a peripheral portion on the front surface side of the second device wafer and located outside the rectangular regions corresponding to the devices, and adjusting relative positions of the first device wafer and the second device wafer by using the first predetermined line and the second predetermined line.

The invention provides a piezoelectric quartz wafer grinding control method and system based on grinding frequency monitoring, and relates to the technical field of grinding control, the method comprises the following steps: executing multi-source data perception of piezoelectric quartz wafer grinding, and establishing an original behavior observation data stream; behavior modeling of each round of grinding is carried out; the time sequence grinding behavior data set is used for conducting grinding working condition sensing; activating a non-contact thickness sensing unit to execute real-time piezoelectric quartz wafer thickness sensing; with the target grinding requirement as a control target, grinding control reconstruction based on the real-time sensing result and the thickness sensing result is executed, and a reconstruction result is established; and carrying out grinding control management on the piezoelectric quartz wafer. The technical problem that in the prior art, due to the fact that grinding control depends on fixed parameters and lacks real-time sensing and feedback, the quality of the piezoelectric quartz wafer is unstable is solved, the grinding process is optimized and adjusted through the multiple sensing sources, and the machining precision and quality of piezoelectric quartz wafer grinding are improved.

Embodiments of the present disclosure provide a semiconductor device structure having vertically stacked complementary field effect transistors (CFETs). The CFETs are formed by bonding two substrates having semiconductor stacks formed thereon. A bonding structure is formed between the semiconductor stacks using wafer bonding technology. Embodiments of the resent disclosure enable the flexibility of choosing different N / P channel properties, provide a simple way to form the N / P channel isolation structure, and reduce potential leakage path and defects in stacked CFETs.

A system for detecting the presence of a wafer on a wafer handling robot. The system includes a robot having an end effector with a ledge portion having an opening; a vacuum pump; a conduit fluidly coupling the vacuum pump to the opening in the ledge portion; a pressure sensor located along the conduit to determine whether a measured pressure is within a target pressure range; and a wafer configured to be supported by the at least one end effector and spaced apart from the ledge portion by an air gap. When the wafer is supported by the at least one end effector in a proper position, the measured pressure is within the target pressure range. When the wafer is not supported by the wafer support structure or is supported by the wafer support structure in an improper position, the measured pressure is outside of the target pressure range.

The invention discloses a wafer automatic orientation stacking device based on visual identification, and belongs to the technical field of component manufacturing automation. The device comprises a control unit, a visual unit and a motion unit. The moving unit comprises a three-dimensional moving platform, a feeding disc, a receiving disc, a suction nozzle and a rotating motor; the visual unit comprises a light source and a camera. The camera is used for collecting images of the wafers in the feeding disc, the control unit is used for processing the images, the position and the direction of each wafer are accurately recognized, then the movement unit and the rotating motor are driven, the suction nozzle picks up the wafers and carries out rotation correction, and finally directional stacking is carried out on the receiving disc at the height calculated in a self-adaptive mode. The problems that manual stacking is low in efficiency and poor in consistency and existing equipment cannot carry out accurate directional stacking on wafers with similar lengths and widths are solved, and full automation, high precision and high stability of wafer stacking are achieved.

The invention belongs to the technical field of wafer polishing, and discloses a silicon carbide wafer electrochemical mechanical polishing device and a silicon carbide wafer electrochemical mechanical polishing process. The polishing head is provided with an electric brush, a metal ring, a copper spring and a copper column and is connected with a power supply anode through a wire; through holes are punched in the surface of the polishing pad, and the silicon carbide wafer adheres to the surface of the copper cylinder through conductive glue. In the rough polishing stage, hard abrasive particles are used for polishing under high potential, and surface scratches and deep damage are rapidly removed; and in the fine polishing stage, soft abrasive particles are used, potential is gradually reduced for polishing, shallow layer damage is removed, and the smooth and defect-free silicon carbide wafer is obtained. According to the electrochemical mechanical polishing device and process for the silicon carbide wafer, the silicon carbide slice can be rapidly machined into a smooth and defect-free surface within a short time, the polishing process of the silicon carbide is simplified, meanwhile, edge breakage and serious scratches generated by grinding are avoided, and the machining time and cost needed in the manufacturing process of the silicon carbide wafer are reduced.