57 results about "Compound semiconductor" patented technology

Light-emitting diode (LED), with: a GaN-based N-type compound semiconductor layer (57, 157); a GaN-based P-type compound semiconductor layer (63, 161); and an active region (59, 89, 159) of a multi-quantum pot structure with alternating laminated InGaN pot layers (71, 171) and junction layers (74, 84a, 84b, 83c, 173, 175, 177, 179), wherein the active region (59, 89, 159) is arranged between the N-type and P-type compound semiconductor layers (57, 157, 63, 161), wherein at least one of the barrier layers (74, 84a, 84b, 83c, 173, 175, 177, 179) in the active region (59, 89, 159) has an InGaN barrier layer (73, 83a, 83b, 83c) and a Si-doped GaN barrier layer (75), a doping concentration of Si in the InGaN barrier layer (73, 83a, 83b, 83c) is lower than that of the Si-doped GaN barrier layer (75) and the Si-doped GaN barrier layer (75) is positioned closer to the P-type compound semiconductor layer (63, 161) than the InGaN barrier layer (73, 83a, 83b, 83c).

An integrated multiplexing measurement system for measuring semiconductor devices (compound semiconductors) includes a main body, a fringe interferometer device, a white light interferometer probe, and a color conjugate focus measurement probe. The fringe interferometer device, the white light interferometer probe, and the color conjugate focus measurement probe are disposed in the main body. The fringe interferometer device is used to measure the warpage, concavity, color, brightness distribution, shape, and distribution of high-nitrogen areas of semiconductor devices. The white light interferometer probe and the color conjugate focus measurement probe are disposed together. The white light interferometer probe measures the surface roughness and surface depth of semiconductor devices. The color conjugate focus measurement probe (dispersion probe) measures the surface roughness and thickness of semiconductor devices.

The present disclosure provides a semiconductor optical device and a manufacturing method thereof. The semiconductor optical device includes a substrate including silicon and having a platform, a waveguide, and a diffraction grating in regions each different when viewed from above; and a semiconductor element bonded on the diffraction grating and the platform, the semiconductor element being in contact with an upper surface of the substrate, formed of a group III-V compound semiconductor, and having optical gain, the waveguide being optically coupled with the diffraction grating in an extension direction of the waveguide, the platform being located on both sides of the waveguide and the diffraction grating in a direction crossing the extension direction of the waveguide, the substrate having a groove between the platform and the waveguide, and the diffraction grating being continuous with the platform in the direction crossing the extension direction of the waveguide.

To facilitate handling and reduce hazards to an operator compared to a strong acid polishing liquid.SOLUTION: A polishing liquid for compound semiconductor substrate polishing includes an aqueous solution in which permanganate and a water-soluble compound in which a weak acid and a group 3 element, a lanthanide or a group 4 element are combined are dissolved. Preferably, the pH of the polishing liquid is greater than or equal to 3 and less than or equal to 7. Also preferably, the concentration of permanganate is 2.50 wt% or higher. The concentration of the water-soluble compound is greater than or equal to 0.55 wt% and less than or equal to 5.50 wt%.SELECTED DRAWING: Figure 1

A kind of partition heating semiconductor smelting crystal pulling device, it is related to semiconductor processing manufacturing technical field, including furnace body, multiple temperature-controlled heating zones are provided in furnace body inner cavity, and the heating zone includes growth temperature zone;Interface temperature monitoring mechanism is further arranged in the inner cavity of furnace body to monitor the solid-liquid interface temperature at the crucible;Rotary lifting mechanism is arranged at the top of furnace body;Rotary lifting mechanism rod passes through the upper end of furnace body and extends into the crystal pulling rod of growth temperature zone, and the rotary lifting mechanism drives the lifting and rotation of crystal pulling rod;Rotary lifting mechanism further includes rotating base, which drives rotary lifting mechanism to rotate when crystal pulling rod reaches the set height, through the precise temperature field of integrated multi-temperature zone, forced convection of rotary stirring, process flexibility of vertical pulling, and realize multi-system linkage control based on interface real temperature, meet the growth demand of high-precision materials such as multi-component compound semiconductor.

According to the invention there is provided a method of plasma dicing a workpiece comprising a compound semiconductor substrate, the method comprising: providing a workpiece comprising a compound semiconductor substrate; providing a mask structure on the workpiece, the mask structure comprising an upper layer comprising a hard mask material and a lower release layer between the upper layer and the front side of the workpiece, wherein the mask structure defines one or more dicing lanes; and plasma dicing the workpiece by a process which comprises plasma etching at least partially through the compound semiconductor substrate along the dicing lanes.

A photoelectric conversion device includes an amorphous substrate, an orientation control layer on the amorphous substrate, and a photoelectric conversion structure disposed on the orientation control layer and comprising a crystalline III-V compound semiconductor.

This invention provides a flip-chip type light-emitting diode and a method for manufacturing the same that improve light extraction efficiency and simplify the manufacturing process. [Solution] The flip-chip light-emitting diode includes a transparent substrate 208, an epitaxial composite layer, a first conductivity type electrode pad 211, a second conductivity type electrode pad 212, and a wafer bonding composite layer. The epitaxial composite layer is mounted on the transparent substrate and includes a first compound semiconductor layer 204, a light-emitting layer 203, and a second compound semiconductor layer 202. The first conductivity type electrode pad is mounted on the transparent substrate and electrically connected to the epitaxial composite layer. The second conductivity type electrode pad is mounted on the epitaxial composite layer, electrically connected to the epitaxial composite layer, and is located on the same side of the transparent substrate at the same height as the first conductivity type electrode pad. The wafer bonding composite layer includes at least one titanium dioxide (TiO2) layer 206 and at least one silicon dioxide (SiO2) layer 207.

A semiconductor layered body according to the present disclosure includes a first semiconductor layer formed of a III-V compound semiconductor, and a p-type InGaAs layer stacked on the first semiconductor layer and containing carbon as an impurity that generates majority carriers. The p-type InGaAs layer has a resistivity of 2.0×10−3 Ωcm or less.

A sensor for measuring acetone includes: an array of nanowires extending from a substrate, each of the nanowires having a corresponding surface substantially composed of a compound semiconductor and a diameter of less than 100 nm; an electrical contact material disposed on a first portion of the surface of each nanowire to form a Schottky barrier contact with the first portion; an amine-functionalized polymer disposed on the nanowires to functionalize a second portion of the surface of each nanowire; and an electrical contact with the substrate for measuring a current flowing between the electrical contact and the Schottky barrier contact on the nanowire when the nanowire is exposed to light or biased, such that when the nanowire is exposed to a mixture of molecules including acetone, the measured current characterizes the concentration of acetone in the mixture.

An apparatus includes a device comprising a semiconductor junction configured to generate a reference voltage, a voltage divider circuit, a comparator circuit, and a first output circuit. The voltage divider circuit may be configured to generate a first predetermined threshold voltage in response to the reference voltage. The comparator circuit may be configured to generate a first intermediate signal in response to a comparison of the first predetermined threshold voltage and an input signal. The first output circuit may be configured to generate a first output signal in response to the first intermediate signal.

To realize a higher polishing rate than when potassium permanganate and cerium ammonium nitrate are used as polishing liquids.SOLUTION: A polishing liquid for compound semiconductor substrate polishing includes an aqueous solution containing permanganate and a water-soluble compound containing a strong acid and a transition metal element. The transition metal element contains at least one element among a group 3 element, a lanthanoid, and a group 4 element, the concentration of ammonium ions and ammonia contained in the aqueous solution is lower than the concentration of the group 3 element, the lanthanoid, and the group 4 element.SELECTED DRAWING: Figure 1

This compound semiconductor substrate has a main surface. The compound semiconductor substrate contains impurities. The compound semiconductor substrate is formed of gallium arsenide or indium phosphide. In an X-ray topography image of the main surface, a ripple-like pattern caused by impurities is confirmed. The ripple-like pattern has a shape corresponding to a part of the wave pattern concentrically spreading from a wave source. The ripple-like pattern corresponds to a part of the wave pattern concentrically spreading from the wave source. The value obtained by dividing the distance between the center of the main surface and the wave source by the radius of the main surface is 0.1 to 0.9 inclusive.

The present invention provides a method and related apparatus for enabling plasma dicing of workpieces having compound semiconductor substrates. [Solution] The method includes providing a workpiece having a compound semiconductor substrate; providing a mask structure on the workpiece having an upper layer containing a hard mask material and a peeling lower layer between the front side of the workpiece and the upper layer, defining one or more dicing streets; and plasma dicing the workpiece by a process that includes plasma etching the compound semiconductor substrate at least partially along the dicing streets.

A semiconductor laser with the following characteristics is specified: - an epitaxial semiconductor layer sequence (2) based on a nitride compound semiconductor material comprising a p-doped region (5) and an n-doped region (6) as well as an active zone (7) arranged between the p-doped region (5) and the n-doped region (6), and - a mode-shifting layer (13) located within or adjacent to the n-doped region (6), where - the mode-shifting layer (13) positions a mode (25) of the electromagnetic laser radiation (20) such that it overlaps with a gain region (8) of the epitaxial semiconductor layer sequence (2) during operation, wherein the gain region (8) is configured to generate electromagnetic laser radiation (20) during operation, - the mode-shifting layer (13) has at least one via (16). Furthermore, a method for manufacturing a semiconductor laser is provided.

The present application aims to provide a compound semiconductor epitaxial wafer having good lifetime characteristics and a method for manufacturing the same. The compound semiconductor epitaxial wafer of the present application is a compound semiconductor epitaxial wafer in which a p-type GaAs 1‑x P x layer and an n-type GaAs 1‑x P x layer are formed as a p-n junction interface of a light emitting portion, and a region having a fixed nitrogen concentration is formed in a portion including the p-n junction interface, in which the region having the fixed nitrogen concentration has a nitrogen concentration in a range of 2.0 x 10 16 ~ 0.2 x 10 16 atoms / cm 3 , and Te as an n-type dopant is doped in a manner of gradually decreasing from the n-type GaAs 1‑x P x layer toward the p-type GaAs 1‑x P x layer.

A method for making a semiconductor device may include forming a superlattice layer on a semiconductor substrate. The superlattice layer may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming a piezoelectric layer on the superlattice layer and comprising a Group III-N semiconductor.

The application discloses a processing method of a compound semiconductor wafer, which comprises the following steps: attaching the compound semiconductor wafer to a carrier film, fixing the carrier film in a fixing ring, and packaging the edge of the carrier film through the fixing ring to form a bearing assembly; and performing a cutting process, a film expanding process, an etching process and a carrier film retraction process in the form of the bearing assembly. In the continuous process, the wafer is maintained in the form of a bearing assembly, the distance between the crystal grains is expanded after pre-expanding, so that the side wall of the cutting path can be etched clean, the yield rate meets the standard, then the carrier film is retracted to the initial state and is suitable for subsequent process steps, the bearing structure of the wafer does not need to be replaced, the process is simplified, the production cost is reduced, and the production efficiency is improved.

A monolithic focal plane array (FPA) device and method of fabrication. The method can include forming monolithic photodetectors or FPAs by heteroepitaxial growth of III-V PINs, APDs, or other photodetector devices in etched recesses of a Si-based read-out integrated circuit (ROIC) wafer. In a single-color device example, a wavelength configuring buffer layer and photodetector are grown within the etched recesses using compound semiconductor materials to enable infrared detection at desired wavelength(s). Depending on the application, this growth can be done on a graded compliant buffer layer and / or a selectively transparent buffer layer. And, semiconductor detectors can be incorporated to detect visible and NIR wavelengths in a dual-color device example. Further, the resulting devices can be configured as pixels in a sensor array device coupled to the ROIC device.

Provided is a semiconductor light-emitting device that has better light-emitting characteristics and improved reverse current characteristics compared to conventional light-emitting devices. 【Solution means】 The semiconductor light-emitting device according to the present invention is a semiconductor light-emitting device including a quantum well type light-emitting layer of a group III-V compound semiconductor in which a barrier layer and a well layer are repeatedly laminated. The barrier layer is AlGaInAs containing P 1-x P x consisting of (0 < x < 1), and the well layer is AlGaInAs 1-y P y consisting of (0 ≦ y ≦ x). The composition wavelength difference between the composition wavelength λ w of the well layer and the composition wavelength λ b of the barrier layer is 500 nm or more.

Method (400) for forming a compound semiconductor heterostructure transistor device (120), the method comprising: forming (402) an insulating layer (102) over a substrate (100); forming (404) a crystal lattice layer over the insulating layer (102); implanting (406) a material into the crystal lattice layer (104); selectively etching (408) a region (112) of the crystal lattice layer (104); forming (410) a first semiconductor material layer (110) over the crystal lattice layer; and forming (412) a second semiconductor material layer (114) over the first semiconductor material layer (110) to form a compound semiconductor heterostructure with a two-dimensional electron gas channel, wherein the electron gas channel is more conductive than both the first semiconductor material layer (110) and the second semiconductor material layer (114).

The invention discloses a method for improving hole concentration in a p-type compound semiconductor. Comprising the following steps: in the growth process of a p-type doped compound semiconductor epitaxial layer, co-doping and introducing a certain concentration of compensating impurity elements used for inhibiting intrinsic donor type point defects in a compound semiconductor; after growth of the p-type doped compound semiconductor epitaxial layer is completed, annealing treatment is carried out in a protective atmosphere containing non-metallic elements in the compound semiconductor; wherein the hole concentration of the epitaxial layer is improved through the combined action of the introduction of the compensating impurity element and the annealing treatment. According to the method disclosed by the invention, through a synergistic process of low-atomic-number same-family element doping and nitrogen-containing atmosphere annealing, synchronous improvement of the bulk material and the surface hole concentration is realized.

The application relates to a method for preparing a compound crystal by melt migration under high gravity, and relates to the field of semiconductor preparation, and the method comprises the following steps: placing a compound semiconductor polycrystal with a molecular formula of AxBy, an element of A and a seed crystal in a crucible in sequence and closely contacting each other, horizontally placing the crucible on a centrifugal rotating device, heating the crucible to T0 (800 DEG C < T0 < T m , starting the centrifugal rotating device, and making a centrifugal force G greater than 100g; after the centrifugal force is applied, the elements A and B in the melt move to both sides of the melt pool, the polycrystal is dissolved, and the seed crystal starts to grow into a single crystal; with the polycrystal being continuously dissolved and the single crystal being continuously grown, the melt migrates to the polycrystal direction, and single crystal preparation is realized. By using the method, single crystal can be grown at low temperature, the critical shear stress of a growth interface is improved, and dislocation density is reduced. Meanwhile, the requirement of a pressure equipment and growth conditions are reduced, and a crystal which cannot be prepared by a melt method can be efficiently grown by the melt method.

The application belongs to the technical field of compound semiconductor material crystal protection, and discloses a back surface protection method for a CdZnTe / CdTe wafer. The method aims to solve the problem that the back surface of the brittle semiconductor wafer is easily in contact with equipment during the front surface pixelization process, which causes scratches and further affects the performance of the detector. The method comprises the following steps: pasting a layer of debondable protective adhesive film on the back surface of the wafer; then performing processes such as front surface photoetching and electrode deposition; after the processes are completed, the debonding property of the adhesive film is activated by heating, ultraviolet irradiation or energization, so that the adhesive force of the adhesive film is greatly reduced or disappears; finally, the adhesive film is peeled off, and the back surface of the wafer is cleaned. The protective adhesive film can be pyrolytic, UV debondable or electrochemical, can stably adhere and provide physical isolation during the process, and can be removed cleanly and with low stress after the process. The method can effectively prevent the back surface of the wafer from being scratched, avoid the residual of the adhesive, and help improve the production yield and electrical performance consistency of the final device.

A method of plasma dicing a workpiece having a compound semiconductor substrate by plasma dicing the workpiece by a process which includes plasma etching at least partially through the compound semiconductor substrate along one or more dicing lanes. The workpiece includes a compound semiconductor substrate and a mask structure having an upper layer with a hard mask material and a lower release layer between the upper layer and the front side of the workpiece. The mask structure defines the one or more dicing lanes.

This invention provides a semiconductor device. The semiconductor device includes: a substrate; a buffer layer on the substrate; a channel layer on the buffer layer; a barrier layer on the channel layer, wherein a channel region is located in the channel layer and adjacent to the interface between the channel layer and the barrier layer; a doped compound semiconductor layer on a portion of the barrier layer; an undoped first capping layer on the doped compound semiconductor layer; a gate structure on the undoped first capping layer; and source / drain structures on opposite sides of the gate structure.

Provided is a solid-state imaging element with which it is possible to minimize crosstalk between different pixel columns while suppressing a decrease in quantum efficiency of a photoelectric conversion unit due to a pixel separating section. The solid-state imaging element includes a plurality of pixels arranged in a two-dimensional matrix in the X direction and the Y direction and including a photoelectric conversion unit (N-type semiconductor thin film) containing a compound semiconductor. In addition, the solid-state imaging element includes a pixel separating section disposed only at a pixel boundary extending in the X direction.

An optical semiconductor device includes a first optical device formed on a silicon substrate having a first surface, and a second optical device including a compound semiconductor, mounted on the first optical device, and having a second surface facing the first surface. The first optical device includes a first protrusion that protrudes toward the second surface, and a portion of the second surface makes contact with the first protrusion. In a plan view, the first protrusion is located on an inner side of an outer edge of the second optical device.

A light-emitting diode (LED) and its manufacturing method are provided. The LED comprises a substrate, an epitaxial composite layer, a light-restricting layer, and a transparent conductive layer. The epitaxial composite layer includes a first compound semiconductor layer, a light-emitting layer, and a second compound semiconductor layer, where the first compound semiconductor layer is sandwiched between the substrate and the light-emitting layer. The light-restricting layer, having a light-restricting opening, is disposed between the light-emitting layer and the second compound semiconductor layer. The transparent conductive layer is disposed on the epitaxial composite layer. The light emitted by the light-emitting layer is restricted to pass through the light-restricting opening of the light-restricting layer before being emitted externally via the transparent conductive layer.