45 results about "Charge-carrier density" patented technology

The invention discloses a method for simulating and predicting ablation of silicon carbide by femtosecond laser based on a dual-temperature model, and relates to the technical field of femtosecond laser processing. According to the method, the local carrier density of a silicon carbide material is corrected based on a Fokker-Plank equation; an improved dual-temperature model suitable for interaction of femtosecond laser and silicon carbide is constructed by combining a heat source model of the femtosecond laser; and then, after spatial discretization and time discretization in the depth direction are carried out on the material spatial three-dimensional model, a finite difference method is adopted to calculate the improved dual-temperature model to obtain a physical quantity evolution process in each grid unit, so that simulation prediction is carried out on the interaction process of femtosecond laser and silicon carbide under different laser parameters. The simulation prediction result can reflect the removal mechanism of thermally modified and non-thermally modified materials in the process of processing the silicon carbide by the femtosecond laser, and is favorable for guiding the practical process of processing the silicon carbide by the femtosecond laser, so that the processing quality and efficiency of the silicon carbide by the femtosecond laser can be improved.

An MOS junction barrier Schottky diode relates to the technical field of power semiconductor devices. The N-type substrate, the N-type epitaxial layer, the deep P region, the trench gate, the trench gate oxide layer, the conductive enhancement region and the isolation oxide layer are arranged between the cathode metal and the anode metal, the lower surface of the N-type substrate is in contact with the cathode metal, the upper surface of the N-type substrate is in contact with the lower surface of the N-type epitaxial layer, and the upper surface of the N-type epitaxial layer is in contact with the P region. The conductive enhancement region is arranged on the outer surface of the trench gate oxide layer and is in contact with the N-type epitaxial layer, and a part of the trench gate oxide layer, the conductive enhancement region, the isolation oxide layer and a part of the deep P region are respectively in contact with a part of the anode metal. According to the MOS junction barrier Schottky diode structure, the groove gate MOS structure is inserted into the adjacent P region of a traditional junction barrier Schottky (JBS) diode, so that the carrier density at a channel is improved, the channel resistance is reduced, and the reverse electric leakage characteristic and the forward voltage drop are further improved.

MOS junction barrier Schottky diode relates to the technical field of power semiconductor device. N-type substrate, N-type epitaxial layer, deep P region, slot gate, slot gate oxide layer, conductive enhancement region and isolation oxide layer are arranged between cathode metal and anode metal, the lower surface of the N-type substrate is in contact with the cathode metal, the upper surface is in contact with the lower surface of the N-type epitaxial layer, the upper surface of the N-type epitaxial layer is in contact with the P region, the conductive enhancement region is arranged on the outer surface of the slot gate oxide layer and is in contact with the N-type epitaxial layer, part of the slot gate oxide layer, the conductive enhancement region, the isolation oxide layer and part of the deep P region are respectively in contact with part of the anode metal. The MOS junction barrier Schottky diode structure of the application improves the carrier density at the channel, reduces the channel resistance, and further improves the reverse leakage current characteristics and the forward voltage drop by inserting a slot gate MOS structure in the adjacent P region of the traditional junction barrier Schottky (JBS) diode.

Thin-film transistor (100, 200, 300, 400, 500, 600, 700, 800, 900, 1000, 1100, 1200, 1300, 1400, 1500) which has: an active layer (ACT); a gate electrode (150) that overlaps at least partially with the active layer (ACT); and a source electrode (160) and a drain electrode (170) spaced apart from each other and each connected to the active layer (ACT); wherein the active layer (ACT) has a first active layer (130), and the first active layer (130) has: a channel section (130n) that overlaps with the gate electrode (150); a first connecting section (CON1) which is connected to a first side of the channel section (130n); and a second connecting section (CON2) which is connected to a second side of the channel section (130n), wherein the channel section (130n) has a crystalline structure, wherein the first connecting section (CON1) has a first amorphous section (130a) which is in contact with the channel section (130n), and wherein the second connecting section (CON2) has a second amorphous section (130b) which is in contact with the channel section (130n), wherein the active layer (ACT) further comprises an active barrier layer (140) which overlaps with and is in contact with the first active layer (130), the active barrier layer (140) comprises: a channel section (140n) that overlaps with the gate electrode (150), a first amorphous section (140a) connected to a first side of the channel section (140n) of the active barrier layer (140); and a second amorphous section (140b) connected to a second side of the channel section (140n) of the active barrier layer (140); wherein the channel section (140n) of the active barrier layer (140) has a crystalline structure, wherein the first amorphous section (140a) and the second amorphous section (140b) of the active barrier layer (140) each have an amorphous structure, and where the charge carrier density of the channel section (140n) of the active barrier layer (140) is lower than the charge carrier density of the channel section (130n) of the first active layer (130), and the active barrier layer (140) further comprises: a first active barrier layer (141) that is in contact with the first active layer (130); and a second active barrier layer (142) which is in contact with the first active layer (130), wherein the first active barrier layer (141) and the second active barrier layer (142) are arranged on opposite sides of the first active layer (130).

A multiple gate system for realizing the quantum anomalous Hall effect, including a top channel electrode which controls carrier density and electric field in a conduction channel, a first dielectric layer for the top channel gate, a patterned contact gate electrode which controls earner density on the contact and screens the top channel electrode's electric field on the contact, and a second dielectric layer for the contact gate, an electrically tunable material comprising semiconducting molybdenum ditelluride in the form of a first atomic sheet and a second atomic sheet, wherein first atomic sheet is rotated planarly from the second atomic sheet by about 2.5 to about 5 degrees, to form a geometrically stacked homobilayer moiré superlattice configured to host ferromagnetic states that spontaneously break time-reversal symmetry, where a perpendicular electric field is applied to the electrically tunable material, tuning the quantum anomalous Hall effect.

A multiple gate system for realizing the quantum anomalous Hall effect, including a top channel electrode which controls carrier density and electric field in a conduction channel, a first dielectric layer for the top channel gate, a patterned contact gate electrode which controls earner density on the contact and screens the top channel electrode's electric field on the contact, and a second dielectric layer for the contact gate, an electrically tunable material comprising semiconducting molybdenum ditelluride in the form of a first atomic sheet and a second atomic sheet, wherein first atomic sheet is rotated planarly from the second atomic sheet by about 2.5 to about 5 degrees, to form a geometrically stacked homobilayer moiré superlattice configured to host ferromagnetic states that spontaneously break time-reversal symmetry, where a perpendicular electric field is applied to the electrically tunable material, tuning the quantum anomalous Hall effect.

A new design for a near-UV emitting quantum well structure exhibits a small electron-hole wavefunction overlap. The small electron-hole overlap is beneficial for near UV-microLEDs because small overlap results in a high carrier density even at low current densities. Due to the higher carrier density, non-radiative recombination centers are saturated at relatively low current density in the newly disclosed design. The new design is therefore more robust against non-recombination losses at both intrinsic and surface defects, and capable of higher efficiency than conventional designs at low current densities.

The invention discloses a device aging simulation method, device and equipment, relates to the technical field of microelectronic semiconductor device reliability evaluation, and is used for solving the problems of low model precision, poor universality, low calculation efficiency and weak compatibility with device multi-physical field simulation of a semiconductor device reliability evaluation method in the prior art. Comprising the following steps: performing first electrothermal simulation on a target device structure model to generate carrier temperature distribution information and carrier density distribution information in a target device; the target device structure model is a corrected device model; based on the carrier temperature distribution information and the carrier density distribution information, establishing a defect physical model and a gate medium trap capture model by combining a rate equation; determining defect distribution information including spatial distribution in the target device according to the established model; and performing second electrothermal simulation on the target device structure model based on the defect distribution information, and determining aging electrical characteristic information of the target device.

The invention belongs to the technical field of photocatalysis, and discloses a preparation method of a visible light region LSPR (Localized Surface Plasmon Resonance) catalyst for absorbing and degrading organophosphorus pesticides. According to the invention, a plasma semiconductor MoO3-x is used as a precursor, shows a strong LSPR effect under incident light, and has high charge carrier density and large specific surface area. Sulfides such as sulfur indium zinc, sulfur indium cadmium and the like are loaded on the surface of the MoO3-x nanosheet through in-situ synthesis. The catalyst forms a Z-type heterojunction structure, not only can preserve photo-generated electrons with high reduction ability, but also can preserve photo-generated holes with high oxidation ability, effectively separates electron-hole pairs, and expands the photoresponse range. The method is suitable for degrading various organophosphorus pesticides such as amidothion, parathion-methyl and the like. The composite material is low in cost, simple to prepare, rich in active sites, large in specific surface area, high in degradation rate and good in stability, and the visible light utilization rate is increased by virtue of the LSPR effect.

In an embodiment an optoelectronic device includes a semiconductor layer stack having a planar first semiconductor layer of a first doping type, an active layer and a second semiconductor layer of a second doping type, wherein the second semiconductor layer has a main emission surface layer portion, a contact layer arranged on the first semiconductor layer opposite at least a first portion of the active layer, and a structured contact layer arranged on the second semiconductor layer opposite a second portion of the active layer, wherein the first portion and the second portion are spatially offset in a lateral direction to each other and configured to increase a local charge carrier density in an active region of the active layer partially common to or adjacent to the first and second portions of the active layer, and wherein the active region is defined by a projection of an overlapping section of the first and second portions onto the active layer.

The invention relates to the technical field of dielectric near-zero materials, in particular to a PVA / Fe2O3-coated CNTs flexible film with radio frequency dielectric near-zero performance and a preparation method and application thereof. According to the method disclosed by the invention, the polyvinyl alcohol (PVA) / iron trioxide coated carbon nano tube (Fe2O3 coated CNTs) film is successfully prepared, and the ENZ material with biocompatibility under radio frequency is prepared for the first time. According to the invention, the insulated Fe2O3 nanoparticles are limited in the CNTs channel (Fe2O3-coated CNTs) in situ, so that the carrier density is reduced, and the plasma frequency is reduced to radio frequency. The film shows good biocompatibility and flexibility, and shows huge potential in the technologies of invisible cloaks and wearable medical equipment.

A method of manufacturing an electronic device, the method comprising: varying a charge carrier density of a conductive material, the conductive material comprising an ionic material, where varying the charge carrier density of the conductive material comprises: varying the charge carrier density of the conductive material when the conductive material is in a state in which ion motion of the ionic material is frozen; and changing the charge carrier density. An electronic device is also described.

Provided are a multilayer structure and a semiconductor device in which electrical characteristics are stable from the surface of the semiconductor layer to deep regions thereof. The present disclosure provides a multilayer structure comprising a first semiconductor layer and a second semiconductor layer. The first semiconductor layer and the second semiconductor layer include a crystalline oxide containing gallium. The second semiconductor layer is disposed on the first semiconductor layer directly or via another layer. The lower limit of the carrier density at a depth of 1.0 μm or more from the surface of the second semiconductor layer is at least half of the carrier density at a depth of 1.0 μm from the surface.

The invention discloses an OLED light-emitting device and a preparation method thereof, and belongs to the technical field of organic electroluminescence, the OLED light-emitting device sequentially comprises a transparent substrate, an ITO anode, an anode modification layer, a hole transport layer, a light-emitting layer, an electron transport layer, a cathode modification layer and a cathode from bottom to top, the anode modification layer adopts a PTAA thin film processed by PLASA equipment, and the cathode modification layer adopts a PTAA thin film processed by PLASA equipment. The main body material of the light emitting layer is DTBDQ or 2, 9-bis (naphthalene-2-yl)-4, 7-diphenyl-1, 10-phenanthroline; according to the invention, DTBDQ or NBPhen is introduced as a main body material and PTAA is adopted as an anode modification layer material, so that the organic electroluminescent device which can regulate and control the carrier density of a composite region, avoid direct injection luminescence of an electrode, reduce exciton non-radiative recombination and improve the luminous efficiency and the stability of the device is obtained; the maximum external quantum efficiency and the maximum current efficiency are improved, and the efficiency roll-off of the device is reduced.

The utility model discloses a Si-based SiC-Si epitaxial wafer structure, which comprises a substrate and epitaxial layers sequentially deposited on the substrate, and the substrate is a heavily doped Si substrate; the epitaxial layer comprises a SiC epitaxial layer and a Si epitaxial layer, the SiC epitaxial layer is located on the heavily doped Si substrate, and the Si epitaxial layer is located on the SiC epitaxial layer. According to the utility model, the device is arranged on the Si epitaxial layer, so that the manufacturing cost and difficulty of the SiC device are greatly reduced, for a 22kV high-voltage device, only the SiC epitaxial layer with the thickness of about 20 [mu] m (100V / [mu] m) is required to serve as a voltage-withstanding drift layer, and a low-voltage power device is manufactured on the Si epitaxial layer; besides, the epitaxial wafer structure of the utility model is a Si-SiC-Si three-layer sandwich structure, so that lattice mismatch stress can be offset, and the warping degree of the epitaxial wafer can be improved. Meanwhile, the heterojunction between SiC and Si is beneficial to necessary carrier density control.

The application relates to the technical field of semiconductors, and discloses a modeling method of a MOS device, which comprises discretizing the geometric structure of the MOS device into a three-dimensional cell grid, and defining a state vector containing multi-physical field information for each cell in the three-dimensional cell grid, wherein the state vector at least comprises: carrier density and local electric potential for representing electrical characteristics, carrier average energy for representing quantum effects, local temperature for representing thermal effects, and defect state for representing reliability effects; and for simulating process variability of the device, the initial defect state of each cell in the three-dimensional cell grid is randomly set when the state vector is defined. A double-layer adaptive evolution rule system composed of a meta-learning rule layer and a basic rule layer is set, and the meta-learning rule layer can dynamically adjust the basic rule parameter set used by the basic rule layer according to the local macro state in the neighborhood of each cell.

A method for manufacturing an electronic device, wherein the method comprises: modifying the charge carrier density of an electrically conductive material, wherein the electrically conductive material comprises an ionic material, and wherein the modification of the charge carrier density of the electrically conductive material comprises modifying the charge carrier density while the electrically conductive material is in a state in which the ion motion of the ionic material is frozen. An electronic device is also described.

The two-dimensional photonic crystal laser comprises: a substrate composed of an n-type semiconductor; a p-type cladding layer (p-type semiconductor layer) disposed on the upper side of the substrate and composed of a p-type semiconductor; an active layer disposed on the upper side of the p-type cladding layer; a two-dimensional photonic crystal layer disposed on the upper side of the active layer and formed by periodically disposing different refractive index regions composed of a material having a refractive index different from that of the base material in a plate-shaped base material composed of an n-type semiconductor; a first tunneling layer disposed between the substrate and the p-type cladding layer and composed of an n-type semiconductor having a carrier density higher than that of the substrate; a second tunneling layer disposed between the first tunneling layer and the p-type cladding layer in contact with the first tunneling layer and composed of a p-type semiconductor having a carrier density higher than that of the p-type semiconductor layer; a first electrode disposed on the lower side of or within the substrate; and a second electrode disposed on the upper side of the two-dimensional photonic crystal layer.

The application discloses a bubble formation prediction method and device based on COMSOL-mediated black phosphorus quantum dot-mediated optical perforation, and the method comprises the following steps: based on COMSOL, a two-dimensional axisymmetric transient model of solid heat transfer and fluid heat transfer is constructed to obtain a solid heat transfer module and a fluid heat transfer module; a coefficient form partial differential equation interface is set to construct a carrier density equation; according to the carrier density equation, intermediate physical parameters are pre-set; according to the intermediate physical parameters, a heat source condition is pre-set, the solid heat transfer module and the fluid heat transfer module are coupled according to the heat source condition, and a target simulation model is obtained; according to the target simulation model, nanobubble generation is predicted to obtain a bubble formation time, a nanobubble area and a threshold laser flux. The application can improve the accuracy of optical perforation nanobubble generation prediction and can be widely applied to the fields of photo-induced perforation technology and nanobubble technology.

The application discloses a carrier transport simulation method and device, a medium and an electronic device. The application determines initial conditions and / or boundary conditions of carrier transport in a semiconductor device, and determines a Poisson equation and a Schrodinger equation corresponding to a closed quantum model. The carrier density in the semiconductor device is determined based on the initial conditions and / or the boundary conditions, the Poisson equation and the Schrodinger equation, so as to realize simulation of the carrier transport in the semiconductor device, and further realize research on the carrier transport in the semiconductor device.

A method for etching a semiconductor structure (110) is provided, the semiconductor structure comprising a sub-surface quantum structure (30) of a first III-V semiconductor material, beneath a surface layer (31) of a second III-V semiconductor material having a charge carrier density of less than 5×1017 cm−3. The sub-surface quantum structure may comprise, for example, a quantum well, or a quantum wire, or a quantum dot. The method comprises the steps of exposing the surface layer to an electrolyte (130), and applying a potential difference between the first III-V semiconductor material and the electrolyte, to electrochemically etch the sub-surface quantum structure (30) to form a plurality of nanostructures, while the surface layer (31) is not etched. A semiconductor structure, uses thereof, and devices incorporating such semiconductor structures are further provided.

A laminated piezoelectric body according to the present invention comprises: a polymer piezoelectric film; and a transparent conductive layer that is disposed on at least one surface of the polymer piezoelectric film and contains an indium-tin composite oxide as a main component. The ratio of the content of tin atoms to the total amount of indium and tin atoms in the transparent conductive layer is 1-6 mass%, the hole mobility of the transparent conductive layer is 10 cm2 / (V⋅s) to 20 cm2 / (V⋅s), and the carrier density is 1.0 × 1021 cm−3 to 3.0 × 1021 cm−3.

A multiple gate system for realizing the quantum anomalous Hall effect, including a top channel electrode which controls carrier density and electric field in a conduction channel, a first dielectric layer for the top channel gate, a patterned contact gate electrode which controls earner density on the contact and screens the top channel electrode's electric field on the contact, and a second dielectric layer for the contact gate, an electrically tunable material comprising semiconducting molybdenum ditelluride in the form of a first atomic sheet and a second atomic sheet, wherein first atomic sheet is rotated planarly from the second atomic sheet by about 2.5 to about 5 degrees, to form a geometrically stacked homobilayer moiré superlattice configured to host ferromagnetic states that spontaneously break time-reversal symmetry, where a perpendicular electric field is applied to the electrically tunable material, tuning the quantum anomalous Hall effect.

An interconnect structure including conducting layers of topological semi-metals and / or topological insulators. To increase charge carrier density in the conducting layers, a charge carrier doping layer present on at least one surface of the one or more conductive layers of topological semi-metals. The charge carrying doping layers have a charge carrier density greater than the topological semi-metals and / or topological insulators of the one or more conductive layers.

A method for porosifying a III-nitride material in a semiconductor structure is provided, the semiconductor structure comprising a sub-surface structure of a first III-nitride material, having a charge carrier density greater than 5×1017 cm−3, beneath a surface layer of a second III-nitride material, having a charge carrier density of between 1×1014 cm−3 and 1×1017 cm−3. The method comprises the steps of exposing the surface layer to an electrolyte, and applying a potential difference between the first III-nitride material and the electrolyte, so that the sub-surface structure is porosified by electrochemical etching, while the surface layer is not porosified. A semiconductor structure and uses thereof are further provided.

The invention relates to the technical field of photoelectric catalytic materials, and discloses a preparation method of a self-doped titanium dioxide nanotube electrode material. The method comprises the following steps: (1) forming a titanium dioxide nanotube array on the surface of a titanium mesh by adopting an anodic oxidation method to obtain a material I; (2) preheating the material I to obtain a material II; (3) in the presence of an ammonium sulfate solution, performing electrochemical reduction reaction by taking the material II as an anode to obtain a product I; and (4) carrying out annealing treatment on the product I at 400-500 DEG C to obtain the self-doped titanium dioxide nanotube electrode material. According to the self-doped titanium dioxide nanotube electrode material prepared by the method, the light response range can be expanded, the carrier density and charge transfer are increased, and the conductivity is improved.

The invention provides a semiconductor laser element with a carrier localization layer. The semiconductor laser element comprises a substrate, a lower limiting layer, a lower waveguide layer, an active layer, an upper waveguide layer and an upper limiting layer which are sequentially arranged from bottom to top. According to the semiconductor laser element, the carrier localization layers of a multi-layer structure are arranged in the semiconductor laser element, the multiple carrier localization layers are arranged in the multiple lower limiting layers in a penetrating and inserting mode, and meanwhile, the Philips ionization degree distribution characteristic and the saturated electron drift rate distribution characteristic of each carrier localization layer are limited; the quantum dot superlattice interface with irregular layers is constructed, interface charge transfer is regulated and controlled, cooperative modulation of carrier density and carrier mobility is achieved, the carrier localization effect is improved, the coupling rate from the pumping energy level to the laser upper energy level is improved, the stimulated radiation efficiency of the active layer is improved, population inversion is accelerated, and limiting factors are improved.

Various embodiments herein include a thin film transistor (TFT) including a channel layer stack having layers of different mobility. Since the carrier density in the high mobility channel layer and / or the plurality of high mobility channel layers is higher, the TFTs disclosed herein transport a higher total current through the low mobility and high mobility channel layers, which increases the response speed of the TFTs. The TFT further includes a gate structure disposed over the channel layer stack. The gate structure includes one or more gate electrodes, and thus the TFT is a top gate (TG), dual gate (DG), or bottom gate (BG) TFT. The channel layer stack includes a plurality of layers having different mobility. Layers with different mobility impart various benefits to the TFT. The high mobility layer increases the response speed of the TFT.

The application belongs to the technical field of water treatment, and particularly relates to a doped UiO-66(Zr) metal organic framework material and a preparation method and application thereof. The application changes the energy band structure by doping iron ions on the basis of the UiO-66(Zr) metal organic framework material, increases the carrier density, reduces the electron hole recombination rate, and thus improves the photocatalytic performance. The doped UiO-66(Zr) metal organic framework material is prepared by using a zirconium source, an iron source and terephthalic acid in a polar solvent through a one-step solvothermal method. The doped UiO-66(Zr) metal organic framework material has excellent anti-interference performance and cycle performance, can be applied to photocatalytic removal of heavy metals such as uranyl ions, lead ions and copper ions, and organic pollutants such as antibiotics and pesticides in wastewater, and has a very high removal rate and effect.

A metal separator plate for an electrochemical system, having at least a first laser-surface-treated region with a first passivation layer and a second region with a native or reconstructed passivation layer, wherein, as a result of the laser surface treatment, the first passivation layer has: a charge carrier density that is increased by at least 10%, and a surface area that is no more than 5% larger in relation to the native or reconstructed passivation layer. The present disclosure further relates to methods for producing and characterizing such a separator plate.