56results about How to "Reduce carrier density" patented technology

A gate electrode, a gate insulation film and an inorganic oxide film are formed in this order on a substrate, and a source electrode and a drain electrode are formed to partially cover the inorganic oxide film. Then, oxidation treatment is applied to reduce the carrier density at a region of the inorganic oxide film which is not covered by the electrodes and is used as a channel region of a semiconductor device.

An n-channel transistor or a p-channel transistor provided with a second gate electrode for controlling a threshold voltage in addition to a normal gate electrode is used for a complementary logic circuit. In addition, an insulated gate field-effect transistor with an extremely low off-state current is used as a switching element to control the potential of the second gate electrode. A channel formation region of the transistor which functions as a switching element includes a semiconductor material whose band gap is wider than that of a silicon semiconductor and whose intrinsic carrier density is lower than that of silicon.

Disclosed is a method that can stably manufacture thin films or bulk crystals of SiC monocrystals that are suitable for use in various devices and have low carrier densities of 5 1017 / cm3 or less, and preferably less than 1 1017 / cm3, with liquid phase growth technology using a SiC solution that uses a molten Si alloy as the solvent. As the Si alloy, the method uses an alloy having a composition represented by SixCryTiz wherein x, y and z (each is atom%) satisfy (1) 0.50 < x < 0.68, 0.08 < y < 0.35 and 0.08 < z < 0.35 or (2) 0.40 < x = 0.50, 0.15 < y < 0.40 and 0.15 < z < 0.35. x, y and z preferably satisfy 0.53 < x < 0.65, 0.1 < y < 0.3 and 0.1 < z < 0.3.

Provided is a memory device in which memory capacity per unit area is increased without making the manufacturing process complicated. The memory device includes a plurality of memory cells, a plurality of word lines, and a plurality of bit lines. Each of the plurality of memory cells includes a switching element and a capacitor including a first electrode and a second electrode. In at least one of the plurality of memory cells, in accordance with a potential applied to one of the plurality of word lines, the switching element controls a connection between one of the plurality of bit lines and the first electrode, and the second electrode is connected to another one of the plurality of word lines.

An object is to reduce parasitic capacitance of a signal line included in a liquid crystal display device. A transistor including an oxide semiconductor layer is used as a transistor provided in each pixel. Note that the oxide semiconductor layer is an oxide semiconductor layer which is highly purified by thoroughly removing impurities (hydrogen, water, or the like) which become electron suppliers (donors). Thus, the amount of leakage current (off-state current) can be reduced when the transistor is off. Therefore, a voltage applied to a liquid crystal element can be held without providing a capacitor in each pixel. In addition, a capacitor wiring extending to a pixel portion of the liquid crystal display device can be eliminated. Therefore, parasitic capacitance in a region where the signal line and the capacitor wiring intersect with each other can be eliminated.

The time taken to write a signal to a pixel is shortened in a display device. Further, a signal is written at high speed even when high voltage is applied. The display device includes a pixel including a transistor and a liquid crystal element electrically connected to a source or a drain of the transistor. The transistor includes an intrinsic or substantially intrinsic oxide semiconductor as a semiconductor material and has an off-state current of 1×10−17 A / μm or less. The pixel does not include a capacitor. Since it is not necessary to provide a capacitor, the time taken to write a signal can be shortened.

A semiconductor display device comprising a pixel portion and a signal line driver circuit comprising a first circuit, a second circuit configured to control timing of the sampled serial video signals by the first circuit, and a third circuit configured to perform signal processing on the parallel video signals, wherein the second circuit comprises a first semiconductor element formed over a first substrate, the first semiconductor element including a first semiconductor layer, wherein the third circuit comprises a second semiconductor element formed over a second substrate, the second semiconductor element including a second semiconductor layer, wherein the pixel portion comprises a third semiconductor element formed over the second substrate, the third semiconductor element including a third semiconductor layer, wherein the first semiconductor layer comprises silicon or germanium, and wherein each the second semiconductor layer and the third semiconductor layer has a wider bandgap than the first semiconductor layer.