302results about "Logic circuits using elementary logic circuit components" patented technology

The invention discloses an IO pin multiplexing circuit, a control method, a chip and electronic equipment, and the circuit comprises a gating module which is connected with a chip core and is used for transmitting a first enabling signal and / or a second enabling signal according to an on-chip control signal; the control word coding module is respectively connected with the gating module and the off-chip, and is used for enabling an IO pin to work in a control word coding mode according to the first enable signal; the digital signal input module is respectively connected with the gating module and is used for enabling an IO pin to work in a digital signal input mode according to a second enable signal; and the ESD module is connected with the digital signal input module and the control word coding module and is used for providing electrostatic protection. According to the invention, a pin function multiplexing technology is adopted, a control word writing function can be realized when the chip is just started through an enable signal switching function, a digital signal transmission function can be realized when the chip normally runs, the hardware cost is reduced, and the consumption of pin resources is reduced.

The invention discloses a single-cluster XNOR logic gate and a signal reading method thereof. One end of a single cluster device is provided with a source electrode and a drain electrode, and the other end of the single cluster device is provided with a gate electrode. A single-cluster XNOR logic gate is placed in a resonance tunneling area for signal reading, and when the input potential difference between a source electrode and a drain electrode of a single-cluster device is 0, the gate electrode outputs a high level; and when the input potential difference between the source electrode and the drain electrode of the single cluster device is not 0, the gate electrode outputs a low level.

A method for providing configuration information for generating physically obfuscated information on a chip with a plurality of circuits, which have a plurality of delay stages, is provided, wherein each delay stage has at least two delay elements, and the method includes determining, for each of the circuits, for each delay stage, which of the delay elements of the delay stage has the least delay among the delay elements of the delay stage, determining configuration information depending on the determined delay elements, which configuration information specifies a configuration of the circuit for each of the circuits, in which the delay elements of different delay stages are connected in series in such a way that at least one path from an input of the circuit to an output of the circuit is formed and storing the determined configuration information.

The invention provides an infrared detector driving and adjusting circuit, relates to the technical field of infrared detector driving, and constructs an infrared detector adjusting circuit to perform voltage adjustment, temperature judgment, power-on and power-off control and image signal generation on an infrared detector. Calculating an operation performance coefficient of each device, and calculating a device accumulation performance coefficient of each device according to the operation performance coefficient of each device; according to the device accumulation performance coefficient, accumulation adjustment labeling and performance parameter adjustment are carried out, and the infrared detector adjustment circuit has remarkable advantages in the aspect of solving the problems existing in a traditional infrared detector adjustment circuit and has great significance in improving the performance stability and reliability of an infrared detector.

Methods and systems for performing a surface code error detection cycle. In one aspect, a method includes initializing and applying Hadamard gates to multiple measurement qubits; performing entangling operations on a first set of paired qubits, wherein each pair comprises a measurement qubit coupled to a neighboring data qubit in a first direction; performing entangling operations on a second set of paired qubits, wherein each pair comprises a measurement qubit coupled to a neighboring data qubit in a second or third direction, the second and third direction being perpendicular to the first direction, the second direction being opposite to the third direction; performing entangling operations on a third set of paired qubits, wherein each pair comprises a measurement qubit coupled to a neighboring data qubit in a fourth direction, the fourth direction being opposite to the first direction; applying Hadamard gates to the measurement qubits; and measuring the measurement qubits.

A field-programmable-gate-array (FPGA) integrated-circuit (IC) chip configured to perform a logic function based on a look-up table (LUT), includes: multiple non-volatile memory cells therein configured to store multiple resulting values of the look-up table (LUT); and a programmable logic block therein having multiple static-random-access-memory (SRAM) cells configured to store the resulting values passed from the non-volatile memory cells, wherein the programmable logic block is configured to select, in accordance with one of the combinations of its inputs, one from the resulting values stored in the static-random-access-memory (SRAM) cells into its output.

Embodiments of the present disclosure include improved logic blocks with combined outputs for programmable logic devices and methods of operating and programming these logic blocks. In an exemplary aspect, a programmable logic device (PLD) is described. In some embodiments, the PLD includes a logic block. The logic block may include a first look-up table (LUT) circuit configured to generate a first output; a second LUT circuit configured to generate a second output; a ripple logic circuit configured to receive the first output and the second output and generate a third output; and a three-to-one multiplexer circuit configured to receive the first output, the second output, and the third output and selectively produce an output of the logic block.

The invention discloses a level shift circuit, a control method thereof and electronic equipment, and relates to the technical field of integrated circuits. The circuit comprises a logic control module, an AC / DC coupling module and an inverted output module, in the logic control module, a first signal input end is connected with an input signal source, and a second signal input end is connected with an enable signal source; the AC-DC coupling module comprises a DC coupling unit and an AC coupling unit; in the direct current coupling unit, a first control input end is connected with a first control output end, and a second control input end is connected with a second control output end; in the AC coupling unit, an AC coupling input end is connected with a first control output end; the AC coupling output end is connected with the DC coupling output end; the inverted input end of the inverted output module is connected with the DC coupling output end, and the inverted output end is used for outputting a target level shift signal. And a low-delay, high-speed and good-duty-ratio level shifting function can be realized for an alternating current signal and a direct current signal.

A multiplying circuit of an operation stage of a pipeline analog-to-digital converter (ADC) has first and second output terminals and is configured to generate first and second output signals according to first and second input signals. The multiplying circuit includes a voltage conversion circuit, first and second transistors, and first and second current sources. The voltage conversion circuit is configured to generate a first intermediate voltage and a second intermediate voltage according to the first input signal and the second input signal. The first transistor has a first terminal coupled to the first output terminal, a second terminal coupled to a power supply voltage, and a first control terminal receiving the first intermediate voltage. The second transistor has a third terminal coupled to the second output terminal, a fourth terminal coupled to the power supply voltage, and a second control terminal receiving the second intermediate voltage.

A chassis front-end is disclosed. The chassis front-end may include a switchboard including an Ethernet switch, a Baseboard Management Controller, and a mid-plane connector. The chassis front-end may also include a mid-plane including at least one storage device connector and a speed logic to inform at least one storage device of an Ethernet speed of the chassis front-end. The Ethernet speeds may vary.

To utilize unused or underutilized input and output pins without significantly impacting power consumption and die area, an adaptive logic module (ALM) of a programmable logic device can be implemented with an additional 2LUT to improve low function packing density and broad function mapping coverage. The 2LUT can also serve as a route-through to provide direct access to ALM registers with or without input inversion. The extended ALM can also utilize route-through configurations of the additional 2LUT to enhance the connectivity of the ALM inputs and outputs.

The utility model relates to a PD detection alarm protection circuit of a laser. The PD detection alarm protection circuit comprises a PD sensor, a resistance voltage division circuit, an in-phase proportion amplification circuit, a comparator circuit and a voltage reference circuit, the PD sensor collects a PD photocurrent signal of the laser and then sends the PD photocurrent signal to the resistance voltage division circuit; the resistance voltage division circuit converts the PD photocurrent signal into a PD voltage signal and then sends the PD voltage signal to the in-phase proportion amplification circuit; the in-phase proportional amplification circuit amplifies the PD voltage signal and then transmits the PD voltage signal to one input end of the comparator circuit, the other input end of the comparator circuit is connected with the voltage reference circuit, and the output end of the comparator circuit outputs a processed PD signal; by optimizing a pre-stage amplification framework and a post-stage reference design, the detection reliability is remarkably improved while the cost is reduced, and the detection response speed is very high. And real-time monitoring can be realized through an upper computer. The system is especially suitable for a safety protection system of industrial laser equipment.

The invention provides a synchronous time sequence sub-threshold logic circuit optimization method and device, and relates to the technical field of electronics. Converting a basic combinational logic unit in the sub-threshold logic circuit to be optimized into a sensitive amplifier-pass transistor logic circuit to form a first sub-threshold logic circuit; the sub-threshold logic circuit to be optimized is a circuit which is based on a sub-threshold digital standard cell library and is composed of a basic combinational logic unit and a trigger unit. Then determining matching device groups respectively included in a sensitive amplifier and a transmission transistor network in the sensitive amplifier-transmission transistor logic circuit, setting an incidence relation of device size parameters in each matching device group, and optimizing the device size parameters of the sensitive amplifier-transmission transistor logic circuit; and forming a second sub-threshold logic circuit. Thus, signal weakening is reduced, time delay is reduced, the working frequency of the subthreshold logic circuit is improved, and the transmission transistor network is adopted to support circuit units with unfixed logic functions.

A transmitter circuit (1) that receives parallel signals (D(1:4)) and outputs a serial signal (D_Tx) in response to the parallel signals may include; a clock generator (20) generating first clock signals (CK(1:4)) having different respective phases, a multiplexer (10) including selection circuits (11, 12, 13, 14) respectively configured to selectively provide at least two of the parallel signals (D1, D2 or D2, d3 or D3, D4 or D4, D1) to an output node in response to at least two of the first clock signals (Ck1, Ck2 or Ck2, Ck3 or Ck3, Ck4 or Ck4, Ck1), and an output driver (15) generating the serial signal (D_Tx) by amplifying a signal at the output node.

Integrated circuit devices and circuitry for digital filtering are provided. An integrated circuit device may include a first digital signal processing (DSP) block with first hardened arithmetic circuitry and an output register to store an output of the first DSP block and a second DSP block with second hardened arithmetic circuitry and an input register to receive the output of the first DSP block. An input signal chain may include a first set of registers to provide first input data signals to the first DSP block, a second set of registers to provide second input data signals to the second DSP block, and a third set of registers connected between the first set of registers and the second set of registers to provide delay equal to that of the output register of the first DSP block and the input register of the second DSP block.

The present invention provides a redundant interlocking circuit for an automotive-grade chip. The redundant interlocking circuit includes a first low-side driver module, a second low-side driver module, a first interlocking circuit, and a second interlocking circuit. When the first low-side driver module is working, the second low-side driver module is locked in a closed state through the first interlocking circuit and the second interlocking circuit. When the second low-side driver module is working, the first low-side driver module is locked in a closed state through the first interlocking circuit and the second interlocking circuit. The first interlocking circuit and the second interlocking circuit can each independently implement an interlocking function between the first low-side driver module and the second low-side driver module, that is, the first interlocking circuit and the second interlocking circuit implement redundant interlocking. After one of the first interlocking circuit and the second interlocking circuit is destroyed, the interlocking function between the first low-side driver module and the second low-side driver module can still be implemented through the other one, thereby preventing the interlocking function from failing.

A chip package used as a logic drive, includes: multiple semiconductor chips, a polymer layer horizontally between the semiconductor chips; multiple metal layers over the semiconductor chips and polymer layer, wherein the metal layers are connected to the semiconductor chips and extend across edges of the semiconductor chips, wherein one of the metal layers has a thickness between 0.5 and 5 micrometers and a trace width between 0.5 and 5 micrometers; multiple dielectric layers each between neighboring two of the metal layers and over the semiconductor chips and polymer layer, wherein the dielectric layers extend across the edges of the semiconductor chips, wherein one of the dielectric layers has a thickness between 0.5 and 5 micrometers; and multiple metal bumps on a top one of the metal layers, wherein one of the semiconductor chips is a FPGA IC chip, and another one of the semiconductor chips is a NVMIC chip.

Circuits, devices, and methods relating to a phase interpolator are described herein. The phase interpolator may comprise a first plurality of functional units and a second plurality of functional units, and may be controlled, in part, by an encoding scheme. The phase interpolator may be designed to have a layout such that a turn-on resistance across the first plurality of functional units in response to a first code of the encoding scheme is equal to a turn-on resistance across the second plurality of functional units in response to a second code of the encoding scheme.

Electronic control device, comprising: a logic circuit (255) capable of reconfiguring a plurality of arithmetic circuits, including a first circuit and a second circuit; a reconfiguration controller (204) that reconfigures the arithmetic circuits based on reconfiguration commands and verifies the reconfigured arithmetic circuits; and a process controller (202) that sends the reconfiguration commands to the reconfiguration controller (204) and commands the arithmetic circuits to perform operations, wherein the reconfiguration controller (204) reconfigures and verifies the first circuit when a first reconfiguration command is received, The process controller (202) of the first circuit commands to perform an operation when the verification of the first circuit by the reconfiguration controller (204) is complete. After the first circuit has been reconfigured, the process controller (202) sends a second reconfiguration command to the reconfiguration controller (204) and orders the reconfiguration controller (204) to start the reconfiguration of the second circuit until the first circuit has completed its operation.

An electronic circuit includes: a data input port, a timing adjustment circuit configured to receive data from the data input port, first and second logic circuits, a multiplexer, and a data output port. The timing adjustment circuit includes two paths configured to impose first and second delays to generate first and second delayed data. The first and second logic circuits are configured to respectively receive the first and second delayed data and generate first and second logic outputs. The first logic output expands a pulse width corresponding to a first logic value. The second logic output expands a pulse width corresponding to a second logic value. The multiplexer is configured to select, based on an equalization feedback, at least one of the first logic output or the second logic output, to provide the multiplexer output. The data output port is configured to output equalized data based on the multiplexer output.

An application specific integrated circuit, ASIC, package for use in an electrical or electronic device is disclosed. The ASIC package comprises a plurality of functional units (411, 412, 413), a plurality of terminals, and a plurality of switches (421, 422). The plurality of switches are connected in series along a portion of an electrical current path within the ASIC package, and at least one of the functional units comprises switching control logic configured to independently switch each of the switches between an open-circuit state and a closed-circuit state. Additionally, at least one of the functional units is configured to provide a monitoring function comprising determining occurrence of a fault condition associated with operation of the electrical or electronic device, and to transmit a fault trigger signal to the switching control logic in response to a fault condition being determined. The switching control logic is configured to trigger an open-circuit state of at least one of the plurality of switches in response to receiving the fault trigger signal. This can provide enhanced safety by enabling the isolation of the ASIC package from power sources (e.g. a charger and / or a battery) and / or a load (e.g. a heater) if a fault is determined by a safety-related functional unit of the ASIC package.

Embodiments of the present disclosure provide a signal processing circuit and a memory. A command decoding circuit is included, which includes: a preprocessing circuit, configured to: receive a first chip select signal corresponding to previous one cycle of a current cycle corresponding to a current chip select signal and a first command signal corresponding to the previous one cycle of the current cycle corresponding to signal, and perform a logical operation on the first chip select signal and the first command signal to generate a first chip select identifier signal; and an operation circuit, connected to the preprocessing circuit, and configured to: receive the first chip select identifier signal and the current chip select signal, and generate a decoded command corresponding to the current chip select signal when the current chip select signal is in an enabled state and the first chip select identifier signal is in a disabled state.

Embodiments of the present application provide a driving circuit, an electronic product, a control method, a medium and equipment. The driving circuit comprises a boosting unit, a logic unit and an output unit. The boosting unit is configured to perform boosting processing on a received input waveform to output a boosted waveform; the input end of the logic unit is connected to the input end of the boosting unit, and the logic unit is configured to output a logic signal according to the received input waveform; and the input end of the output unit is connected to the output end of the boosting unit, and the output unit is configured to receive the boosted waveform and control the output of the boosted waveform according to the logic signal output by the logic unit. Therefore, the technical effects of precise output with high voltage and high stability, wide output range and small volume of the driving circuit can be achieved.

A wearable sensor device includes a liquid metal wire that includes an elongated tube with an internal cavity having a uniform cross-sectional geometry, the internal cavity is at least partially filled with liquid metal. The wearable sensor device further includes detection circuitry to detect a change in an electrical attribute of the liquid metal wire based on a temporary change in the cross-sectional geometry, and generate sensor data to identify an event associated with a wearer of the wearable device based on the temporary change in the cross-sectional geometry.

The disclosure provides a detection system based on proximity switches and a vehicle sampling device, wherein the detection system comprises a plurality of proximity switches, a power module and a control module; the proximity switch comprises a first power supply end, a second power supply end and a signal output end; the power module comprises a first power supply line and a second power supply line with opposite polarities; the signal output end of the first proximity switch and the first power supply end of the second proximity switch in adjacent proximity switches are connected, the first power supply line is connected with the first power supply end of the first proximity switch in all proximity switches, the second power supply line is connected with the second power supply end of each proximity switch, and the signal input end of the control module is connected with the signal output end of the last proximity switch in all proximity switches. In the detection system based on proximity switches and the vehicle sampling device, the ''and'' logic function of the plurality of proximity switches is realized by using series connection, so that the occupation of multiple channels in the control module and the increase of the preamplifier are avoided.

The bidirectional logic element of the present invention comprises a function / inverse function control unit, a forward input unit, a forward information transfer unit, a backward input unit, a backward information transfer unit, a bidirectional function operation unit that performs both a forward logical operation and a backward operation, a forward function transfer unit, and a backward function transfer unit. The arithmetic device and arithmetic method of the present invention use the above bidirectional logic element.

The invention discloses a time delay circuit which comprises a first selector, a plurality of series-connected time delay units, an NAND gate, a second selector and a plurality of phase inverters, a first data input end of the first selector is connected with a first enable signal, and the first enable signal serves as an input signal of the time delay circuit in an input mode; the delay units are connected with the output end of the first selector, the first input end of the NAND gate is connected to the output end of the last-stage delay unit, the second input end of the NAND gate is connected with a second enable signal, the second enable signal is used for controlling the working mode of the delay circuit, and the selection control end of the second selector is connected to the output end of the NAND gate. The first data input end and the second data input end are connected through the first phase inverter, the output end is connected to the second data input end of the first selector through the second phase inverter, and the third phase inverter is connected to the output end of the second selector and used for outputting an output signal of the time delay circuit. The method is used for testing register establishment time and retention time.

To provide a programmable logic device (PLD) having a less number of switches and high reliability.SOLUTION: A PLD includes: first to third columns each having a plurality of logic elements (LE); a plurality of first to third wiring lines to which a signal output from LE of the first to third columns are respectively given; a plurality of fourth wiring lines to which a signal inputted to LE on the second column are respectively given; a plurality of groups each of which has at least a first switch and a second switch for selecting a conduction state or a non-conduction state according to a potential of a node to which a signal is given through the first switch; a fifth wiring line to which a predetermined potential is given; and a third switch for controlling electrical connection between the plurality of fourth wiring lines and the fifth wiring line. The plurality of first to third wiring lines are respectively provided between the first column and the second column or between the second column and the third column, and in one group of the plurality of groups selected according to the signal, and when the second switch becomes a conduction state, one of the plurality of first to third wiring lines is connected to one of the plurality of fourth wiring lines.SELECTED DRAWING: Figure 1

Methods, systems and apparatus for targeting many-body states on a quantum computer. In one aspect, a method includes an adaptive phase shift method that includes preparing the quantum system in an initial state, wherein the initial state has non-zero overlap with the target eigenstate; preparing an ancilla qubit in a zero computational basis state; and iteratively applying a quantum eigenstate locking circuit to the quantum system and ancilla qubit until the state of the quantum system approximates the target eigenstate, wherein the quantum eigenstate locking circuit comprises a phase gate that, at each n-th iteration, is updated using a current average energy estimate of the quantum system.