557results about "Logic circuits using elementary logic circuit components" patented technology

The present invention relates to a reconfigurable logic-in-memory cell consisting of triple-gate feedback memory elements. The reconfigurable logic-in-memory cell according to one embodiment of the present invention includes a plurality of triple-gate feedback memory elements including a drain region, a channel region, a source region, and a gate region where first and second programming gate electrodes and a control gate electrode are formed on the channel region.

The present disclosure relates to a universal logic memory block using a plurality of universal logic memory cells. The universal logic memory block according to one embodiment of the present disclosure may implement various combinational logical operations in a single structure by combining logical operation results from a plurality of universal logic memory cells using triple-gate silicon devices driven by a positive feedback loop.

The invention discloses an IO pin multiplexing circuit, a control method, a chip and electronic equipment, and the circuit comprises a gating module which is connected with a chip core and is used for transmitting a first enabling signal and / or a second enabling signal according to an on-chip control signal; the control word coding module is respectively connected with the gating module and the off-chip, and is used for enabling an IO pin to work in a control word coding mode according to the first enable signal; the digital signal input module is respectively connected with the gating module and is used for enabling an IO pin to work in a digital signal input mode according to a second enable signal; and the ESD module is connected with the digital signal input module and the control word coding module and is used for providing electrostatic protection. According to the invention, a pin function multiplexing technology is adopted, a control word writing function can be realized when the chip is just started through an enable signal switching function, a digital signal transmission function can be realized when the chip normally runs, the hardware cost is reduced, and the consumption of pin resources is reduced.

The invention belongs to the field of electronic devices, particularly relates to an anti-SET reinforced phase frequency detector, and aims to solve the problems that the existing SET injection can change the output logic state of a PFD (phase frequency detector), and a post-stage circuit obtains a wrong phase difference indication signal. According to the invention, an output UP signal and an output DOWN signal of a first-stage unit are used as the input of an input control logic, and the input control logic outputs four indication signals; the input of the first output control logic is four indication signals, and the output of the first output control logic is a first conduction control signal; the second-stage unit is used for carrying out rising edge sampling on the UP signal and the DOWN signal respectively and outputting two indication signals; the input of the phase selector is a reference clock signal, a feedback clock signal and two indication signals, the output of the phase selector is the input of the second output control logic, and the second output control logic outputs a second conduction control signal. According to the invention, the output logic state is not changed during SET injection, and a correct phase difference indication signal is obtained at a rear stage.

An apparatus, including: a first multiplexer including inputs configured to receive an input data signal and a scan signal, and a select input configured to receive shift control signal; a first latch including an input coupled to an output of the first multiplexer, and a complementary (e.g., inverting) clock input configured to receive a clock signal; a second latch including an input coupled to the output of the first multiplexer, and a non-complementary clock input configured to receive the clock signal; and a second multiplexer including inputs coupled to outputs of the first and second latches, respectively, a select input configured to receive the clock signal, and an output configured to generate an output data or scan signal.

According to the image recognition device and method, a current resistance relational expression is obtained according to the resistance values of a plurality of second memristors, the resistance value of a second column selection switch and a plurality of test currents, and the resistance value when the column selection switch is conducted is considered; after the weight voltage obtained according to the conductance value of the first memristor and the current resistance relational expression is input to the row signal end of the memristor sub-array, accurate mapping of the conductance value of the first memristor and the weight of the neural network can be realized. The plurality of column currents output from the plurality of column signal ends of the memristor sub-array are multiplication accumulation of the to-be-identified voltage and the conductance value of the memristor sub-array on the column, so that the accuracy of the image identification result determined according to the plurality of column currents is very high; switch control and data control are separated to different FPGAs, so that the reliability, flexibility and isolation of the device can be improved; and the serial-parallel conversion module is arranged, so that the IO interface pressure of the FPGA can be reduced, and the expandability is improved.

An input / output interface circuit includes a common receiving driver configured to receive a differential clock signal and output a first clock signal corresponding to the differential clock signal and a pair of sub-channels connected to the common receiving driver. Each sub-channel of the pair of sub-channels may be configured to receive the first clock signal and a chip select signal, output a second clock signal through a logical AND operation of the first clock signal and the chip select signal, and output a single clock signal, among the second clock signal and one or more divided clock signals. The single clock signal is used to sample a command address signal.

The invention discloses a single-cluster XNOR logic gate and a signal reading method thereof. One end of a single cluster device is provided with a source electrode and a drain electrode, and the other end of the single cluster device is provided with a gate electrode. A single-cluster XNOR logic gate is placed in a resonance tunneling area for signal reading, and when the input potential difference between a source electrode and a drain electrode of a single-cluster device is 0, the gate electrode outputs a high level; and when the input potential difference between the source electrode and the drain electrode of the single cluster device is not 0, the gate electrode outputs a low level.

A method for providing configuration information for generating physically obfuscated information on a chip with a plurality of circuits, which have a plurality of delay stages, is provided, wherein each delay stage has at least two delay elements, and the method includes determining, for each of the circuits, for each delay stage, which of the delay elements of the delay stage has the least delay among the delay elements of the delay stage, determining configuration information depending on the determined delay elements, which configuration information specifies a configuration of the circuit for each of the circuits, in which the delay elements of different delay stages are connected in series in such a way that at least one path from an input of the circuit to an output of the circuit is formed and storing the determined configuration information.

A circuit for driving digital-to-analog converter (DAC) comprising a serializer (110, 210) configured to combine multiple signals to one input signal to drive a forward inverter (311) coupled to a first node (A) with a first impedance in serial configuration and a first capacitance (C1) in shunt configuration. The circuit includes a chain of inverters (321, 322) coupled in series to transfer the input signal from the first node (A) to the fifth node based on a signal transfer function. The circuit further includes a feedback inverter (425) between the third node and the first node (A) to form a feedback loop with two inverters in the chain, adding peaking in the signal transfer function at the first node (A). A second feedback inverter (425) can be added between the fifth node and the third node to add peaking in the signal transfer function at the third node. The feedback inverter (425) is designed as a current-starved inverter in order to alleviate hot-carrier injection (HCI) aging of the transistors and add programmability in the peaking. The circuit includes a DAC switch coupled to the fifth node.

The invention discloses a gallium nitride driving circuit which is used for generating driving voltage for driving a gallium nitride transistor. The circuit comprises a gallium nitride switching tube, an upper switching tube, a lower switching tube, a clamping module, an energy collection module, a diode, a capacitor, a clamping and logic driving module and a bias voltage generation module. The gallium nitride switch tube is connected with the drain electrode of the gallium nitride transistor and clamps the drain electrode voltage to a first voltage; the clamping module receives the first voltage and clamps the first voltage to a second voltage; the energy collection module receives the second voltage and the PWM signal and generates a power supply voltage and a stable voltage. The clamping and logic driving module receives a power supply voltage and a PWM signal and generates a pull-down driving signal. The bias voltage generation module receives the stable voltage and the pull-down driving signal and outputs a bias voltage. When the PWM signal is at a high level, the pull-down driving signal is at a low level, the bias voltage is at a high level, and the driving voltage is at a high level; when the PWM signal is at a low level, the pull-down driving signal is at a high level, the bias voltage is at a low level, and the driving voltage is at a low level.

A test apparatus includes an input terminal, a first multiplexer, a plurality of first elements connected in series between the input terminal and the first multiplexer, and a processor. The first multiplexer is connected to each of a plurality of nodes between the plurality of first elements, and the processor is connected to the input terminal and to the first multiplexer. The processor inputs data to the plurality of first elements through the input terminal. The plurality of first elements outputs at least a portion of a plurality of pieces of data through the plurality of nodes between the elements to the first multiplexer. The processor may thereby determine whether a defect has occurred in any of the plurality of first elements by comparing data, output from the multiplexer, with an expected output value.

A detection circuit includes a tunable delay circuit that generates a delayed signal and that receives a supply voltage. The detection circuit includes a control circuit that adjusts a delay provided by the tunable delay circuit to the delayed signal. The detection circuit includes a time-to-digital converter circuit that converts the delay provided by the tunable delay circuit to the delayed signal to a digital code and adjusts the digital code based on changes in the supply voltage. The control circuit causes the tunable delay circuit to maintain the delay provided to the delayed signal constant in response to the digital code reaching an alignment value. The detection circuit may continuously monitor timing margin of a data signal relative to a clock signal and update the digital code in every clock cycle. The detection circuit may be a security sensor that detects changes in the supply voltage.

The invention discloses an embedded special high-frequency low-level control system, which comprises a digital signal processing board card, an ADC / DAC sub-board card and a radio frequency front-end board card, the radio frequency front-end board card comprises two paths of up-conversion channels and six paths of down-conversion channels; the digital signal processing board card comprises an FPGA (Field Programmable Gate Array); wherein the radio frequency front-end board card is used for dividing an input reference line RF signal into four paths of RF reference signals and generating an LO signal; the ADC / DAC sub board card is used for ADC analog-to-digital conversion and DAC digital-to-analog conversion; the main functions of the digital signal processing board card comprise clock distribution of RF reference signals, a motor drive and piezo ceramic drive circuit, a data acquisition and logic control algorithm of an FPGA logic unit PL part, an embedded ARM system of an FPGA processor unit PS part, EPICS-IOC application of a low-level system, network data communication and the like.

The invention provides an infrared detector driving and adjusting circuit, relates to the technical field of infrared detector driving, and constructs an infrared detector adjusting circuit to perform voltage adjustment, temperature judgment, power-on and power-off control and image signal generation on an infrared detector. Calculating an operation performance coefficient of each device, and calculating a device accumulation performance coefficient of each device according to the operation performance coefficient of each device; according to the device accumulation performance coefficient, accumulation adjustment labeling and performance parameter adjustment are carried out, and the infrared detector adjustment circuit has remarkable advantages in the aspect of solving the problems existing in a traditional infrared detector adjustment circuit and has great significance in improving the performance stability and reliability of an infrared detector.

The present disclosure provides DFE-based peaking techniques for high speed transmitters. A circuit for driving a digital-to-analog converter (DAC) includes a serializer configured to combine a plurality of signals into one input signal to drive a forward inverter coupled to a first node having a first impedance in a series configuration and a first capacitance in a shunt configuration. The circuit includes inverter chains coupled in series to transfer the input signal from the first node to a fifth node based on a signal transfer function. The circuit further includes a feedback inverter between a third node and the first node at which a peak in the signal transfer function is added to form a feedback loop having two inverters in the chain. A second feedback inverter may be added between the fifth node and the third node to add a peak in the signal transfer function at the third node.

The invention provides a driving method, a driving circuit of an amplification module and electronic equipment. The method comprises the following steps: when a power tube is conducted, outputting a first conduction current to a grid electrode of the power tube; after the gate-source voltage of the power tube rises to the threshold voltage, the first conduction current is reduced to the second conduction current, so that the reverse recovery current of the body diode corresponding to the power tube is reduced; after the gate-source voltage of the power tube is increased from the threshold voltage to the Miller voltage, the second conduction current is increased to third conduction current until the power tube is completely conducted; and when the power tube is turned off, the grid electrode of the power tube outputs a first turn-off current until the power tube is completely turned off. In the conduction process of the power tube, after the gate source voltage of the power tube rises to the threshold voltage, the first conduction current is reduced to the second conduction current, so that the reverse recovery current of a body diode corresponding to the power tube is reduced, overshoot of the power tube in the conduction process is avoided, and the conduction safety of the power tube is improved.

The invention discloses a chip reset circuit, a server and a mobile terminal, relates to the technical field of chip reset, and provides the chip reset circuit aiming at the problem that the reset of a CPU (Central Processing Unit) chip excessively depends on a CPLD (Complex Programmable Logic Device) chip at present. And a power-on ready signal is output to a backward stage through the time delay module. The post-stage reset control circuit can control whether to reset the CPU chip according to whether the reset trigger signal is received. Otherwise, a reset control signal is output all the time to prohibit the CPU chip from being started, so that the reset control requirement and the power-on time sequence management requirement of the CPU chip are met at the same time. And the circuit is completely realized by a hardware circuit and does not need to depend on complex devices such as a CPLD (Complex Programmable Logic Device), so that the reliability and the stability of the reset control of the CPU chip are greatly improved.

A Y-branch type phase-change all-optical Boolean logic device comprises a waveguide of a Y-branch structure and phase change function units covered over the waveguide. In the logic implementation method, a light pulse having a large power is employed to perform a write operation on the phase change function unit, so that the phase change function unit is heated to generate a crystallization or amorphization phase change, thereby causing a difference in optical properties under two states; the state of the phase change function unit is read by employing a light pulse having a small power, and the state of its phase change material is not changed. By defining input logic signals respectively and defining three operation steps, an operation mode reconfigurable logic can be implemented, and all 16 binary Boolean logic calculations are implemented in a simple structure by means of step-by-step operation.

An electronic circuit includes: a data input port, a timing adjustment circuit configured to receive data from the data input port, first and second logic circuits, a multiplexer, and a data output port. The timing adjustment circuit includes two paths configured to impose first and second delays to generate first and second delayed data. The first and second logic circuits are configured to respectively receive the first and second delayed data and generate first and second logic outputs. The first logic output expands a pulse width corresponding to a first logic value. The second logic output expands a pulse width corresponding to a second logic value. The multiplexer is configured to select, based on an equalization feedback, at least one of the first logic output or the second logic output, to provide the multiplexer output. The data output port is configured to output equalized data based on the multiplexer output.

Voltage regulator circuitry is provided that includes a pass transistor, an error amplifier for regulating the pass transistor, a high rail switch coupled between a first power supply line and the pass transistor, a big low rail switch coupled between a second power supply line and the pass transistor, a small low rail switch coupled between the second power supply line and the pass transistor, and a comparator for monitor a current flowing through or a voltage across the small low rail switch. The small low rail switch, the comparator, and a gating logic can be coupled in an analog feedback loop. The voltage regulator circuitry can include a sequencer for controlling the high rail switch, the big low rail switch, and the gating logic to perform fast seamless transitions between a low voltage rail mode and a high voltage rail mode without incurring large current glitches.

A phase locked loop (PLL) includes a phase detector configured to receive a reference signal and a feedback signal, wherein the reference signal has a reference frequency, sample the feedback signal, and output a phase detection signal indicative of a phase of the feedback signal. A voltage controlled oscillator is configured to generate an output signal based on the phase detection signal. The output signal has an output frequency greater than the reference frequency. Feedback circuitry is configured to detect a signal edge of the output signal and selectively supply, once per cycle of the reference signal, the detected signal edge of the output signal as the feedback signal.

The invention discloses a clock control device and method, a controller and a system-on-chip, and the device comprises the steps: delaying a first preset clock to stop inputting a digital clock signal to a digital logic device based on an analog clock signal inputted by an analog clock generation device when a low-power-consumption request signal issued by the digital logic device is received; delaying the second preset clock to close the analog clock signal output by the analog clock generation device; when a wake-up input signal input by an external wake-up source is received, after a first preset clock is delayed to input a high-level digital clock gating signal to a digital clock gating unit in the clock control device, a third preset clock is delayed to control the analog clock generation device to output an analog clock signal; the digital clock gating unit inputs a digital clock signal to the digital logic device based on the high-level digital clock gating signal and the analog clock signal. The device can completely avoid burrs generated when clock signals are turned on and turned off.

Techniques described herein may relate to providing a programmable interconnect network (e.g., a programmable network-on-chip (NOC)). A method may include determining a transmission parameter, bonding one or more channels of an interconnect network based at least in part on the transmission parameter, and power-gating any unused channels after the bonding.

A method and system for controlling a power supply rail. The method includes adjusting a power supply rail for circuit component(s) to a first setting. The method includes determining voltage sample(s) by sampling an input voltage corresponding to an input signal. The method also includes determining whether the voltage sample(s) breach a first or second voltage threshold. Additionally, the method includes adjusting the power supply rail to a second setting if a predetermined quantity of the voltage sample(s) breach the first voltage threshold, wherein a magnitude of the second setting equals or is greater than a magnitude of the first setting; and adjusting the power supply rail to a third setting if the voltage sample(s) are captured during at least a threshold amount of time and do not breach the second voltage threshold. The magnitude of the first setting is greater than a magnitude of the third setting.

Methods and systems for performing a surface code error detection cycle. In one aspect, a method includes initializing and applying Hadamard gates to multiple measurement qubits; performing entangling operations on a first set of paired qubits, wherein each pair comprises a measurement qubit coupled to a neighboring data qubit in a first direction; performing entangling operations on a second set of paired qubits, wherein each pair comprises a measurement qubit coupled to a neighboring data qubit in a second or third direction, the second and third direction being perpendicular to the first direction, the second direction being opposite to the third direction; performing entangling operations on a third set of paired qubits, wherein each pair comprises a measurement qubit coupled to a neighboring data qubit in a fourth direction, the fourth direction being opposite to the first direction; applying Hadamard gates to the measurement qubits; and measuring the measurement qubits.

A filter device includes an unbalanced terminal, balanced terminals, and first and second resonant circuits. The first resonant circuit is connected to the unbalanced terminal. The second resonant circuit is connected to the balanced terminals and electromagnetically coupled with the first resonant circuit. The first resonant circuit includes a resonator in which an inductor and a capacitor are connected in parallel between the unbalanced terminal and a reference potential. The second resonant circuit includes a resonator including an inductor connected between the balanced terminals and capacitors connected in series between the balanced terminals.

A computer-implemented method for optimizing telemetry configurations may include enabling, by a computing device, a broadcast multiplexer such that a group of integrated circuits connects to a single channel of an interface controller of the computing device. The method may also include configuring, by the computing device, the group of integrated circuits by simultaneously broadcasting a firmware configuration from the single channel of the interface controller to the group of integrated circuits via the broadcast multiplexer. The method may then include disabling, by the computing device, the broadcast multiplexer such that each integrated circuit in the group of integrated circuits connects to a separate channel of the interface controller. Additionally, the method may include periodically polling, by the computing device, the group of integrated circuits based on a predetermined time interval for each integrated circuit. Various other methods, systems, and computer-readable media are also disclosed.

A field-programmable-gate-array (FPGA) integrated-circuit (IC) chip configured to perform a logic function based on a look-up table (LUT), includes: multiple non-volatile memory cells therein configured to store multiple resulting values of the look-up table (LUT); and a programmable logic block therein having multiple static-random-access-memory (SRAM) cells configured to store the resulting values passed from the non-volatile memory cells, wherein the programmable logic block is configured to select, in accordance with one of the combinations of its inputs, one from the resulting values stored in the static-random-access-memory (SRAM) cells into its output.

Embodiments of the present disclosure include improved logic blocks with combined outputs for programmable logic devices and methods of operating and programming these logic blocks. In an exemplary aspect, a programmable logic device (PLD) is described. In some embodiments, the PLD includes a logic block. The logic block may include a first look-up table (LUT) circuit configured to generate a first output; a second LUT circuit configured to generate a second output; a ripple logic circuit configured to receive the first output and the second output and generate a third output; and a three-to-one multiplexer circuit configured to receive the first output, the second output, and the third output and selectively produce an output of the logic block.