434results about "Logic circuits using elementary logic circuit components" patented technology

The present invention relates to a reconfigurable logic-in-memory cell consisting of triple-gate feedback memory elements. The reconfigurable logic-in-memory cell according to one embodiment of the present invention includes a plurality of triple-gate feedback memory elements including a drain region, a channel region, a source region, and a gate region where first and second programming gate electrodes and a control gate electrode are formed on the channel region.

The present disclosure relates to a universal logic memory block using a plurality of universal logic memory cells. The universal logic memory block according to one embodiment of the present disclosure may implement various combinational logical operations in a single structure by combining logical operation results from a plurality of universal logic memory cells using triple-gate silicon devices driven by a positive feedback loop.

The invention discloses an IO pin multiplexing circuit, a control method, a chip and electronic equipment, and the circuit comprises a gating module which is connected with a chip core and is used for transmitting a first enabling signal and / or a second enabling signal according to an on-chip control signal; the control word coding module is respectively connected with the gating module and the off-chip, and is used for enabling an IO pin to work in a control word coding mode according to the first enable signal; the digital signal input module is respectively connected with the gating module and is used for enabling an IO pin to work in a digital signal input mode according to a second enable signal; and the ESD module is connected with the digital signal input module and the control word coding module and is used for providing electrostatic protection. According to the invention, a pin function multiplexing technology is adopted, a control word writing function can be realized when the chip is just started through an enable signal switching function, a digital signal transmission function can be realized when the chip normally runs, the hardware cost is reduced, and the consumption of pin resources is reduced.

An apparatus, including: a first multiplexer including inputs configured to receive an input data signal and a scan signal, and a select input configured to receive shift control signal; a first latch including an input coupled to an output of the first multiplexer, and a complementary (e.g., inverting) clock input configured to receive a clock signal; a second latch including an input coupled to the output of the first multiplexer, and a non-complementary clock input configured to receive the clock signal; and a second multiplexer including inputs coupled to outputs of the first and second latches, respectively, a select input configured to receive the clock signal, and an output configured to generate an output data or scan signal.

An input / output interface circuit includes a common receiving driver configured to receive a differential clock signal and output a first clock signal corresponding to the differential clock signal and a pair of sub-channels connected to the common receiving driver. Each sub-channel of the pair of sub-channels may be configured to receive the first clock signal and a chip select signal, output a second clock signal through a logical AND operation of the first clock signal and the chip select signal, and output a single clock signal, among the second clock signal and one or more divided clock signals. The single clock signal is used to sample a command address signal.

The invention discloses a single-cluster XNOR logic gate and a signal reading method thereof. One end of a single cluster device is provided with a source electrode and a drain electrode, and the other end of the single cluster device is provided with a gate electrode. A single-cluster XNOR logic gate is placed in a resonance tunneling area for signal reading, and when the input potential difference between a source electrode and a drain electrode of a single-cluster device is 0, the gate electrode outputs a high level; and when the input potential difference between the source electrode and the drain electrode of the single cluster device is not 0, the gate electrode outputs a low level.

A method for providing configuration information for generating physically obfuscated information on a chip with a plurality of circuits, which have a plurality of delay stages, is provided, wherein each delay stage has at least two delay elements, and the method includes determining, for each of the circuits, for each delay stage, which of the delay elements of the delay stage has the least delay among the delay elements of the delay stage, determining configuration information depending on the determined delay elements, which configuration information specifies a configuration of the circuit for each of the circuits, in which the delay elements of different delay stages are connected in series in such a way that at least one path from an input of the circuit to an output of the circuit is formed and storing the determined configuration information.

A circuit for driving digital-to-analog converter (DAC) comprising a serializer (110, 210) configured to combine multiple signals to one input signal to drive a forward inverter (311) coupled to a first node (A) with a first impedance in serial configuration and a first capacitance (C1) in shunt configuration. The circuit includes a chain of inverters (321, 322) coupled in series to transfer the input signal from the first node (A) to the fifth node based on a signal transfer function. The circuit further includes a feedback inverter (425) between the third node and the first node (A) to form a feedback loop with two inverters in the chain, adding peaking in the signal transfer function at the first node (A). A second feedback inverter (425) can be added between the fifth node and the third node to add peaking in the signal transfer function at the third node. The feedback inverter (425) is designed as a current-starved inverter in order to alleviate hot-carrier injection (HCI) aging of the transistors and add programmability in the peaking. The circuit includes a DAC switch coupled to the fifth node.

The invention discloses a gallium nitride driving circuit which is used for generating driving voltage for driving a gallium nitride transistor. The circuit comprises a gallium nitride switching tube, an upper switching tube, a lower switching tube, a clamping module, an energy collection module, a diode, a capacitor, a clamping and logic driving module and a bias voltage generation module. The gallium nitride switch tube is connected with the drain electrode of the gallium nitride transistor and clamps the drain electrode voltage to a first voltage; the clamping module receives the first voltage and clamps the first voltage to a second voltage; the energy collection module receives the second voltage and the PWM signal and generates a power supply voltage and a stable voltage. The clamping and logic driving module receives a power supply voltage and a PWM signal and generates a pull-down driving signal. The bias voltage generation module receives the stable voltage and the pull-down driving signal and outputs a bias voltage. When the PWM signal is at a high level, the pull-down driving signal is at a low level, the bias voltage is at a high level, and the driving voltage is at a high level; when the PWM signal is at a low level, the pull-down driving signal is at a high level, the bias voltage is at a low level, and the driving voltage is at a low level.

The invention discloses an embedded special high-frequency low-level control system, which comprises a digital signal processing board card, an ADC / DAC sub-board card and a radio frequency front-end board card, the radio frequency front-end board card comprises two paths of up-conversion channels and six paths of down-conversion channels; the digital signal processing board card comprises an FPGA (Field Programmable Gate Array); wherein the radio frequency front-end board card is used for dividing an input reference line RF signal into four paths of RF reference signals and generating an LO signal; the ADC / DAC sub board card is used for ADC analog-to-digital conversion and DAC digital-to-analog conversion; the main functions of the digital signal processing board card comprise clock distribution of RF reference signals, a motor drive and piezo ceramic drive circuit, a data acquisition and logic control algorithm of an FPGA logic unit PL part, an embedded ARM system of an FPGA processor unit PS part, EPICS-IOC application of a low-level system, network data communication and the like.

The invention provides an infrared detector driving and adjusting circuit, relates to the technical field of infrared detector driving, and constructs an infrared detector adjusting circuit to perform voltage adjustment, temperature judgment, power-on and power-off control and image signal generation on an infrared detector. Calculating an operation performance coefficient of each device, and calculating a device accumulation performance coefficient of each device according to the operation performance coefficient of each device; according to the device accumulation performance coefficient, accumulation adjustment labeling and performance parameter adjustment are carried out, and the infrared detector adjustment circuit has remarkable advantages in the aspect of solving the problems existing in a traditional infrared detector adjustment circuit and has great significance in improving the performance stability and reliability of an infrared detector.

The present disclosure provides DFE-based peaking techniques for high speed transmitters. A circuit for driving a digital-to-analog converter (DAC) includes a serializer configured to combine a plurality of signals into one input signal to drive a forward inverter coupled to a first node having a first impedance in a series configuration and a first capacitance in a shunt configuration. The circuit includes inverter chains coupled in series to transfer the input signal from the first node to a fifth node based on a signal transfer function. The circuit further includes a feedback inverter between a third node and the first node at which a peak in the signal transfer function is added to form a feedback loop having two inverters in the chain. A second feedback inverter may be added between the fifth node and the third node to add a peak in the signal transfer function at the third node.

The invention discloses a chip reset circuit, a server and a mobile terminal, relates to the technical field of chip reset, and provides the chip reset circuit aiming at the problem that the reset of a CPU (Central Processing Unit) chip excessively depends on a CPLD (Complex Programmable Logic Device) chip at present. And a power-on ready signal is output to a backward stage through the time delay module. The post-stage reset control circuit can control whether to reset the CPU chip according to whether the reset trigger signal is received. Otherwise, a reset control signal is output all the time to prohibit the CPU chip from being started, so that the reset control requirement and the power-on time sequence management requirement of the CPU chip are met at the same time. And the circuit is completely realized by a hardware circuit and does not need to depend on complex devices such as a CPLD (Complex Programmable Logic Device), so that the reliability and the stability of the reset control of the CPU chip are greatly improved.

An electronic circuit includes: a data input port, a timing adjustment circuit configured to receive data from the data input port, first and second logic circuits, a multiplexer, and a data output port. The timing adjustment circuit includes two paths configured to impose first and second delays to generate first and second delayed data. The first and second logic circuits are configured to respectively receive the first and second delayed data and generate first and second logic outputs. The first logic output expands a pulse width corresponding to a first logic value. The second logic output expands a pulse width corresponding to a second logic value. The multiplexer is configured to select, based on an equalization feedback, at least one of the first logic output or the second logic output, to provide the multiplexer output. The data output port is configured to output equalized data based on the multiplexer output.

A method and system for controlling a power supply rail. The method includes adjusting a power supply rail for circuit component(s) to a first setting. The method includes determining voltage sample(s) by sampling an input voltage corresponding to an input signal. The method also includes determining whether the voltage sample(s) breach a first or second voltage threshold. Additionally, the method includes adjusting the power supply rail to a second setting if a predetermined quantity of the voltage sample(s) breach the first voltage threshold, wherein a magnitude of the second setting equals or is greater than a magnitude of the first setting; and adjusting the power supply rail to a third setting if the voltage sample(s) are captured during at least a threshold amount of time and do not breach the second voltage threshold. The magnitude of the first setting is greater than a magnitude of the third setting.

Methods and systems for performing a surface code error detection cycle. In one aspect, a method includes initializing and applying Hadamard gates to multiple measurement qubits; performing entangling operations on a first set of paired qubits, wherein each pair comprises a measurement qubit coupled to a neighboring data qubit in a first direction; performing entangling operations on a second set of paired qubits, wherein each pair comprises a measurement qubit coupled to a neighboring data qubit in a second or third direction, the second and third direction being perpendicular to the first direction, the second direction being opposite to the third direction; performing entangling operations on a third set of paired qubits, wherein each pair comprises a measurement qubit coupled to a neighboring data qubit in a fourth direction, the fourth direction being opposite to the first direction; applying Hadamard gates to the measurement qubits; and measuring the measurement qubits.

A field-programmable-gate-array (FPGA) integrated-circuit (IC) chip configured to perform a logic function based on a look-up table (LUT), includes: multiple non-volatile memory cells therein configured to store multiple resulting values of the look-up table (LUT); and a programmable logic block therein having multiple static-random-access-memory (SRAM) cells configured to store the resulting values passed from the non-volatile memory cells, wherein the programmable logic block is configured to select, in accordance with one of the combinations of its inputs, one from the resulting values stored in the static-random-access-memory (SRAM) cells into its output.

Embodiments of the present disclosure include improved logic blocks with combined outputs for programmable logic devices and methods of operating and programming these logic blocks. In an exemplary aspect, a programmable logic device (PLD) is described. In some embodiments, the PLD includes a logic block. The logic block may include a first look-up table (LUT) circuit configured to generate a first output; a second LUT circuit configured to generate a second output; a ripple logic circuit configured to receive the first output and the second output and generate a third output; and a three-to-one multiplexer circuit configured to receive the first output, the second output, and the third output and selectively produce an output of the logic block.

The invention discloses a level shift circuit, a control method thereof and electronic equipment, and relates to the technical field of integrated circuits. The circuit comprises a logic control module, an AC / DC coupling module and an inverted output module, in the logic control module, a first signal input end is connected with an input signal source, and a second signal input end is connected with an enable signal source; the AC-DC coupling module comprises a DC coupling unit and an AC coupling unit; in the direct current coupling unit, a first control input end is connected with a first control output end, and a second control input end is connected with a second control output end; in the AC coupling unit, an AC coupling input end is connected with a first control output end; the AC coupling output end is connected with the DC coupling output end; the inverted input end of the inverted output module is connected with the DC coupling output end, and the inverted output end is used for outputting a target level shift signal. And a low-delay, high-speed and good-duty-ratio level shifting function can be realized for an alternating current signal and a direct current signal.

A multiplying circuit of an operation stage of a pipeline analog-to-digital converter (ADC) has first and second output terminals and is configured to generate first and second output signals according to first and second input signals. The multiplying circuit includes a voltage conversion circuit, first and second transistors, and first and second current sources. The voltage conversion circuit is configured to generate a first intermediate voltage and a second intermediate voltage according to the first input signal and the second input signal. The first transistor has a first terminal coupled to the first output terminal, a second terminal coupled to a power supply voltage, and a first control terminal receiving the first intermediate voltage. The second transistor has a third terminal coupled to the second output terminal, a fourth terminal coupled to the power supply voltage, and a second control terminal receiving the second intermediate voltage.

A chassis front-end is disclosed. The chassis front-end may include a switchboard including an Ethernet switch, a Baseboard Management Controller, and a mid-plane connector. The chassis front-end may also include a mid-plane including at least one storage device connector and a speed logic to inform at least one storage device of an Ethernet speed of the chassis front-end. The Ethernet speeds may vary.

A method of operating a memory device includes receiving a quadrature clock and performing quadrature error correction of the quadrature clock in a non-sequential scheme, wherein the quadrature clock includes a first clock, a second clock, a third clock, and a fourth clock, having a sequential phase.

To utilize unused or underutilized input and output pins without significantly impacting power consumption and die area, an adaptive logic module (ALM) of a programmable logic device can be implemented with an additional 2LUT to improve low function packing density and broad function mapping coverage. The 2LUT can also serve as a route-through to provide direct access to ALM registers with or without input inversion. The extended ALM can also utilize route-through configurations of the additional 2LUT to enhance the connectivity of the ALM inputs and outputs.

A method includes, during a time period A, in a computer storage element having first and second power inputs separated by an array of transistors, the computer storage element configured to store computer data bits, move an input of the array of transistors, a logic value "1" or "0" to a master latch; during a time period B, recovering at least a portion of the energy containing the input using the first clock; during a time period C, moving the input in the main latch to the isolation stage; recovering at least a portion of the energy containing the input from the isolation stage using a second clock during a time period D; during a time period E, recovering at least a portion of the energy containing the input from the slave latch using a third clock; and moving at least a portion of the input from the isolation stage to the slave latch during the time period F.

Examples described herein generally relate to multi-chip devices having stacked chips. In one example, the multi-chip device comprises a chip stack including chips. Adjacent chips are connected to one another. A plurality of the chips collectively include rows of broken via pillars and bridges. Each chip of the plurality of chips has a broken via pillar in each row. The broken via pillar has first and second continuous via pillar portions aligned in a direction perpendicular to the plane of the semiconductor substrate of the respective chip. The first continuous via pillar portion is not connected to the second continuous via pillar portion within the broken via pillar. Each of the plurality of chips has one or more bridges. Each bridge connects a first continuous via pillar portion in one row to a second continuous via pillar portion in another row within the respective chip.

The invention discloses a domestic FPGA-based complex switch control circuit and method, and the circuit comprises an FPGA minimum system circuit and a peripheral serial-parallel conversion circuit, and the FPGA minimum system circuit is connected with the peripheral serial-parallel conversion circuit. Through complex combinational logic of the multi-channel switch, control can be conveniently carried out, use of devices is reduced, the design cost of the switch is saved, due to the fact that the multi-channel switch is a domestic device, the readability of a manual is high, the function implementation difficulty can be reduced, meanwhile, the multi-channel switch has the advantages of being convenient to operate and high in response speed, and the working efficiency is greatly improved.

The utility model relates to a PD detection alarm protection circuit of a laser. The PD detection alarm protection circuit comprises a PD sensor, a resistance voltage division circuit, an in-phase proportion amplification circuit, a comparator circuit and a voltage reference circuit, the PD sensor collects a PD photocurrent signal of the laser and then sends the PD photocurrent signal to the resistance voltage division circuit; the resistance voltage division circuit converts the PD photocurrent signal into a PD voltage signal and then sends the PD voltage signal to the in-phase proportion amplification circuit; the in-phase proportional amplification circuit amplifies the PD voltage signal and then transmits the PD voltage signal to one input end of the comparator circuit, the other input end of the comparator circuit is connected with the voltage reference circuit, and the output end of the comparator circuit outputs a processed PD signal; by optimizing a pre-stage amplification framework and a post-stage reference design, the detection reliability is remarkably improved while the cost is reduced, and the detection response speed is very high. And real-time monitoring can be realized through an upper computer. The system is especially suitable for a safety protection system of industrial laser equipment.

The invention belongs to the technical field of integrated circuits, and discloses a CML-to-CMOS logic circuit, a chip and electronic equipment. The CML-to-CMOS logic circuit comprises a CML signal-to-CMOS signal module which is used for converting an input CML differential clock into a CMOS differential clock and outputting the CMOS differential clock; and the duty ratio correction module is connected with a common mode node of the CML signal to CMOS signal module and is used for adjusting the common mode voltage of the CML signal to CMOS signal module so as to correct the duty ratio deviation of the CMOS differential clock. The common-mode voltage of the CML signal-to-CMOS signal module is directly adjusted, so that the duty ratio adjustment process is not affected by a CMOS transmission path, and the problem that the duty ratio adjustment power consumption is increased along with the lengthening of the CMOS transmission path is avoided. Therefore, correction of the CMOS differential clock duty ratio deviation is realized with low power consumption.

The invention provides a synchronous time sequence sub-threshold logic circuit optimization method and device, and relates to the technical field of electronics. Converting a basic combinational logic unit in the sub-threshold logic circuit to be optimized into a sensitive amplifier-pass transistor logic circuit to form a first sub-threshold logic circuit; the sub-threshold logic circuit to be optimized is a circuit which is based on a sub-threshold digital standard cell library and is composed of a basic combinational logic unit and a trigger unit. Then determining matching device groups respectively included in a sensitive amplifier and a transmission transistor network in the sensitive amplifier-transmission transistor logic circuit, setting an incidence relation of device size parameters in each matching device group, and optimizing the device size parameters of the sensitive amplifier-transmission transistor logic circuit; and forming a second sub-threshold logic circuit. Thus, signal weakening is reduced, time delay is reduced, the working frequency of the subthreshold logic circuit is improved, and the transmission transistor network is adopted to support circuit units with unfixed logic functions.

A transmitter circuit (1) that receives parallel signals (D(1:4)) and outputs a serial signal (D_Tx) in response to the parallel signals may include; a clock generator (20) generating first clock signals (CK(1:4)) having different respective phases, a multiplexer (10) including selection circuits (11, 12, 13, 14) respectively configured to selectively provide at least two of the parallel signals (D1, D2 or D2, d3 or D3, D4 or D4, D1) to an output node in response to at least two of the first clock signals (Ck1, Ck2 or Ck2, Ck3 or Ck3, Ck4 or Ck4, Ck1), and an output driver (15) generating the serial signal (D_Tx) by amplifying a signal at the output node.