162results about "Logic circuits using elementary logic circuit components" patented technology

Methods and systems for performing a surface code error detection cycle. In one aspect, a method includes initializing and applying Hadamard gates to multiple measurement qubits; performing entangling operations on a first set of paired qubits, wherein each pair comprises a measurement qubit coupled to a neighboring data qubit in a first direction; performing entangling operations on a second set of paired qubits, wherein each pair comprises a measurement qubit coupled to a neighboring data qubit in a second or third direction, the second and third direction being perpendicular to the first direction, the second direction being opposite to the third direction; performing entangling operations on a third set of paired qubits, wherein each pair comprises a measurement qubit coupled to a neighboring data qubit in a fourth direction, the fourth direction being opposite to the first direction; applying Hadamard gates to the measurement qubits; and measuring the measurement qubits.

A chassis front-end is disclosed. The chassis front-end may include a switchboard including an Ethernet switch, a Baseboard Management Controller, and a mid-plane connector. The chassis front-end may also include a mid-plane including at least one storage device connector and a speed logic to inform at least one storage device of an Ethernet speed of the chassis front-end. The Ethernet speeds may vary.

To utilize unused or underutilized input and output pins without significantly impacting power consumption and die area, an adaptive logic module (ALM) of a programmable logic device can be implemented with an additional 2LUT to improve low function packing density and broad function mapping coverage. The 2LUT can also serve as a route-through to provide direct access to ALM registers with or without input inversion. The extended ALM can also utilize route-through configurations of the additional 2LUT to enhance the connectivity of the ALM inputs and outputs.

The utility model relates to a PD detection alarm protection circuit of a laser. The PD detection alarm protection circuit comprises a PD sensor, a resistance voltage division circuit, an in-phase proportion amplification circuit, a comparator circuit and a voltage reference circuit, the PD sensor collects a PD photocurrent signal of the laser and then sends the PD photocurrent signal to the resistance voltage division circuit; the resistance voltage division circuit converts the PD photocurrent signal into a PD voltage signal and then sends the PD voltage signal to the in-phase proportion amplification circuit; the in-phase proportional amplification circuit amplifies the PD voltage signal and then transmits the PD voltage signal to one input end of the comparator circuit, the other input end of the comparator circuit is connected with the voltage reference circuit, and the output end of the comparator circuit outputs a processed PD signal; by optimizing a pre-stage amplification framework and a post-stage reference design, the detection reliability is remarkably improved while the cost is reduced, and the detection response speed is very high. And real-time monitoring can be realized through an upper computer. The system is especially suitable for a safety protection system of industrial laser equipment.

A transmitter circuit (1) that receives parallel signals (D(1:4)) and outputs a serial signal (D_Tx) in response to the parallel signals may include; a clock generator (20) generating first clock signals (CK(1:4)) having different respective phases, a multiplexer (10) including selection circuits (11, 12, 13, 14) respectively configured to selectively provide at least two of the parallel signals (D1, D2 or D2, d3 or D3, D4 or D4, D1) to an output node in response to at least two of the first clock signals (Ck1, Ck2 or Ck2, Ck3 or Ck3, Ck4 or Ck4, Ck1), and an output driver (15) generating the serial signal (D_Tx) by amplifying a signal at the output node.

Integrated circuit devices and circuitry for digital filtering are provided. An integrated circuit device may include a first digital signal processing (DSP) block with first hardened arithmetic circuitry and an output register to store an output of the first DSP block and a second DSP block with second hardened arithmetic circuitry and an input register to receive the output of the first DSP block. An input signal chain may include a first set of registers to provide first input data signals to the first DSP block, a second set of registers to provide second input data signals to the second DSP block, and a third set of registers connected between the first set of registers and the second set of registers to provide delay equal to that of the output register of the first DSP block and the input register of the second DSP block.

A chip package used as a logic drive, includes: multiple semiconductor chips, a polymer layer horizontally between the semiconductor chips; multiple metal layers over the semiconductor chips and polymer layer, wherein the metal layers are connected to the semiconductor chips and extend across edges of the semiconductor chips, wherein one of the metal layers has a thickness between 0.5 and 5 micrometers and a trace width between 0.5 and 5 micrometers; multiple dielectric layers each between neighboring two of the metal layers and over the semiconductor chips and polymer layer, wherein the dielectric layers extend across the edges of the semiconductor chips, wherein one of the dielectric layers has a thickness between 0.5 and 5 micrometers; and multiple metal bumps on a top one of the metal layers, wherein one of the semiconductor chips is a FPGA IC chip, and another one of the semiconductor chips is a NVMIC chip.

Electronic control device, comprising: a logic circuit (255) capable of reconfiguring a plurality of arithmetic circuits, including a first circuit and a second circuit; a reconfiguration controller (204) that reconfigures the arithmetic circuits based on reconfiguration commands and verifies the reconfigured arithmetic circuits; and a process controller (202) that sends the reconfiguration commands to the reconfiguration controller (204) and commands the arithmetic circuits to perform operations, wherein the reconfiguration controller (204) reconfigures and verifies the first circuit when a first reconfiguration command is received, The process controller (202) of the first circuit commands to perform an operation when the verification of the first circuit by the reconfiguration controller (204) is complete. After the first circuit has been reconfigured, the process controller (202) sends a second reconfiguration command to the reconfiguration controller (204) and orders the reconfiguration controller (204) to start the reconfiguration of the second circuit until the first circuit has completed its operation.

An electronic circuit includes: a data input port, a timing adjustment circuit configured to receive data from the data input port, first and second logic circuits, a multiplexer, and a data output port. The timing adjustment circuit includes two paths configured to impose first and second delays to generate first and second delayed data. The first and second logic circuits are configured to respectively receive the first and second delayed data and generate first and second logic outputs. The first logic output expands a pulse width corresponding to a first logic value. The second logic output expands a pulse width corresponding to a second logic value. The multiplexer is configured to select, based on an equalization feedback, at least one of the first logic output or the second logic output, to provide the multiplexer output. The data output port is configured to output equalized data based on the multiplexer output.

Embodiments of the present application provide a driving circuit, an electronic product, a control method, a medium and equipment. The driving circuit comprises a boosting unit, a logic unit and an output unit. The boosting unit is configured to perform boosting processing on a received input waveform to output a boosted waveform; the input end of the logic unit is connected to the input end of the boosting unit, and the logic unit is configured to output a logic signal according to the received input waveform; and the input end of the output unit is connected to the output end of the boosting unit, and the output unit is configured to receive the boosted waveform and control the output of the boosted waveform according to the logic signal output by the logic unit. Therefore, the technical effects of precise output with high voltage and high stability, wide output range and small volume of the driving circuit can be achieved.

A wearable sensor device includes a liquid metal wire that includes an elongated tube with an internal cavity having a uniform cross-sectional geometry, the internal cavity is at least partially filled with liquid metal. The wearable sensor device further includes detection circuitry to detect a change in an electrical attribute of the liquid metal wire based on a temporary change in the cross-sectional geometry, and generate sensor data to identify an event associated with a wearer of the wearable device based on the temporary change in the cross-sectional geometry.

The disclosure provides a detection system based on proximity switches and a vehicle sampling device, wherein the detection system comprises a plurality of proximity switches, a power module and a control module; the proximity switch comprises a first power supply end, a second power supply end and a signal output end; the power module comprises a first power supply line and a second power supply line with opposite polarities; the signal output end of the first proximity switch and the first power supply end of the second proximity switch in adjacent proximity switches are connected, the first power supply line is connected with the first power supply end of the first proximity switch in all proximity switches, the second power supply line is connected with the second power supply end of each proximity switch, and the signal input end of the control module is connected with the signal output end of the last proximity switch in all proximity switches. In the detection system based on proximity switches and the vehicle sampling device, the ''and'' logic function of the plurality of proximity switches is realized by using series connection, so that the occupation of multiple channels in the control module and the increase of the preamplifier are avoided.

The invention discloses a time delay circuit which comprises a first selector, a plurality of series-connected time delay units, an NAND gate, a second selector and a plurality of phase inverters, a first data input end of the first selector is connected with a first enable signal, and the first enable signal serves as an input signal of the time delay circuit in an input mode; the delay units are connected with the output end of the first selector, the first input end of the NAND gate is connected to the output end of the last-stage delay unit, the second input end of the NAND gate is connected with a second enable signal, the second enable signal is used for controlling the working mode of the delay circuit, and the selection control end of the second selector is connected to the output end of the NAND gate. The first data input end and the second data input end are connected through the first phase inverter, the output end is connected to the second data input end of the first selector through the second phase inverter, and the third phase inverter is connected to the output end of the second selector and used for outputting an output signal of the time delay circuit. The method is used for testing register establishment time and retention time.

The present disclosure relates to a power domain management circuit and a system on chip. The power domain management circuit includes: an enable unit, configured to generate an enable signal with a first preset level in a case of receiving an isolation set signal, or to generate an enable signal with a second preset level in a case of receiving a reset indication signal; and a clamping unit, electrically connected to the enable unit, and configured to clamp an initial signal transmitted from a first power domain to a second power domain to generate a target signal with a third preset level in a case of receiving the enable signal with the first preset level, or to skip clamping the initial signal to generate a target signal with a level that varies with a level of the initial signal in a case of receiving the enable signal with the second preset level.

A debouncing logic circuit for processing an asynchronous input signal (din) and provide a debounced signal (dout), including a clock edge (ck), a first stage of flip-flops (q0; q1) driven by the clock edge, a multiplexer (MUX1) and coupled to the first stage of flip-flops, a second stage of flip-flops (q2; q3), a counter logic module (cnt) driven by the clock edge, a comparator module, a second multiplexer (MUX2) operable to select between the processed output signal and the debounced signal based on the control signal from the comparator, the internal state being the selected signal and an output stage (q4) driven by the clock edge and configured to provide the debounced signal (dout).

This bidirectional logic element is provided with: a function / inverse function control unit; a forward input unit; a forward information transmission unit; a reverse input unit; a reverse information transmission unit; a bidirectional function operation unit that performs a forward logical operation and also performs a reverse operation; a forward function transfer unit; and an inverse function transfer unit. The arithmetic device and the arithmetic method use the bidirectional logic element.

A solid state switch for railroad equipment having an isolation boundary galvanically isolating a first zone from a second zone, a switch for switching a current in the first zone between a switch input terminal and a switch output terminal, a relay to receive an operating signal indicating whether to switch the switch and at least two channels. Each channel has a switch module in the first zone that includes a switch module input terminal, a switch module output terminal and a semiconductor switch. Each channel has a programmable device in the second zone with an input terminal, a switch driving terminal for driving the switch module, a monitoring terminal for monitoring the switch module, a control connection with a photovoltaic isolator for bridging the isolation boundary, and a monitoring circuit connecting the monitoring terminal to the switch module input terminal and output terminal.

The invention discloses a ferroelectric field effect transistor-based multifunctional logic operation circuit, which comprises a first voltage input end, a second voltage input end, a core operation module and a result output end, and is characterized in that the core operation module consists of two ferroelectric field effect transistors and a reconfigurable switching network; the network comprises at least three controlled switching devices which are connected with the source electrodes and the drain electrodes of the two ferroelectric field effect transistors. The on-off state of the controlled switching device is changed in response to a plurality of control signals, and the core operation module can dynamically change the electrical connection relation between the two ferroelectric field effect transistors, so that the result output end connected to the unique output node generates corresponding voltage to represent different logic operation or data matching results. The NV-TCAM has the advantages that various logical operations such as NOR and IMP and the NV-TCAM function are realized in the same hardware structure through a unified logic output path and hardware-level dynamic reconstruction, the functional diversity and flexibility are remarkably improved, and the complexity and power consumption of a peripheral circuit are reduced.

Methods and systems for performing a surface code error detection cycle. In one aspect, a method includes initializing and applying Hadamard gates to multiple measurement qubits; performing entangling operations on a first set of paired qubits, wherein each pair comprises a measurement qubit coupled to a neighboring data qubit in a first direction; performing entangling operations on a second set of paired qubits, wherein each pair comprises a measurement qubit coupled to a neighboring data qubit in a second or third direction, the second and third direction being perpendicular to the first direction, the second direction being opposite to the third direction; performing entangling operations on a third set of paired qubits, wherein each pair comprises a measurement qubit coupled to a neighboring data qubit in a fourth direction, the fourth direction being opposite to the first direction; applying Hadamard gates to the measurement qubits; and measuring the measurement qubits.

A fine-grained dynamic random-access memory (DRAM) includes a first memory bank, a second memory bank, and a dual mode I / O circuit. The first memory bank includes a memory array divided into a plurality of grains, each grain including a row buffer and input / output (I / O) circuitry. The dual-mode I / O circuit is coupled to the I / O circuitry of each grain in the first memory bank, and operates in a first mode in which commands having a first data width are routed to and fulfilled individually at each grain, and a second mode in which commands having a second data width different from the first data width are fulfilled by at least two of the grains in parallel.

A method including, during time period A, in a computer storage element having first and second power inputs separated by an array of transistors configured for storing a computer bit of data, moving an input of the array of transistors a logic value "1" or "0" a master latch, during time period B, recovering at least a portion of energy comprising the input with a first clock, during a time period C, moving the input in the master latch to an isolation stage, during time period D, recovering at least a portion of energy comprising the input from the isolation stage with a second clock, during time period E, recovering at least a portion of energy comprising the input from a follower latch with a third clock, and during time period F, moving at least a portion of the input from the isolation stage to the follower latch.

A field programmable gate array (FPGA) has a 4-LUT (lookup table) that has four stages of multiplexers. The 4-LUT is fracturable. The 4-LUT being fracturable includes the capability to implement multiple LUTs in an instance of FPGA programming for functions from a group that includes adder functions and further functions. The 4-LUT has outputs exposed to programmable connection in accordance with FPGA programming. Outputs of the 4-LUT include an output of a first multiplexer in the third stage, an output of a multiplexer in the second stage, and an output of a multiplexer in the second or third stage of the 4-LUT

To provide a device for and a method of separating a plurality of tenants in an integrated circuit including a programmable logic circuit, a processor system, and a network-on-chip.SOLUTION: The present invention is directed to a system-on-chip (SoC) 100 having a programmable logic (PL) circuit 104 arranged to operate with a plurality of tenants, a processor system (PS) 106 coupled with the PL circuit 104, and a network-on-chip (NoC) 108 coupled with the PL circuit 104 and the processor system. The PL circuit 104 is equipped with one or more hardware acceleration functions for the plurality of tenants and routes data between a first interface communicating with a host data processing system so as to separate the plurality of tenants and a second interface operating with the plurality of tenants.SELECTED DRAWING: Figure 1

This invention relates to a device for generating truly random numbers, comprising a digital chaotic oscillating autonomous Boolean network as an entropy source. According to the invention, the proposed digital chaotic oscillating autonomous Boolean network comprises three interconnected logic elements, two of which represent two-input XOR gates and / or XNOR gates, while the third logic element has three inputs and one output, and implements a logic "one-to-one counting" function, wherein if a logic 1 appears at no more than one input of the third logic element, the output of the third logic element is set to logic 1; otherwise, the output is set to logic 0. The resulting technical advantages include improved truly random number generation speed while reducing energy consumption.

The application relates to a programmable frequency divider and a phase-locked loop, the programmable frequency divider comprising a plurality of cascaded subtractors, a period end detection module and a delay reset circuit, wherein the plurality of cascaded subtractors are connected to corresponding initial value signals, under the triggering of a clock signal to be divided, the signals output by the plurality of cascaded subtractors correspond to the output results of decrement, and under the condition that the signals output by the plurality of cascaded subtractors reach a period end condition, the period end detection module outputs a period end signal to the delay reset circuit based on the signals output by the plurality of cascaded subtractors and the period end condition. Under the condition that the delay reset circuit receives the period end signal, a reset trigger signal is output to each subtractor so as to reset each subtractor. After a preset delay time length of the delay reset circuit after the reset trigger signal, a work trigger signal is output to each subtractor so as to make each subtractor work and enter the next round of decrement cycle operation.

A signal transmitting device, according to the present invention, for example, transmits a drive signal of a gate drive transistor between a primary circuit system and a secondary circuit system while insulating between the primary circuit system and the secondary circuit system, and comprises: a first external terminal configured to connect a grounding end of the secondary circuit system; a second external terminal configured so that the terminal voltage changes depending on whether the first external terminal is in an open state; and an open detection circuit that monitors the terminal voltage of the second external terminal and detects whether the first external terminal is open.

A field-programmable-gate-array (FPGA) integrated-circuit (IC) chip configured to perform a logic function based on a look-up table (LUT), includes: multiple non-volatile memory cells therein configured to store multiple resulting values of the look-up table (LUT); and a programmable logic block therein having multiple static-random-access-memory (SRAM) cells configured to store the resulting values passed from the non-volatile memory cells, wherein the programmable logic block is configured to select, in accordance with one of the combinations of its inputs, one from the resulting values stored in the static-random-access-memory (SRAM) cells into its output.

Device for performing a similarity assessment for an attention mechanism comprising a capacitor (C1) for storing a key (K), an input for a query (Q), a comparator (Com) for comparing a query (Q) with a key (K) stored in the capacitor (C1), wherein the comparator (Com) outputs an analogous similarity value (S) as a result of the comparison.

The application relates to the technical field of program memories of FPGA processors, and particularly relates to an FPGA program memory cold backup circuit and a program burning method; in the FPGA program memory cold backup circuit: an FPGA processor is connected with a main program memory and a backup program memory through an analog multiplexer; a power supply is connected with the backup program memory through a load switch; a backup enable signal output by a signal isolation circuit controls the load switch and the analog multiplexer; a delay detection circuit is connected with the FPGA processor, detects whether the FPGA processor is loaded, and outputs a result; the result output by the delay detection circuit controls whether a reset control circuit triggers the FPGA processor to perform a reconfiguration operation, and the result is synchronously output to the signal isolation circuit; the signal isolation circuit outputs the backup enable signal based on a program-controlled backup signal or a main abnormal signal output by the FPGA processor. The application has simple circuit structure and low cost.