Logic circuit utilizing pass transistors and logic gate

Abstract

A logic circuit combines a plurality of pass-transistor logic trees and a multiple-input logic gate for receiving intermediate logic signals from the respective pass-transistor logic trees, and can express a complex logical operation while decreasing the number of stages in pass-transistor logic trees and improving operation speed. Even a logical operation that cannot be expressed efficiently by a known or conventional pass-transistor logic circuit can be expressed efficiently with performance higher than that of a known CMOS logic circuit. Furthermore, when a static feedthrough current of the multiple-input logic gate is suppressed, power consumption can be reduced. In some embodiments, since circuitry for suppressing a static feedthrough current of the multiple-input logic gate is arranged so that a probability of occurrence of logical collision with a preceding stage will decrease or will be nil, power consumption can further be reduced.

Description

1. Field of the InventionThe present invention relates to a logic circuit using switching devices, in each of which conduction between an input terminal and output terminal is turned ON or OFF according to a potential at a control terminal, as pass transistors to realize desired logic. In particular, this invention is concerned with a logic circuit capable of realizing complex logic while improving operation speed by decreasing the number of stages of pass transistors required to be connected in series. Furthermore, the present invention relates to a logic circuit capable of realizing logic functions, for which many transistors are needed in conventional pass-transistor logic circuits, using a smaller number of transistors, and having characteristics of high operation speed and small power consumption.2. Description of the Related ArtWhat is referred to as a "pass-transistor logic circuit" that aims to minimize the number of circuit elements or improve operation speed has been sugge...

AI Technical Summary

Problems solved by technology

This poses the problem that it becomes hard to verify the operating timing of a logic circuit.

However, intense restrictions are imposed on such product terms containing a large number of variables.

It is hard to efficiently express various logical operations with them.

In addition, power consumption by the logic circuit in the succeeding stage creases, and a noise margin decreases.

Furthermore, it is a problem that the logical amplitude (difference in potential between HIGH and LOW states) of an output logic signal decreases.

However, when the pull-up or pull-down is thus carried out, the problem arises that load capacitance relative to a logic circuit in a preceding stage becomes larger, signal delay is extended, and power consumption and chip area increase.

The inventor has recognized a problem that the number of required switching devices in conventional pass-transistor logic circuits can become larger than that of ordinary CMOS logic circuits, depending on the logical operation to be realized.

Consequently, power consumption increases.

However, it is not mandatory to restore the potentials to the power supply potential or reference potential.

However, the inventors have recognized that the mere employment of the method poses a problem that current consumption increases, because of logical collision between the pull-up circuit and a logic circuit in the preceding stage.

Since the dimension of the P-channel MOS transistor is thus smaller, an increase in area of a semiconductor integrated circuit chip due to the addition of the P-channel MOS transistors as the means for restoring is limited.

Moreover, the smaller dimension of the P channel MOS transistors limits the increase in a load capacitance for a logic circuit in the preceding stage.

Therefore, the degradation in the operation speed is also limited.

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