Method for manufacturing double-layer metal-insulator-metal capacitor by using copper damascene process

A double-layer metal and metal capacitor technology, which is applied in semiconductor/solid-state device manufacturing, circuits, electrical components, etc., can solve problems such as incomplete compatibility, and achieve the effect of improving capacitor performance and increasing capacitor density

Active Publication Date: 2012-04-18
SHANGHAI HUALI MICROELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the current multi-layer metal-insulator-metal capacitor process is not fully compatible with the copper damascene process of complementary metal oxide semiconductor logic circuits and inductors.

Method used

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  • Method for manufacturing double-layer metal-insulator-metal capacitor by using copper damascene process
  • Method for manufacturing double-layer metal-insulator-metal capacitor by using copper damascene process
  • Method for manufacturing double-layer metal-insulator-metal capacitor by using copper damascene process

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Embodiment （ 1

[0035] figure 1 It is a schematic diagram of the structure of a method for manufacturing a double-layer metal-insulating layer-metal capacitor using a copper damascene process in the present invention, as figure 1 As shown, the double-layer metal-insulator-metal (Metal-Insulator-Metal, referred to as MIM) capacitor includes a structure of three layers of metal electrodes and two layers of intermetallic insulating layers, showing the use of copper damascene process in the base dielectric layer 4 Form the first metal electrode groove 19 and the metal interconnection groove 21, and deposit metal in the first metal electrode groove 19 and the metal interconnection groove 21 to make the first metal electrode 1 and the metal interconnection at the same time line 7; deposit the first dielectric barrier layer 9 to cover the base dielectric layer 4, the first metal electrode 1 and the metal interconnection line 7, and then deposit the first dielectric layer 5 to the first dielectric ba...

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Abstract

The invention discloses a method for manufacturing a double-layer metal-insulator-metal capacitor by using a copper damascene process. In the method, a double-layer MIM (Metal-Insulator-Metal) capacitor structure and the copper damascene manufacturing process are used, and the method can be completely compatible with the copper damascene process of a CMOS (Complementary Metal-Oxide-Semiconductor Transistor) logic circuit and an inductor, and can be used for increasing the capacitance density of an MIM. According to the double-layer metal-insulator-metal capacitor manufactured by using the copper damascene process, disclosed by the invention, the method is completely compatible with the copper damascene process of the CMOS logic circuit and the inductor while the density of the MIM capacitor is increased.

Description

technical field [0001] The invention relates to a copper damascene manufacturing process, in particular to a method for manufacturing a double-layer metal-insulating layer-metal capacitor by utilizing the copper damascene process. Background technique [0002] With the rapid development of the microelectronics industry, the feature size of semiconductor devices is required to be reduced. At present, the semiconductor back-end copper process replaces the aluminum process and becomes the mainstream process. In mixed-signal and RF circuits, it is necessary to develop a metal-insulator-metal capacitor structure and manufacturing process that is fully compatible with CMOS logic circuits and copper damascene processes for inductors. This not only improves the complexity of the process; but also uses low-resistance copper as the electrode plate to improve the metal-insulator-metal capacitance performance. [0003] Patent US6329234, making a single-layer Damascus metal-insulating l...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/02H01L21/768
Inventor 李磊胡友存陈玉文姬峰张亮
Owner SHANGHAI HUALI MICROELECTRONICS CORP
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