16 results about "Cmos logic circuits" patented technology

The invention belongs to the technical field of integrated circuits, and discloses a CML-to-CMOS logic circuit, a chip and electronic equipment. The CML-to-CMOS logic circuit comprises a CML signal-to-CMOS signal module which is used for converting an input CML differential clock into a CMOS differential clock and outputting the CMOS differential clock; and the duty ratio correction module is connected with a common mode node of the CML signal to CMOS signal module and is used for adjusting the common mode voltage of the CML signal to CMOS signal module so as to correct the duty ratio deviation of the CMOS differential clock. The common-mode voltage of the CML signal-to-CMOS signal module is directly adjusted, so that the duty ratio adjustment process is not affected by a CMOS transmission path, and the problem that the duty ratio adjustment power consumption is increased along with the lengthening of the CMOS transmission path is avoided. Therefore, correction of the CMOS differential clock duty ratio deviation is realized with low power consumption.

The invention relates to an embedded low-voltage nano-gate ferroelectric transistor structure and a preparation method thereof, and relates to the field of memory devices, the embedded low-voltage nano-gate ferroelectric transistor structure comprises a silicon-based CMOS logic circuit, the silicon-based CMOS logic circuit is provided with a first insulating dielectric layer and a plurality of horizontally arranged nano-gate ferroelectric transistors, a second insulating medium layer is arranged between every two adjacent nano-gate ferroelectric transistors; the nanometer gate ferroelectric transistor comprises a gate metal interconnection, a third insulating dielectric layer, a ferroelectric layer, a metal floating gate, a gate dielectric layer, a channel material layer and a source and drain electrode which are arranged from bottom to top, and the bottom of the gate metal interconnection is connected with the silicon-based CMOS logic circuit through a connecting line penetrating through the first insulating dielectric layer; metal nano-gates are vertically arranged on the two sides of the gate metal interconnection and the third insulating dielectric layer, the tops of the metal nano-gates are in contact with the ferroelectric layer, and side walls are arranged between the metal nano-gates and the second insulating dielectric layer. According to the invention, ultra-low power consumption edge computing application can be met, and storage and computing integrated operation is supported.

The present invention relates to a TFT CMOS logic circuit comprising a mixture of two semiconductor materials: carbon nanotubes (CNTs) and zinc oxide (ZnO), and a method for fabricating the same. The CMOS circuit structure comprises an equal number of PMOS and NMOS transistors. The CMOS is fabricated using planar thin-film growth and patterning techniques. The PMOS active layer is CNT, and the NMOS active layer is ZnO. The PMOS source and drain electrodes are gold, and the gate is ITO. The three NMOS electrodes are all ITO, and the gate oxide layers of both the PMOS and NMOS are Al2O3. The TFT CMOS logic circuit of the present invention can be used to fabricate small and medium-sized integrated circuits. The hybrid material CMOS logic circuit of the present invention has low cost, simple fabrication, and excellent electrical performance. Compared to conventional enhancement-mode, depletion-mode, and pseudo-CMOS transistors, it offers advantages such as low power consumption, high noise tolerance, high gain, simple structure, and high integration.

The application discloses a high-speed, high-durability and low-fluctuation FeFET and a preparation method thereof, and belongs to the technical field of semiconductors. The application first forms multiple grooves by etching a high-k gate dielectric, then grows ferroelectric HZO in the grooves, and finally prepares a FeFET gate stack by chemical mechanical polishing to a specific size and annealing. The ferroelectric HZO monophase grown in each groove is high, even close to single crystal, the polarization orientation and polarization flip consistency are very high, which is conducive to improving the read-write speed of the FeFET and reducing the fluctuation between devices, and the oxide semiconductor is used as a channel, so that the existence of an interface layer can be eliminated, and the retention characteristics and durability characteristics of the FeFET are improved. The preparation process is completely compatible with the CMOS back-end process, and is expected to be mixed and integrated with a CMOS logic circuit.

A processing core includes a multi-core processor directly integrated with high-bandwidth, high-capacity memory. The processor may be, for example, a large graphics processing unit (GPU) or an artificial intelligence (AI) processor. The memory may include non-volatile memory and volatile memory. The non-volatile memory may include a CMOS bonded-to-array (CBA) memory tile, which includes a single large NAND memory tile coupled to a CMOS logic circuit tile. The volatile memory may include one or more DRAM memory tiles or the like. The processing core may further include stacks of high-bandwidth memory (HBM) semiconductor die attached to the interposer around one or more sides of the processor, the one or more volatile memory tiles, and the CBA memory tile.

The utility model discloses a switching device and a testing system, and mainly relates to the technical field of memory card testing, the switching device is used for connecting a memory card and a host device, the switching device comprises a circuit main board, the circuit main board is provided with a host interface, a CMOS logic circuit module, a state display module, a memory card interface and a reset module, the CMOS logic circuit module is connected with the host interface, the host interface is used for being connected with a host device, the memory card interface is connected with the CMOS logic circuit module, the memory card interface is used for being connected with a memory card, and the state display module is connected with the CMOS logic circuit module. The reset module is connected with the memory card interface; the CMOS logic circuit module is used for monitoring the test state of the memory card, the state display module is used for displaying the test state of the memory card, and the reset module is used for resetting the state of the memory card. Through the design, the card opening convenience of the memory card is improved.

A semiconductor device includes one or more paired CMOS bonded array (CBA) dies. Each paired CBA memory die includes first and second CBA memory dies. Each CBA memory die includes a first semiconductor die having a memory array formed in a silicon substrate and a second semiconductor die having CMOS logic circuits formed in a silicon substrate. The paired CBA memory dies may be affixed to each other face-to-face; that is, with their active surfaces facing each other. In such a configuration, the disparate coefficients of thermal expansion of the device layers and silicon substrate balance each other to prevent warping of the paired CBA memory die.

The invention discloses a logic unit based on a gallium oxide NMOS (N-channel Metal Oxide Semiconductor) field effect transistor. The logic unit comprises a pull-up structure and a pull-down network, the pull-up structure is composed of a gate-drain short circuit or gate-source short circuit gallium oxide NMOS transistor, and the pull-up structure is used for providing a potential pull-up function at an output end and pulling up an output signal to a high level; the pull-down network is formed by connecting at least one gallium oxide NMOS transistor according to a target logic function and a CMOS logic circuit design standard, and the pull-down network is used for providing a potential pull-down function at an output end and pulling down an output signal to a low level GND. The method does not need heterogeneous integration, and has the characteristics of low process difficulty, low cost, strong anti-interference capability and capability of supporting complete logic function realization.

A processing core includes a multi-core processor integrated directly onto a high bandwidth, high-capacity memory. The processor may for example be a large graphics processing unit (GPU) or artificial intelligence (AI) processor. The memory may include a non-volatile memory and a volatile memory. The non-volatile memory may comprise a CBA (CMOS bonded to array) memory tile having a single large NAND memory tile coupled together with a CMOS logic circuit tile. The volatile memory may comprise one or more DRAM memory tiles or the like. The processing core may further include stacks of high bandwidth memory (HBM) semiconductor dies affixed to the interposer around one or more sides of the processor, the one or more volatile memory tiles and CBA memory tile.

A processing core includes a multi-core processor integrated directly onto a high bandwidth, high capacity memory. The processor can be, for example, a large graphics processing unit (GPU) or artificial intelligence (AI) processor. The memory can include a non-volatile memory and a volatile memory. In one embodiment, a non-volatile memory can include a CBA (CMOS bonded to an array) memory die having a single large NAND memory die coupled with a CMOS logic circuit die. The volatile memory can include one or more DRAM memory slices, etc. The processing core can also include a high bandwidth memory (HBM) semiconductor die stack attached to the interposer around one or more sides of the processor, the one or more volatile memory tiles, and the CBA memory tiles.

A processing core includes a multi-core processor integrated directly onto a high bandwidth, high-capacity non-volatile memory. The processor may for example be a large graphics processing unit (GPU) or artificial intelligence (AI) processor. The non-volatile memory may comprise a CBA (CMOS bonded to array) memory tile having a single large NAND memory tile coupled together with a CMOS logic circuit tile. The integrated processor and CBA memory tile may be affixed to an interposer. The processing core may further include stacks of high bandwidth memory (HBM) semiconductor dies affixed to the interposer around one or more sides of the processor and CBA memory tile.

A magnetic random access memory (MRAM) stores information by utilizing spinning of electrons, does not need standby energy consumption, and is the most powerful candidate of a memory which replaces an SRAM and a DRAM to be applied on a large scale at present. A storage unit of the MRAM has radiation resistance, but the storage unit needs a CMOS (complementary metal oxide semiconductor) logic circuit to perform operations such as information reading and writing, so that the risk of being influenced by radiation still exists. The invention provides an anti-irradiation circuit for a magnetic random access memory (MRAM) chip, which improves the resistance to two main irradiation influences, that is, the resistance to single event upset and double-node upset is improved.

An integrated circuit (IC) (400) including a flash memory and CMOS logic circuitry and a method of manufacturing the same are disclosed. The IC (400) includes: a substrate including a first region (403A / C) and a second region (403B), with a flash memory cell gate stack (485-1) formed in the first region (403A / C); a first transistor (491) formed in the first region (403A / C) and operable at a first voltage level, the first transistor (491) including a gate (489) formed over a first gate oxide layer (486) in which nitridation does not occur; and one or more sets of second transistors (471A / B) formed in the second region (403B), each set of second transistors (471A / B) operable at a corresponding second voltage level different from the first voltage level and including a nitrided corresponding second gate oxide layer (450).

An integrated circuit (IC) (400) including a flash memory and CMOS logic circuitry and a method of manufacturing the same are disclosed. The IC (400) comprises: a substrate (402) comprising a recessed region (407) of a first region (403A); a flash memory cell gate stack (485-1) formed in the recessed region (407); a word line (WL) transistor formed in the recessed region (407) and coupled with the flash memory cell gate stack (485-1), the WL transistor including a WL gate (444-1) formed over a first gate oxide layer (437) that does not include nitridation; and a transistor (471 A / B) formed in a second region (403B) of the substrate (402) separated from the recessed region (407), the transistor (471 A / B) forming at least a portion of logic circuitry of the IC (400) and including a second gate oxide layer (450) having nitridation.

A processing core includes a multi-core processor integrated directly onto a high bandwidth, high-capacity non-volatile memory. The processor may for example be a large graphics processing unit (GPU) or artificial intelligence (AI) processor. The non-volatile memory may comprise a CBA (CMOS bonded to array) memory tile having a single large NAND memory tile coupled together with a CMOS logic circuit tile. The integrated processor and CBA memory tile may be affixed to an interposer. The processing core may further include stacks of high bandwidth memory (HBM) semiconductor dies affixed to the interposer around one or more sides of the processor and CBA memory tile.

This invention provides a P-channel SiC MOSFET device and its fabrication method. The P-channel SiC MOSFET device includes a substrate, an N-type SiC epitaxial layer, a gate, a P-Well region, a P+ region, an N-type graphene layer, a source, and a drain. The N-type SiC epitaxial layer is disposed on the substrate. The gate is disposed on the N-type SiC epitaxial layer. The P-Well region is disposed within the N-type SiC epitaxial layer and located on both sides of the gate. The P+ region is disposed within the P-Well region and located on both sides of the gate, with the P+ region located on the side of the P-Well region away from the substrate. The N-type graphene layer is disposed between the gate and the N-type SiC epitaxial layer and connects to the P+ region. The source is disposed on the N-type SiC epitaxial layer and located on one side of the gate, with the source above the P+ region. The drain is disposed on the N-type SiC epitaxial layer and located on the other side of the gate, with the drain above the P+ region. This invention can improve the hole mobility of P-channel SiC MOSFET devices, thereby matching them with N-channel SiC MOSFET devices with high electron mobility for use in SiC CMOS logic circuits.