66 results about "Cmos logic circuits" patented technology

A logic circuit combines a plurality of pass-transistor logic trees and a multiple-input logic gate for receiving intermediate logic signals from the respective pass-transistor logic trees, and can express a complex logical operation while decreasing the number of stages in pass-transistor logic trees and improving operation speed. Even a logical operation that cannot be expressed efficiently by a known or conventional pass-transistor logic circuit can be expressed efficiently with performance higher than that of a known CMOS logic circuit. Furthermore, when a static feedthrough current of the multiple-input logic gate is suppressed, power consumption can be reduced. In some embodiments, since circuitry for suppressing a static feedthrough current of the multiple-input logic gate is arranged so that a probability of occurrence of logical collision with a preceding stage will decrease or will be nil, power consumption can further be reduced.

A novel RF buffer circuit adapted for use with an RF switch circuit and method for switching RF signals is described. The RF switch circuit is fabricated in a silicon-on-insulator (SOI) technology. The RF switch includes pairs of switching and shunting transistor groupings used to alternatively couple RF input signals to a common RF node. The switching and shunting transistor grouping pairs are controlled by a switching control voltage (SW) and its inverse (SW_). The switching and shunting transistor groupings comprise one or more MOSFET transistors connected together in a “stacked” or serial configuration. The stacking of transistor grouping devices, and associated gate resistors, increase the breakdown voltage across the series connected switch transistors and operate to improve RF switch compression. A fully integrated RF switch is described including digital control logic and a negative voltage generator integrated together with the RF switch elements. In one embodiment, the fully integrated RF switch includes a built-in oscillator, a charge pump circuit, CMOS logic circuitry, level-shifting and voltage divider circuits, and an RF buffer circuit. Several embodiments of the charge pump, level shifting, voltage divider, and RF buffer circuits are described. The inventive RF switch provides improvements in insertion loss, switch isolation, and switch compression.

A CMOS logical circuit comprises two electric current paths each of which has circuits consisting of n-type and p-type transistors. In a circuit consisting of n-type or p-type transistors, one electric current path is provided with a circuit having the same construction as that of a circuit having an n-type transistor of a CMOS logical circuit outputting a logical operation result similar to that of this logical circuit, and the other electric current path is provided with a circuit having the same construction as that of a circuit having a p-type transistor of the CMOS logical circuit outputting a logical operation result similar to that of this logical circuit. In another circuit consisting of the other channel type, a gate electrode of the transistor provided on the one electric current path and that of the transistor provided on the other electric current path are connected to drain electrodes of the counterparts. According to the construction, the amplitude of an input signal can be made smaller than a supply voltage of the logical circuit.

Circuit for detecting error transients in logic circuits due to atomic events or other non-recurring noise sources includes a first circuit coupled to a data line for sensing a first signal on the data line at a first point in time (T1) and a second circuit coupled to the data line for sensing the first signal on the data line at a second point in time (T2) such that a time difference between T1 and T2 is small enough so that the first signal is still present on the data line in the absence of a perturbation event and such that the time difference between T1 and T2 is large enough so that any such perturbation event is resolved. A compare circuit coupled to the first and second circuits compares the sensing of the first signal by the first and second circuits, and generates an error signal in response to a non-compare.

A content-addressable memory (CAM) comprises a first CAM cell and a second CAM cell. The first CAM cell stores a first data bit, and compares the first data bit with a first search bit to determine if they are matched. The second CAM cell stores a second data bit, and compares the second data bit with a second search bit to determine if they are matched. The first CAM cell comprises a first logic circuit, the second CAM cell comprises a second logic circuit, and the first logic circuit and the second logic circuit form a static CMOS logic circuit.

An electrical wiring structure capable of improving a wiring delay to thereby achieve both low power consumption and high-speed performances without accompanying any significant changes in circuit layout and wiring structure of prior known CMOS logic circuitry and also alterations of the multilayer configuration of wiring layers is provided. A local wiring 1 and global wirings 2, 3 are stacked over a semiconductor substrate 10 in this order of sequence when looked at from lower part in a lamination direction, with dielectric layers sandwiched between adjacent ones of these layers. A distance between the local wiring 1 and the global wiring 2 is so formed as to be greater than a distance between the global wiring layer 2 and the global wiring, 3. Thus provided is a semiconductor device featured in that a drive voltage used to drive the global wirings 2, 3 is potentially lower than a drive voltage for driving inside of the local wiring 1.

A novel RF switch circuit and method for switching RF signals is described. The RF switch circuit is fabricated in a silicon-on-insulator (SOI) technology. The RF switch includes pairs of switching and shunting transistor groupings used to alternatively couple RF input signals to a common RF node. A fully integrated RF switch is described including digital control logic and a negative voltage generator integrated together with the RF switch elements. In one embodiment, the fully integrated RF switch includes a built-in oscillator, a charge pump circuit, CMOS logic circuitry, level-shifting and voltage divider circuits, and an RF buffer circuit. Several embodiments of the charge pump, level shifting, voltage divider, and RF buffer circuits are described. The RF switch provides improvements in insertion loss, switch isolation, and switch compression. An improved voltage reducing circuit is described. The improved voltage reducing circuit limits voltages applied to selected nodes within the integrated circuit.

A semiconductor integrated circuit apparatus and an electronic apparatus having a power control function configured from power control MOS transistors in such a manner that leakage current and on resistance at the time of cut-off is sufficiently small in actual use. Semiconductor integrated circuit apparatus is comprised of a CMOS logic circuit, a second pseudo power supply line connected to a low potential side power supply terminal of the CMOS logic circuit, and a power control NchMOS transistor connected across a second pseudo power supply line and a low potential side power supply line, with the substrate and gate of power control NchMOS transistor being electrically connected. The gate and the substrate may also, for example, be connected via a current limiter utilizing, for example, a source follower of a depletion type NchMOS transistor.

The invention relates to a single-phase power clock trigger based on charge recovering. The trigger comprises an input inverter used for generating two inverse signals and sending the two signals to a charge recovery unit, a cross-coupling charge recovery unit used for reducing the power consumption of a circuit, and a RS trigger used for latching the output of a charge recycling unit, wherein, the input and the output of the inverter are connected with two input terminals of the cross-coupling charge recovery unit respectively; and two output terminals of the cross-coupling charge recovery unit are connected with two input terminals of the RS trigger. The trigger adopts the single phase power clock (similar to a sine wave power) Pclk to complete the function of the trigger D, input and output signals adopt the square wave and can be directly cascaded with a traditional CMOS logic circuit to complete the logic. Compared with a traditional trigger, the trigger of the invention has the advantages that the power consumption is low, and the extremely low power consumption can be realized particularly when the data change rate is low; the number of transistors is small; and the single-phase clock is adopted.

A hybrid CMOL stack enables more efficient design of CMOS logical circuits. The hybrid CMOL structure includes a first substrate having a CMOS device layer on the substrate, a first interconnect layer with interface pins over the CMOS device layer of the first substrate, a first array of nanowires connected to the interface pins of the first interconnect layer, a layer of nanowire junction material over the first array of nanowires, a second array of nanowires over the nanowire junction material, a second interconnect layer having interface pins disposed over the second array of nanowires, the interface pins being connected to the second array of nanowires, and a second substrate, the second substrate including a second CMOS device layer disposed over the second interconnect layer.

The invention relates to a micro-power-consumption tipping bucket type rainfall pulse signal collecting device and method. The device comprises a first attendant circuit, a second attendant circuit, a working circuit, an attendant power source and a working power source. The first attendant circuit and the second attendant circuit are CMOS logic circuits of the micro-power-consumption design, the working current of each attendant circuit is in microampere level, and the working power source has the switch-on state and the switch-off state, and is in the switch-off state when it does not rain. The first attendant circuit locks and stores a pulse signal of a dipping bucket type rainfall sensor when it rains and generates an awakening signal. The second attendant circuit receives the awakening signal and controls the working power source to be switched on so as to supply power to the working circuit. The working circuit reads the pulse signal locked and stored by the first attendant circuit and controls the second attendant circuit to switch off the working power source after data processing is carried out on the pulse signal. The micro-power-consumption tipping bucket type rainfall pulse signal collecting device has the advantages of working in the microampere power consumption state when it does not rain, being capable of saving energy, and prolonging the service life of a one-shot battery.

A monolithically integrated CMOS image sensor with double focal micro-lens array comprises a standard CMOS logic circuit integrating a photodiode of silicon pin, a micro-lens array integrated on an optical absorption surface corresponding to an active region of the CMOS circuit, a silicon nitride layer covering the micro-lens array, a color filter arranged on the silicon nitride layer. The invention is characterized in that the micro-lens array, which is a double focal micro-lens array, is monolithically integrated with the CMOS circuit, and with a 1.44-2.0 refractive index, the micro-lens array is applied on a good optical focusing double focal micro-lens array to improve light collection efficiency and quantum efficiency.

Disclosed is an oscillator in which current consumption relating to oscillation is reduced. The oscillator comprises: an amplifier to an input and output of which a piezoelectric oscillator and a feedback resistor are connected in parallel, and which is constituted by a CMOS logic inverter circuit; and a control circuit, which is constituted by a CMOS logic circuit, for clamping input/output levels of the amplifier and halting oscillation before oscillation start-up, unclamping the input/output levels at beginning of oscillation start-up and supplying a pulse signal to an output terminal of the amplifier a prescribed period of time after the beginning of oscillation start-up.

The invention relates to a copper Damascus process MIM (metal-insulator-metal) capacitor structure and a manufacturing process thereof. The structure is characterized that through adding two maskplates, a single Damascus process is used so as to manufacture an MIM capacitor and an inductor simultaneously. According to the technical scheme of the invention, the manufactured MIM double-layer capacitor structure can be completely compatible with a CMOS (complementary metal-oxide-semiconductor transistor) logic circuit and an inductive copper Damascus process, and the density of the MIN capacitor is increased.

A dual mode, analog differential and complementary metal oxide semiconductor (CMOS) logic circuit is provided. The circuit includes a differential input for receiving a differential input signal. A switch pair is coupled to the differential input. A pair of load resistors coupled to the switch pair defines a differential output for providing a differential output signal. A current source is coupled to the switch pair. A control input receives a control signal and control circuitry coupled to the control input disable the current source to select a CMOS testing mode responsive to the control signal being activated.