The invention discloses a low-power-consumption and low-leakage SRAM applied to a storage and calculation integrated
chip. The low-power-consumption and low-leakage SRAM comprises: an SRAM storage operation unit array which comprises N rows and M columns of storage operation units, wherein each storage operation unit comprises a storage module and an operation module and is used for realizing
voltage signal input, storing input data in the storage module and calculating and outputting the data by the operation module; a ground wire
voltage raising module which is used for raising the
voltage of the power supply ground wire of the selected column in the SRAM storage operation unit array so as to improve the writing threshold value of the full-selection unit when the SRAM writes data; and abit line
charge recovery module which is used for recovering the leakage charge of the
bit line of the half-selection unit when the SRAM writes data so as to drive the
ground line voltage lifting module, reducing the voltage of the
bit line of the half-selection unit and improving the
static noise margin of the half-selection unit. According to the invention, the
arithmetic logic unit is integrated into the SRAM, so that the design of the storage and calculation integrated
chip is realized.