4results about "Power reduction by adiabatic operation" patented technology

A method including, during time period A, in a computer storage element having first and second power inputs separated by an array of transistors configured for storing a computer bit of data, moving an input of the array of transistors a logic value "1" or "0" a master latch, during time period B, recovering at least a portion of energy comprising the input with a first clock, during a time period C, moving the input in the master latch to an isolation stage, during time period D, recovering at least a portion of energy comprising the input from the isolation stage with a second clock, during time period E, recovering at least a portion of energy comprising the input from a follower latch with a third clock, and during time period F, moving at least a portion of the input from the isolation stage to the follower latch.

A microchip (300) for driving a resonant circuit, the resonant circuit being an LC tank, an antenna or a piezo transducer, the microchip (300) being a single unit including multiple interconnected embedded components and subsystems including at least an oscillator (315), a pulse width modulation (PWM) signal generator subsystem (329), an analog to digital converter (ADC) subsystem (318), and a digital to analog converter (DAC) subsystem (327).

An AQFP circuit comprises a Josephson junction having a respective plasma frequency, a clocking signal line, an inductive coupler between said clocking signal line and said Josephson junction, and a data signal line be-tween a data signal source and said Josephson junction. The AQFP circuit is configured to feed into said clocking signal line an oscillating clocking signal having a clocking signal frequency selected so that said plasma frequency is an integral multiple of said clocking signal frequency.

Apparatus and associated methods relate to a quasi-adiabatic circuit comprising a plurality of quasi-adiabatic logic gates daisy-chained in a phasing sequence. Each of the quasi-adiabatic logic gates in the daisy-chained sequence has a power node conductively coupled to one of the sinusoidal power signals in the phasing sequence of sinusoidal power signals. The sinusoidal power signal conductively coupled to each of the quasi-adiabatic logic gates is phase delayed relative to the sinusoidal power signal conductively coupled to its immediately preceding quasi-adiabatic logic gate in the daisy-chained sequence. The phase delay is equal to 360 DEG divided by the number of sinusoidal power signals in the phasing sequence of sinusoidal power signals.