2results about "Power reduction by adiabatic operation" patented technology

A method including, during time period A, in a computer storage element having first and second power inputs separated by an array of transistors configured for storing a computer bit of data, moving an input of the array of transistors a logic value "1" or "0" a master latch, during time period B, recovering at least a portion of energy comprising the input with a first clock, during a time period C, moving the input in the master latch to an isolation stage, during time period D, recovering at least a portion of energy comprising the input from the isolation stage with a second clock, during time period E, recovering at least a portion of energy comprising the input from a follower latch with a third clock, and during time period F, moving at least a portion of the input from the isolation stage to the follower latch.

A microchip (300) for driving a resonant circuit, the resonant circuit being an LC tank, an antenna or a piezo transducer, the microchip (300) being a single unit including multiple interconnected embedded components and subsystems including at least an oscillator (315), a pulse width modulation (PWM) signal generator subsystem (329), an analog to digital converter (ADC) subsystem (318), and a digital to analog converter (DAC) subsystem (327).