13results about "Power reduction by adiabatic operation" patented technology

A method includes, during a time period A, in a computer storage element having first and second power inputs separated by an array of transistors, the computer storage element configured to store computer data bits, move an input of the array of transistors, a logic value "1" or "0" to a master latch; during a time period B, recovering at least a portion of the energy containing the input using the first clock; during a time period C, moving the input in the main latch to the isolation stage; recovering at least a portion of the energy containing the input from the isolation stage using a second clock during a time period D; during a time period E, recovering at least a portion of the energy containing the input from the slave latch using a third clock; and moving at least a portion of the input from the isolation stage to the slave latch during the time period F.

An AQFP circuit (202) comprises a Josephson junction (302) having a respective plasma frequency, a clocking signal line, an inductive coupler (307-310) between said clocking signal line and said Josephson junction, and a data signal line (306) between a data signal source and said Josephson junction. The AQFP circuit is configured to feed into said clocking signal line an oscillating clocking signal having a clocking signal frequency selected so that said plasma frequency is an integral multiple of said clocking signal frequency.

A method including, during time period A, in a computer storage element having first and second power inputs separated by an array of transistors configured for storing a computer bit of data, moving an input of the array of transistors a logic value "1" or "0" a master latch, during time period B, recovering at least a portion of energy comprising the input with a first clock, during a time period C, moving the input in the master latch to an isolation stage, during time period D, recovering at least a portion of energy comprising the input from the isolation stage with a second clock, during time period E, recovering at least a portion of energy comprising the input from a follower latch with a third clock, and during time period F, moving at least a portion of the input from the isolation stage to the follower latch.

A microchip (300) for driving a resonant circuit, the resonant circuit being an LC tank, an antenna or a piezo transducer, the microchip (300) being a single unit including multiple interconnected embedded components and subsystems including at least an oscillator (315), a pulse width modulation (PWM) signal generator subsystem (329), an analog to digital converter (ADC) subsystem (318), and a digital to analog converter (DAC) subsystem (327).

The present invention relates to a circuit unit, a circuit arrangement, and a method for reducing the switching losses of a semiconductor switch (T1), wherein the circuit unit comprises: the semiconductor switch (T1), an auxiliary switch (S1), a capacitor (C1), and a logic unit (10), wherein a series connection of the auxiliary switch (S1) and the capacitor (C1) is connected in parallel to a load path of the semiconductor switch (T1), and wherein the logic unit (10) is configured to determine, in a switched-on state of the semiconductor switch (T1), a current (IL) of an electric current to be switched by means of the semiconductor switch (T1) flowing along the load path, and to close the auxiliary switch (S1) before a switching-off process of the semiconductor switch (T1) or to keep it in a closed state if the determined current exceeds a predefined current threshold value.and to open the auxiliary switch (S1) before switching off the semiconductor switch (T1) or to keep it in an open state if the measured current does not exceed the predefined current threshold.

A method including, during time period A, in a computer storage element having first and second power inputs separated by an array of transistors configured for storing a computer bit of data, moving an input of the array of transistors a logic value “1” or “0” a master latch, during time period B, recovering at least a portion of energy comprising the input with a first clock, during a time period C, moving the input in the master latch to an isolation stage, during time period D, recovering at least a portion of energy comprising the input from the isolation stage with a second clock, during time period E, recovering at least a portion of energy comprising the input from a follower latch with a third clock, and during time period F, moving at least a portion of the input from the isolation stage to the follower latch.

An AQFP circuit comprises a Josephson junction having a respective plasma frequency, a clocking signal line, an inductive coupler between said clocking signal line and said Josephson junction, and a data signal line be-tween a data signal source and said Josephson junction. The AQFP circuit is configured to feed into said clocking signal line an oscillating clocking signal having a clocking signal frequency selected so that said plasma frequency is an integral multiple of said clocking signal frequency.

Apparatus and associated methods relate to a quasi-adiabatic circuit comprising a plurality of quasi-adiabatic logic gates daisy-chained in a phasing sequence. Each of the quasi-adiabatic logic gates in the daisy-chained sequence has a power node conductively coupled to one of the sinusoidal power signals in the phasing sequence of sinusoidal power signals. The sinusoidal power signal conductively coupled to each of the quasi-adiabatic logic gates is phase delayed relative to the sinusoidal power signal conductively coupled to its immediately preceding quasi-adiabatic logic gate in the daisy-chained sequence. The phase delay is equal to 360 DEG divided by the number of sinusoidal power signals in the phasing sequence of sinusoidal power signals.

The invention relates to a circuit unit, a circuit arrangement and a method for reducing switching losses of a semiconductor switch (T1), comprising a semiconductor switch (T1), an auxiliary switch (S1), a capacitor (C1) and a logic unit (10), a series circuit consisting of the auxiliary switch (S1) and the capacitor (C1) being connected in parallel to a load path of the semiconductor switch (T1), the logic unit (10) is configured to determine a current intensity of a current (IL) flowing along the load path and to be switched by the semiconductor switch (T1) in an on state of the semiconductor switch (T1), to close the auxiliary switch (S1) or to hold the auxiliary switch (S1) in a closed state before a switching-off process of the semiconductor switch (T1) if the determined current intensity is higher than a predefined current threshold value, and to switch off the auxiliary switch (S1) before the switching-off process of the semiconductor switch (T1). If the determined current intensity is not higher than the predefined current threshold value, the auxiliary switch (S1) is switched off or is kept in the switched-off state before the switching-off process of the semiconductor switch (T1).

Adiabatic and reversible logic have a previously unexploited ability to manage the location where energy is turned into heat. In addition to reducing the total amount of energy used, this ability can be used to move waste energy away from sensitive components before it is turned into heat, allowing supercomputers and quantum computers to scale to larger sizes. Embodiments herein include an adiabatic powertrain and a new adiabatic logic family called Quiet 2-Level Adiabatic Logic (Q2LAL) that supports energy management both at room (supercomputer) and cryogenic (quantum computer) temperatures. Managing energy effectively requires coordinated actions by a computer's physical and algorithmic components. These embodiments describe how computational tasks can be distributed such that tasks that consume energy and dissipate heat are performed at the most appropriate location without unnecessarily impacting performance. Using the methods herein, a quantum computer design approach is disclosed, which is more suitable to scale up.

A circuit unit for reducing switching losses of a semiconductor switch. The circuit unit includes: the semiconductor switch, an auxiliary switch, a capacitor, and a logic unit. A series circuit including the auxiliary switch and the capacitor is connected in parallel with a load path of the semiconductor switch. The logic unit is configured to determine, in a switched-on state of the semiconductor switch, a current intensity of an electric current to be switched using the semiconductor switch and flowing along the load path, close the auxiliary switch or to keep it in a closed state before a switch-off operation of the semiconductor switch when the determined current intensity exceeds a predefined current threshold value, and open the auxiliary switch or to keep it in an open state before a switch-off operation of the semiconductor switch when the determined current intensity does not exceed the predefined current threshold value.

A resonant clocking system for reducing wideband series resonant clock skew is provided. The resonant clocking system includes at least one Pulsed Series Resonance (PSR) driver, at least one clock gater, and at least one clock buffer. The PSR driver is connected with at least one on-chip inductor. The PSR driver receives a boosted-amplitude pulsed signal VSR that is generated using a matching pulse generator and at least one on-chip inductor connected with the at least one Pulsed Series Resonance (PSR) driver resonates with a capacitance of the resonant clocking system to generate a pulse signal RCLK. The at least one clock gater and the at least one clock buffer propagate the pulse signal RCLK to clock pins of resonant flip-flops. An inductance value of the at least one on-chip inductor is matched with a load capacitance of a corresponding branch capacitance using an inductor tuning technique to obtain equal frequency signals in all clock branches, thereby storing dissipated energy in a form of a magnetic field in the at least one on-chip inductor and reducing wideband series resonant clock skew.