14 results about "Power analysis" patented technology

This invention discloses a security chip based on a configurable lookup table. The security chip includes: at least one configurable logic block, each containing at least one configurable lookup table unit; a dynamic mask generator connected to the configurable lookup table unit, dynamically generating a mask sequence according to the current processing clock cycle; a reconfiguration controller connected to the dynamic mask generator, changing the configuration values ​​of the configurable lookup table units in real time according to a security policy; and a security execution engine, whose input is connected to the output of the configurable lookup table unit, performing secure operations based on the masked lookup results; wherein the configurable lookup table unit presents different truth table mappings for the same logic input in at least two different clock cycles. This invention enables the lookup table unit to present different truth table mappings in different clock cycles, breaking the deterministic correlation between power consumption characteristics and data, and effectively resisting side-channel attacks such as differential power analysis.

The application provides a line loss analysis method and system based on carbon flow tracking, and belongs to the technical field of power data anomaly analysis. CE = CE in ‑ CE o , CE The total loss carbon amount of the node i ; CE in The total input carbon amount of the node i ; CE o The total output carbon amount of the node i ; an XGBoost model for carbon amount anomaly screening is constructed based on a gradient decision tree XGBoost, and a target function of the model; each node in a network topology is analyzed based on the XGBoost model, and a carbon amount anomaly node is predicted based on the power and carbon emission density of each node; each user corresponding to the carbon amount anomaly node is subjected to power analysis, the power analysis includes high-voltage user abnormal power analysis and low-voltage user abnormal power analysis, and the type of abnormal situation existing in the user is obtained.

This invention discloses a power analysis self-healing control method and apparatus for integrated circuit power supplies, relating to the field of integrated circuit technology. The method includes: collecting detection data of the power supply to be evaluated; extracting features from the detection data to obtain a multi-dimensional feature data sequence; inputting the multi-dimensional feature data sequence into a pre-trained target network model to predict the power supply parameter degradation prediction result; determining the PWM control parameter adjustment amount based on the power supply parameter degradation prediction result; generating a self-healing control command based on the PWM control parameter adjustment amount and the power supply parameter degradation prediction result, and outputting the self-healing control command; the power supply system to be evaluated responds to the self-healing control command by adjusting the PWM control parameters. This method provides early identification of power supply faults and dynamic self-healing control of the power supply, thus effectively avoiding equipment downtime for maintenance and reducing equipment maintenance costs.

This invention belongs to the field of measurement and analysis technology, and relates to a data processing system for a Yokogawa power analyzer based on the LabVIEW platform. The system includes a communication module, a data processing module, a data acquisition and synchronization module, and a data storage and export module. By constructing a standardized communication interface based on VISA-SCPI, an ASCII data stream structured parsing engine, a unified modeling mechanism with a shared variable library, and a native synchronous acquisition architecture based on TDMS, this invention achieves physical homogeneity, temporal synchronization, and logical isomorphism between the raw measurement data from the Yokogawa power analyzer and the multi-source sensor data from the test bench within the LabVIEW platform. Without the need for additional hardware gateways or post-processing interpolation, it achieves microsecond-level trigger alignment and frame-level parameter binding, ensuring the time synchronization of power parameters with other physical quantities. This significantly improves the automated testing efficiency, data integration capabilities, and multi-dimensional joint analysis level of the test bench.

The present application belongs to the technical field of power supply detection and aging management, and particularly relates to a mobile DCS power supply automatic detection device. An input of an industrial computer inputs power supply information to be detected, formulates power supply test steps to be detected, generates control instructions, controls other units to work in coordination to complete input / output / protection tests of the power supply to be detected, and gives test reports and statistical results. An AC test power supply and a power supply loop provide various input parameter changes according to instructions of the host computer. An electronic load and a load loop provide various output load changes according to instructions of the host computer. A system control unit completes power supply protection action command changes according to instructions of the host computer. A power analyzer and input collection and sampling loops complete input / output test result collection and feedback to the industrial computer. According to input power supply parameters to be detected, selectable power supply test items are designed, input / output performance of the power supply under different conditions is detected, and reports and analysis results are formed.

This invention relates to the fields of information security and quantum-resistant computing, and discloses a hardware-accelerated parallel implementation method and system for quantum-resistant encryption algorithms. The method includes: configuring a parallelized quantum-resistant encryption core computing array; deploying a spiking neural network control module that simulates the random firing behavior of biological neurons, and connecting it to a power-compensating execution unit; monitoring key computing cycles and activating the module; using the non-periodic random pulses generated by the module to drive power consumption perturbation, deeply fusing instantaneous power consumption and noise; and dynamically adjusting neuron parameters through a feedback mechanism to make the total power consumption exhibit random characteristics similar to biological neural electrical signals. Through the above scheme, this invention disguises the encryption power consumption trajectory as random noise, resisting physical attacks such as differential power analysis without sacrificing computational performance, thereby improving the physical layer security and energy efficiency of the quantum-resistant encryption system.

The application relates to a SM4 algorithm mask implementation method for resisting power consumption analysis on a DSP chip, which comprises the following steps: obtaining plaintext data to be encrypted and an initial round key; generating a first random mask equal to the length of the plaintext data, and performing a first mask operation on the plaintext data by using the first random mask to obtain first mask state data; for the multi-round iteration encryption structure of the SM4 algorithm, in each round of encryption operation, a second random mask is generated based on the current round key; the first mask state data and the second random mask are input into an arithmetic logic unit of the DSP chip to execute a round function F which is subjected to mask conversion, wherein the round function F comprises a nonlinear transformation T and a linear transformation L; in the nonlinear transformation T, a pre-constructed and stored S-box lookup table which is subjected to mask processing is called, and the input data and the output data of the S-box lookup table which is subjected to mask processing are both covered by masks; the DSP implementation SM4 mask of the application is resistant to power consumption, is safe and efficient, and has better hardware adaptability.

This invention relates to the field of digital information transmission security and discloses a design method for an SM2 hardware accelerator resistant to side-channel attacks in an RTOS. The method includes: constructing an absolute time window strictly aligned with the communication time slot period based on a bus synchronization clock; monitoring the SM2 operation progress within the window and automatically triggering an isochronous flow control unit upon completion of the actual instruction; this unit drives the operation core to perform twin pseudo-instruction filling on irrelevant data, isomorphic to the actual instruction, until the window terminates and the result is output. This invention physically shapes non-constant-time cryptographic operations into carrier signals with fixed timing and continuous equal-amplitude power envelopes, eliminating feature leakage in differential power analysis and ensuring that the hardware accelerator presents a zero-jitter, time-rigid node to the RTOS, thus meeting the stringent requirements of deterministic transmission in industrial time-sensitive networks.

The application relates to the technical field of power market data analysis, and discloses a power consumption analysis self-adaptive adjustment method and device based on natural language driving, which comprises the following steps: S1, receiving power consumption analysis algorithm adjustment requirements input by a user in natural language; S2, standardizing and preprocessing the natural language to obtain a standardized semantic text; S3, calling a power industry exclusive natural semantic rule library, adopting a bidirectional attention segmentation algorithm and a triple alignment algorithm to analyze the standardized semantic text, and outputting structured demand characteristics; and S4, inputting the structured demand characteristics into a three-level composite mapping model, combining hash-vector hybrid retrieval, and generating power analysis algorithm executable standardized adjustment instructions and the like. The method can realize natural language input directly driving power consumption analysis algorithm self-adaptation, code-free, millisecond-level, super-high-precision adjustment, and greatly improves analysis accuracy, system stability and use flexibility.

The application discloses a power system transmission section transmission power limit and fault analysis method. A system topology undirected graph capable of representing the topology structure of a power system is constructed, a transmission section parameter model of a standardized operation mode is established, and the sending end and the receiving end of the transmission section are determined. A power system transmission section sending end unit automatic search model based on a topology analysis method is further constructed, and fault cards for transient stability analysis of different elements and fault types are generated in batches. A transmission section transmission power analysis model is constructed based on GRPO, and a transmission section transient stability transmission limit calculation model is constructed by adopting a repeated power flow strategy to determine the transient stability transmission limit of the target transmission section. A transmission section fault identification model considering transient stability constraints is constructed to identify the key fault restricting the transmission capacity of the target transmission section.

This invention proposes a side-channel attack defense system and method based on dynamic noise injection and multi-path randomization, belonging to the field of network security technology. The system includes a noise injection module, a time equalization engine, a dynamic mapping unit, and a quantum key interface. The method includes six steps: noise masking, random source acquisition, path randomization, dynamic data mapping, equalization execution, and result output. This invention masks physical signals through dynamic noise injection, disrupts execution trajectories using multi-path randomization, and eliminates timing differences by combining time equalization operations, thereby constructing a collaborative defense system from the physical layer, logic layer, and timing layer. It can effectively resist various side-channel attacks such as power analysis, electromagnetic analysis, and time analysis, significantly improving security while ensuring system computational efficiency. It can be widely applied in scenarios such as encryption chips, IoT devices, and cloud computing containers.

The application discloses an intelligent AI computing power system working state control system, relates to the technical field of AI computing power system management, and comprises a data acquisition module, a computing power analysis module, a device prediction module and a device planning module.The data acquisition module is used for collecting data of the previous year operation of the intelligent AI computing power system and classifying the collected data.The technical key points are as follows: the data of the previous year operation of the intelligent AI computing power system is analyzed and processed, and then prediction is carried out, the total computing power Zsl required by the intelligent AI computing power system operation at a future time point of the current year is predicted, and then the number of required devices is analyzed and judged according to the total computing power Zsl, which can help relevant personnel to understand the number of required devices at different time points in the future, can reasonably allocate devices, and can avoid the cases that too many devices are idle or too few standby devices are provided, so that the overall use effect is good, and the application has a good use prospect.

The application relates to the technical field of vehicle chip testing, and discloses a domain control chip computing performance automatic testing method and platform system, the platform system comprising: a to-be-tested domain control chip system, which is used for executing pre-designed computing tasks and outputting real-time performance data; a data connection system, which comprises a power analyzer and a protocol analyzer and is used for collecting electrical parameter and communication load data; an automatic platform system, which is used for dynamically scheduling test cases, converging multi-source data and triggering an abnormal protection mechanism; a test host computer system, which is used for configuring a test strategy and generating a visual report, and supports historical data comparison and performance trend analysis; and the to-be-tested domain control chip system, the data connection system, the automatic platform system and the test host computer system are interconnected through physical or communication links to form a closed-loop test architecture. The application can realize full-stack closed-loop automatic testing, and the test indexes are comprehensive, the test results are reliable, and the test efficiency is relatively high.