163 results about "Round function" patented technology

The invention discloses a cipher device adopting a Feistel-PG structure and an encryption method. The Feistel-PG structure consists of a round function F, the round function F maps a t*k*m bit string into a t*k*m bit string, the input X is mapped into U through linear conversion P and nonlinear conversion G, the linear conversion P is displacement based on the t*k*m bit string and is the position conversion of t*m k bit characters, the nonlinear conversion G is concatenation of t nonlinear conversions based on t*k bit string, the nonlinear conversion T is nonlinear conversion based on k*m bit string, and T converts (um-1 to u1, u0) into A (S(um-1 to u1, u0)) through S box layer and linear conversion A, wherein the S box layer is formed by m k*k s boxes through concatenation, and the linear conversion A is linear conversion based on k*m bit string. The encryption method adopting the Feistel-PG encryption structure comprises round key addition, linear conversion P and nonlinear conversion G, the output of plaintext W after the r-round iteration is used as ciphertext. Through the device and the method provided by the invention, the cipher algorithm design is more flexible, and in addition, lower realization cost can be realized at the same security intensity.

An efficient software implementation of the round function of the Data Encryption Standard (DES) involves mathematical transformations performed on the DES round function and the DES round key computation function that reduce the computation required to complete a DES round on general-purpose, embedded, and cryptographic processors. These transformations shift computation associated with the Expansion Permutation from the DES round function to the DES round key computation function. As a result, fewer instructions are required to compute the inputs of the DES S-boxes in the round function.

Provided are an arithmetic method and apparatus for supporting Advanced Encryption Standard (AES) and Academy, Research Institute and Agency (ARIA) encryption/decryption functions. The apparatus includes: a key scheduler for generating a round key using an input key; and a round function calculator for generating encrypted/decrypted data using input data and the round key. Here, the round function calculator includes an integrated substitution layer and an integrated diffusion layer capable of performing both AES and ARIA algorithms.

The invention discloses a novel low-resource efficient lightweight Surge block cipher implementation method. The method comprises the steps that the Surge block length is designed to be of a 64-bit type, and the secrete key length is designed to be of the 64-bit type, the 80-bit type and the 128-bit type on the basis of the SPN structure; a secrete key is in a non-extensible mode; five modules of a round function are combined in a new mode, the encryption sequence is constant addition, round key addition, S-box replacement, row shifting and column mixing transformation, and column mixing transformation does not exist in the last round; a constant addition transformation module operates a round constant in each round; according to the round constant selection combination, 0, 1, 2 and 3 are selected as the high bits, the combination of one odd number, one even number, one even number and one add number from 0 to 15 is selected as the low bits, and the obtained combinatorial numbers are randomly fixed into a permutation; a column mixing transformation module utilizes the (0,1,2 and 4) combination which facilitates hardware implementation for forming a matrix, and hardware is constructed on a galois field GF (24) to obtain the friendly matrix. The experimental result shows that the occupied area resources are smaller, meanwhile, the encryption performance is good and the known attacks can be resisted compared with existing lightweight ciphers of the SPN structure.

The invention discloses a method and apparatus for implementing a lightweight block cipher SCS. A turn key and a control key are divided in keys, the round key participates in a round key adding operation, the control key controls the generation of each turn of S box to obtain a random S box, the update of the control key and the turn key is related to the operation result of the last turn, the Sbox used in each turn is random, the operation result of each turn is also random, so that the degree of confusion can be increased; in a round function, a high pseudo-random P permutation is generated by the Mason rotation algorithm in each round to achieve the diffusion, and after the end of the round function iteration, row shift and the column confusion transform are executed, so that the diffusion effect is enhanced by using the dual diffusion mode, and the security is improved. Compared with the situation that the difference between the resource consumption of fixed cipher structures isnot large, the internal structure of the device has the advantages of greatly improving the security of the scheme, and increasing the defense coefficients of linear attack, differential attack and the like to a certain extent.

The invention provides a method of generating arbitrary numbers given a seed, characterized by providing a challenge derived from the seed to a physical token, receiving an initial response from the physical token, combining the initial response with helper data associated with the challenge to produce a stable response, and generating the arbitrary numbers using a pseudo-random number generator using the stable response as a seed for the generator. Preferably one or more of these pseudo-random permutations are used as one or more round function(s) in a Feistel block cipher. The generated arbitrary numbers may also be used to create a cryptographic key.

Disclosed are an apparatus and a method for encryption. The apparatus includes a key table generator configured to generate random values based on a seed value and generate a key table including the generated random values; and an encryptor configured to apply the generated key table to a round function, generate a block encryption algorithm having a Feistel structure based on the round function, and encrypt a plaintext data block based on the generated block encryption algorithm.

An apparatus and method are disclosed for minimizing accumulated rounding errors in coefficient values in a lookup table for interpolating polynomials. Unlike prior art methods that individually round each polynomial coefficient of a function, the method of the present invention use a “ripple carry” rounding method to round each coefficient using information from the previously rounded coefficient. The “ripple carry” method generates rounded coefficients that significantly improve the total rounding error for the function.

In an unsafe environment, a cryptographic analyzer can implement attacks on an algorithm and a secret key by tracking a binary system operated by a program, reading the secret key in a memory and a program execution intermediate result, carrying out static analysis and the like, and a white-box cryptographic algorithm can protect the secret key in the unsafe environment. The invention discloses a 16-round SM4-128/128 white box password implementation method, which describes a new mode of improving an SM4 password algorithm when the encryption round number is 16, and the mode improves the structure of a round function, namely the iterative process of the encryption algorithm. An improved SM4 white-box cryptographic algorithm is provided, and the whole encryption and decryption process can be converted into a form of calculating randomly selected affine transformation and lookup tables. The principle is that the internal state of a coding hiding algorithm is input and output scrambled, the secret key is embedded into a lookup table in a coding mode, and meanwhile, a block matrix is used for reducing the scale of the lookup table.

The invention discloses a housing case flanger, which comprises an axial feed mechanism, a main shaft box, a clamp device and a rotary pressing device, wherein the clamp device is fixed to the axial feed mechanism; and the rotary pressing device is in transmission connection with the main shaft box. The use method of the housing case flanger comprises the steps of fixing a housing case, rotary pressing a horn mouth, rotary pressing a right-angle side and the like. The housing case flanger and the use method thereof are adopted; through the autorotation of main rotating wheels and auxiliary rotating wheels and the rotation of a turnplate, a horn side and a right-angle side flange of the housing case are subjected to rotary pressing; since the clamp device which internally expands and externally holds is used for fixing the housing case, and the clamp device has an automatic centring rounding function, a necking-down phenomenon cannot happen to an opening of the housing case in the rotary pressing process, an assembling clearance between the impeller outer diameter of a draught fan which is finally assembled and the inner wall of the housing case can be reduced, and the aerodynamic performance and the efficiency of the draught fan are improved.

The invention discloses a mask method and a mask device for an SM4 algorithm. The mask method comprises the following steps: acquiring an inputted masked plain text, a random mask and round keys; carrying out a first round operation of a round function on the masked plain text, the random mask and a first round key in the round keys, to obtain a first round ciphertext and a first round mask; carrying out a second round operation of the round function on the first round ciphertext, the first round mask and a second round key in the round keys, to obtain a second round ciphertext and a second round mask, so as to realize N rounds of operation of the round function in turn; and carrying out an XOR operation an N round ciphertext and an N round mask outputted from the N round operation, wherein the operation result is taken as an output of the SM4 algorithm. Namely, except for the first round operation in the N rounds of operation of the round function, masks required for each round operation are all obtained by the output of the last round operation next to the current round operation, and therefore a demask on an intermediate value of the N rounds of operation is not required by adopting the technical solution disclosed by the invention, so that a resistance to an energy attack is realized.

The invention discloses a three-dimensional space vector modulation algorithm of a multi-level inverter. According to the algorithm, coordination transformation and trigonometric function operation are avoided, a three-phase reference voltage is directly mapped to a three-dimensional space coordinates system and sampled, the switching state vector closest to the sampled reference voltage vector is obtained through a round function, three coordinate components of the switching state vector are changed in sequence with the switching state vector as the starting point according to the relation between the switching state vector and the reference voltage vector, four switching state vectors are obtained, the reference voltage vector is combined through the four switching state vectors, and switching among the four switching state vectors is achieved. According to the algorithm, the space vector modulation algorithm of the multi-level inverter is simplified and is suitable for any multi-level inverter, and the output voltage zero-sequence component is controlled within the range shown in the specification, and the space vector modulation algorithm can be applied and popularized in the multi-level inverter.

The invention relates to a method and device for generating symmetric block ciphers. The device adopts chips for symmetric block ciphers. The method is characterized in that initial replacement is carried out on the input data; all the round function operations in the first-stage pipeline are carried out on the input data; the data after undergoing operations in the first-stage pipeline are input into the second-stage pipeline, and the second group of data are input into the first-stage pipeline; when a group of data in one batch finish all the round function operations, the data are transmitted to an inverse initial replacement module by a data output controller under the control of a sequential control module to finish encryption and decryption operations; simultaneously, when a group of data in the above step are output, a group of data in the next batch are output to the pipeline and the rest can be done in the same manner to finish all the encryption and decryption operations. After adopting the method, under the premise of not reducing the number of rounds of cipher algorithm iteration, the area of the chips is reduced by a specific method of module reuse.

The invention provides a lightweight cryptographic algorithm HBcipher implementation method and device. In the method, a round function used in the encryption or decryption process is an F function adopting three groups of SPN structures, and a novel P2 substitution mode is proposed in the round function. By selecting a round constant count as a round operation control signal, two different operation modes are designed according to the parity of count; when the algorithm is implemented by Xilinx ISE Design Suite 13.2 hardware, the throughput rate of HBcipher-64 is 511.38 Mbps, the throughput rate of HBcipher-128 is 716.6848 Mbps, and compared with a current lightweight cryptographic algorithm, the algorithm has high encryption efficiency.