29 results about "Round function" patented technology

The invention relates to the technical field of data security, in particular to a CPA-based SMBA encryption algorithm side channel attack method and related equipment, and the method comprises the steps that a collection probe and a programmable oscilloscope are used to collect side channel leakage information when a cryptographic chip runs an SMBA algorithm, and the side channel leakage information comprises a power consumption curve, a current curve or an electromagnetic signal; selecting a result of whitening transformation in a round function of the SMBA encryption algorithm as an intermediate value, calculating the result of whitening transformation in the encryption process for each input data and the assumed encryption sub-key, and constructing an intermediate value set; performing correlation analysis by using the side channel leakage information and the intermediate value set to deduce an encryption sub-key of an SMBA encryption algorithm; the invention provides an effective security assessment means for the practical application of the SMBA encryption algorithm.

The invention provides an SM3 and SM4 fusion optimization method and system based on an SIMD register, and belongs to the technical field of data encryption and hash optimization. Executing SM3 message extension, writing an extension result into a stack area according to the determined mapping relation, and then reading extension data from the stack area by a compression function according to the mapping relation and executing a previous round operation of the SM3 compression function; reading a parameter pointer address of the SM4 from a stack area, loading a data block to be encrypted into an SIMD register, and performing format conversion from a large end sequence to a small end sequence on data; inserting a round function of the SM4 realized by using an SIMD instruction into a post-set round compression function of the SM3, so that a compression function instruction of the SM3 and a round function instruction of the SM4 are alternately executed, and post-set round calculation after merging is completed; after all round function calculation of the SM3 and the SM4 is completed, the encryption result of the SM4 is stored in the memory, then the parameter pointer of the SM3 is read from the stack area, and the hash result of the SM3 is written in the memory.

The invention discloses a low-overhead anti-power analysis AES (advanced encryption standard) algorithm mask protection method. According to the method, two shares of a plaintext and a secret key are received in a clock period 0, ten rounds of round functions are executed from the clock period 0 to the clock period 30, each round needs three clock periods, and two shares of a ciphertext are output in a clock period 31; in the implementation of a round function and key expansion, the calculation of an S box (not including input linear mapping) needs three clock periods; in the third clock period after S box calculation is completed, a round of residual operation (wherein the residual operation of a round function comprises a multiplication module of the S box, S box output linear mapping, row shifting, column confusion and round key addition, and the residual operation of key expansion comprises key word XOR generation of a next round of round key) and the next round of S box input linear mapping calculation are completed at the same time. According to the mask, the side channel security capability of first-order power consumption analysis resistance can be provided for the AES algorithm, and the requirements on random numbers and chip area are remarkably reduced.

The invention relates to the technical field of information security, in particular to a sequential cipher security analysis method for a composite structure, which comprises the following steps of: acquiring round function parameters of a target cipher algorithm, nonlinear component definition and a key scheduling rule, and generating a standardized configuration data set; dividing the complete algorithm into a plurality of independent low wheel structures along the boundary of the nonlinear component according to the wheel function parameters, and constructing a directed graph data model containing state transition constraints to compress a state space; calling a password component vulnerability feature library to quantify a sub-structure active S box distribution abnormal value and a linear diffusion layer vulnerability path, and generating a risk weight priority ranking list; and inputting the state sequence data into the target application environment simulation platform, and generating a reproducible vulnerability report when the output deviation exceeds a security threshold. Through hierarchical compression, risk guidance and multi-environment verification, the technical defect of insufficient path coverage of a high-round-number lightweight algorithm in a resource-limited scene is solved.

The application relates to the technical field of data encryption, and discloses a data encryption device, a memory encryption and decryption system and a chip. The device comprises an address input end, a password root output end, a key generation circuit for generating a first key and a second key with n bits, and a data encryption logic circuit comprising a four-round encryption module. Four-round encryption units in the four-round encryption module comprise an interleaver with n bits, four 64-bit round function components arranged on both sides of the interleaver, and two sub-circuits for encrypting residual data and residual keys. The data encryption logic circuit is connected with the address input end, the password root output end and the key generation circuit, is used for performing alignment processing on a memory access address, and performs interleaving encryption processing on the n-bit aligned address, the first key and the second key obtained through the alignment processing on the basis of the four-round encryption module to generate a password root with n bits. The encryption device is used for encrypting write data on the basis of the password root, and the decryption device is used for decrypting read data on the basis of the password root.

The application discloses a high-performance block cipher construction method and device, electronic equipment and a storage medium, wherein the method comprises: an encryption process: using a preset round function generation algorithm to encrypt plaintext to obtain ciphertext, wherein a round key in the preset round function generation algorithm is obtained by performing position permutation on 32 positions in units of 4 bits through a 128-bit key scheduling algorithm; and a decryption process: decrypting the ciphertext through a decryption algorithm to obtain the plaintext. Thus, the problem that the existing block cipher algorithm has high resource occupation when hardware is efficiently implemented, and has low software implementation efficiency is solved.

The application discloses an identity authentication and key distribution method and system based on a white-box cryptographic algorithm, and the method comprises the following steps: a communication initiator generates an identity authentication token by using randomly selected white-box code and sends the token to a key management center; a session key distribution token sent by the key management center is received, the session key distribution token is generated by the key management center after the identity authentication token is verified to be correct, and the session key distribution token comprises a target round function generated based on a randomly selected session key; the communication initiator refreshes the reference code stored locally by using the target round function and the white-box code stored locally, and generates a communication session white-box cryptographic algorithm; the communication initiator sends the communication session white-box cryptographic algorithm and the session key distribution token to a communication responder for encrypted communication; and the application reduces the resource consumption of white-box code transmission and switching in the whole identity authentication and key distribution process while ensuring security.

The invention discloses a password period evaluation method and device based on an SH structure. The method comprises the steps of obtaining a to-be-evaluated cryptographic algorithm; converting the input of the cryptographic algorithm into a plaintext mode and constructing a structural model of the cryptographic algorithm; inputting the plaintext mode into a structure model of the cryptographic algorithm, and performing round function iteration operation to obtain the periodic function round number, independent variables, parameters and output variables of the cryptographic algorithm; constructing a periodic function, verifying the correctness of the constructed periodic function, judging whether the round number of the periodic function is greater than one half of the whole round of the to-be-evaluated cryptographic algorithm under the correct condition, and if yes, determining that the evaluation result of the to-be-evaluated cryptographic algorithm is safe under the quantum model; and if not, determining that the evaluation result of the cryptographic algorithm to be evaluated is unsafe under the quantum model. The design method is simple and easy to realize on software and hardware platforms, and has the advantage of high efficiency.

The invention discloses a block chain anti-quantum hash calculation method and system based on modulo 30 shrinkage residual coefficient prime numbers, and belongs to the technical field of block chain security. The method comprises the steps of obtaining to-be-processed block chain data; constructing a prime number replacement function P30 and a modulo 30 confusion function M30 based on a modulo 30 simplified residual system Z30 * = {1, 7, 11, 13, 17, 19, 23, 29}, and performing modulo 30 congruence replacement on a special number 1 in Z30 by adopting a prime number 31 to form a modulo 30 congruence prime number set of Z30; the method comprises the following steps: embedding an M30 function into a core compression round function of an SHA256 algorithm, and constructing an improved Hash algorithm Mod30SHA256; and performing hash operation on the block chain data by using a Mod30SHA256 algorithm to generate a 256-bit hash value, and writing the 256-bit hash value into the block chain. According to the method, a number-theory confusion layer of a modular 30 shrinkage residual system is introduced, and a double diffusion mechanism of number-theory confusion and bit operation confusion is constructed, so that the quantum attack resistance of the Hash algorithm is effectively improved, the operation efficiency basically equivalent to that of SHA256 is kept, the method is seamlessly compatible with an existing block chain architecture, a core structure and a consensus mechanism of a block chain do not need to be modified, and the method is easy to implement. And smooth upgrading can be realized through direct deployment, and a lightweight anti-quantum hash solution is provided for the block chain system.

The invention relates to a block cipher algorithm architecture, an algorithm calling method and device and electronic equipment. The algorithm architecture comprises a quantum security layer which is used for taking a quantum true random number generator as a key entropy source and generating an unpredictable initialization vector and a dynamic key seed based on a quantum optical effect; the hybrid encryption layer is used for encrypting a session key by adopting a hybrid encryption mechanism of post quantum cryptography and SM4 and using a public key algorithm based on lattice cryptography, generating a master key through an anti-quantum algorithm, and generating a sub-key sequence in combination with an SM4 round key expansion algorithm; the core algorithm layer is used for optimizing a round function, dynamically generating an S-box replacement table based on quantum random numbers through an implicit coding technology of dynamic S-box generation and white-box protection, carrying out implicit coding on XOR and shift operations in the round function and injecting redundant noise data; and the protocol adaptation layer is used for integrating a dynamic defense protocol. The encryption security can be improved, and the algorithm efficiency can be remarkably improved.

The application provides an SM3 and SM4 fusion optimization method and system based on a SIMD register, belongs to the technical field of data encryption and hash optimization, and comprises: a required stack area; performing SM3 message expansion, writing an expansion result into the stack area according to a determined mapping relationship, then a compression function reads expansion data from the stack area according to the mapping relationship and performs a preset round operation of an SM3 compression function; reading an SM4 parameter pointer address from the stack area, loading a data block to be encrypted into a SIMD register, and performing format conversion of big-endian sequence to little-endian sequence on the data; inserting a round function of SM4 realized by using a SIMD instruction into a post-set round compression function of SM3, so that the compression function instruction of SM3 and the round function instruction of SM4 are alternately executed to complete post-set round calculation after merging; after all round function calculation of SM3 and SM4 is completed, the encryption result of SM4 is stored back into a memory, then an SM3 parameter pointer is read from the stack area, and the hash result of SM3 is written back into the memory.

This application discloses a lightweight hardware implementation method and related apparatus for SHA-3, belonging to the field of post-quantum cryptography. The lightweight hardware implementation method of this application includes initializing a state matrix and absorbing input data into the state matrix; initiating a round function calculation process: when the current round number is less than or equal to a preset round number, reading target data from the state matrix and sequentially performing write-back operations of θ transformation, χ transformation, ι transformation, fused ρ transformation, and π transformation on the target data to obtain the transformed state matrix; when the current round number is greater than the preset round number, calculating and outputting the hash result based on the transformed state matrix. Using this application helps reduce the consumption of logical and storage resources.

The invention relates to the technical field of cryptography, and provides an encryption method and system based on computer-aided proof security, and the method comprises the steps: carrying out the parametric modeling of an EGFN structure, constructing a constraint condition based on a differential cryptographic analysis framework, and carrying out the optimization of the constraint condition through an SMT constraint solver; calculating the minimum number of rounds of complete diffusion of all rounds of functions of a certain round of the EGFN structure during encryption inquiry and the minimum number of rounds of complete diffusion of all rounds of functions of a certain round of the EGFN structure during decryption inquiry; constructing a coefficient matrix of the ciphertext output by the EGFN structure about a round function, and calculating the minimum round number when the coefficient matrix of the ciphertext output by the EGFN structure about the round function reaches a full rank during encryption inquiry through a linear algebraic calculation tool; and when the EGFN structure meets the security, encrypting the plaintext through the EGFN structure to obtain a ciphertext. And the encryption speed and security are improved.

The invention relates to the technical field of information security, and provides an encryption authentication method based on a hash function and a Feistel structure, the encryption authentication method comprises an encryption authentication algorithm and a decryption verification algorithm, the encryption authentication method is realized by taking the Feistel structure as a password structure, selecting a hash function as a round function of the Feistel structure, and instantiating the round function into a hash function. According to the invention, encryption and decryption and message integrity verification can be carried out. The plaintext length and the secret key length are selectable, and the method is high in universality, good in expansibility, low in error code diffusion and high in safety. The method can be widely applied to wireless communication environments such as satellite internet and internet of things.

The invention relates to the technical field of cryptographic analysis, and discloses an automatic linear path analysis method and system for an ARX type cryptographic algorithm, and the method comprises the following steps: constructing a round function, configuring a linear analysis target, and selecting a search strategy; performing linear mask initialization on the round function, and establishing an association relationship between inter-round mask variables; generating local linear mask propagation expressions based on the linear approximation characteristic of each basic operation unit, combining the local linear mask propagation expressions into a global linear approximation model, and calculating a correlation expression of a linear path; executing a search strategy on the global linear approximation model; converting the global linear approximation model and the search strategy into constraint description and solving the constraint description; according to the method, the modeling complexity of linear analysis is reduced through visual modeling and selection of the path search strategy, and automation of the linear path search process is achieved.

The present application is directed to the security problem of ROCCA algorithm and the low-efficiency implementation problem of the algorithm in the resource-restricted embedded environment, and provides an implementation method of an improved algorithm SAFE for the ROCCA algorithm in the ARM Cortex series embedded microprocessor environment.The SAFE round function adopts the components of the AES twice iteration, so that the SAFE can be efficiently implemented based on the semi-fixed slice in the resource-restricted embedded device; and in order to improve the security of the algorithm, the SAFE algorithm improves the structure of the ROCCA algorithm, on the one hand, adds two sets of operations of the key XOR initialization and the key XOR generation tag, and on the other hand, makes corresponding modifications to the initialization, the encryption plaintext and the generation tag part of the ROCCA algorithm.Compared with the ROCCA, the SAFE can better resist the key recovery attack, the state recovery attack and the differential attack, and has better security.

This invention discloses a lightweight authentication encryption algorithm differential fault attack method, relating to the fields of cryptography and information security technology; it initializes the AEGIS encryption algorithm and injects a random single-bit fault, with plaintext P as input. i The method involves encrypting the AEGIS encryption algorithm after initialization to generate correct and incorrect ciphertexts and obtaining their output difference. The output difference between the correct and incorrect ciphertexts is then XORed, and the location of the fault is determined using the XOR result. Byte state recovery is then performed based on the XOR result, and the word state recovery process is repeated. Finally, the inverse round function formula and encryption formula are applied to restore the complete internal state. This invention employs a lightweight authentication encryption algorithm differential fault attack method, which can efficiently extract key features from complex high-dimensional time-series data and accurately identify potential fault modes.

This invention discloses an edge medical emergency signal encryption processing method based on a race-sleep strategy, relating to information security technology and embedded hardware acceleration technology. The method includes the following steps: S1, real-time monitoring of the number K of physiological data blocks to be encrypted in the data input buffer; S2, comparing the number K of data blocks with a preset minimum start threshold, and generating a global wake-up pulse when K ≥ 0; S3, responding to the global wake-up pulse, causing the fully expanded pipeline layer to transition from a sleep state to a full-speed running state, and sequentially injecting K data blocks into the fully expanded pipeline layer for encryption processing. This invention originates from the fully expanded architecture, which eliminates iterative feedback loops and, in conjunction with a deep pipeline, cuts off critical paths. By spatially instantiating R round function units, it achieves the output of a complete ciphertext block per clock cycle, improving throughput while reducing power consumption.

The application relates to a SM4 algorithm mask implementation method for resisting power consumption analysis on a DSP chip, which comprises the following steps: obtaining plaintext data to be encrypted and an initial round key; generating a first random mask equal to the length of the plaintext data, and performing a first mask operation on the plaintext data by using the first random mask to obtain first mask state data; for the multi-round iteration encryption structure of the SM4 algorithm, in each round of encryption operation, a second random mask is generated based on the current round key; the first mask state data and the second random mask are input into an arithmetic logic unit of the DSP chip to execute a round function F which is subjected to mask conversion, wherein the round function F comprises a nonlinear transformation T and a linear transformation L; in the nonlinear transformation T, a pre-constructed and stored S-box lookup table which is subjected to mask processing is called, and the input data and the output data of the S-box lookup table which is subjected to mask processing are both covered by masks; the DSP implementation SM4 mask of the application is resistant to power consumption, is safe and efficient, and has better hardware adaptability.

The invention relates to the technical field of cryptographic analysis, and discloses an ARX type cryptographic algorithm differential path analysis method and system based on differential propagation, and the method comprises the following steps: constructing a round function of a cryptographic algorithm, configuring differential analysis parameters, and selecting a differential path search strategy. Comprising a multi-differential path automatic mining strategy, a differential aggregation analysis strategy and a search strategy with conditional constraints; converting the round function and the differential analysis parameters into intermediate description data; analyzing the intermediate description data, and extracting structure information of each basic operation unit in the round function; generating a differential analysis constraint; executing a differential path search; submitting the differential analysis constraint to a constraint solver for solving to obtain a differential path result; according to the method, the difference path result is analyzed, and the difference path and the aggregation analysis result are displayed, based on the method, a visual software system is constructed, and convenience and automation of difference analysis are achieved through visual modeling, automatic constraint generation and solver calling.

The invention discloses an impossible difference divider search method for an SKINNY128 algorithm, and the method combines difference set propagation with a Boolean satisfiability problem (SAT) modeling technology, and integrates a miss-in-the-middle idea. The method comprises the following steps of: firstly, simulating propagation of a differential set in a SKINNY128 round function with a probability 1 from the encryption direction and the decryption direction respectively, and recording all possible propagation modes; then, constructing a bit-oriented SAT constraint model based on a propagation mode; then, constraints are established for possible contradiction points in the middle round; and finally, searching an effective impossible differential divider by solving the SAT model, and taking the condition that the model has a solution as a judgment condition. According to the method, the defects that in the prior art, contradictory points cannot be positioned, and indirect contradictions cannot be processed are overcome, and an impossible difference divider with a longer round number of an SKINNY128 algorithm can be automatically and more comprehensively searched.

The application discloses a 16-bit S-box construction method and device based on a MISTY structure, and belongs to the field of information security. The method is characterized in that four 8-bit S-boxes are selected, and four rounds of iteration calculation are performed on high and low 8-bit data by using a MISTY type round function structure. In the method, S-box substitution, modulo addition mixing and data exchange are sequentially performed on the high 8-bit data in each of the first three rounds; and S-box substitution and modulo addition mixing are performed in the fourth round, and then the result is directly output. Finally, the result is spliced into 16-bit output. The application further provides a hardware device for implementing the method. The method utilizes the regularity of the MISTY structure, is easy to implement by using a hardware pipeline, and enhances nonlinearity by using modulo addition operation. The 16-bit S-box constructed by using the method is excellent in cryptographic properties such as differential uniformity, nonlinearity and algebraic degree, and a good balance between security and implementation efficiency is achieved.

This invention discloses an AES quantum circuit area optimization method and system based on reversible logic, relating to the field of quantum circuit area optimization technology. The method includes quantum resource budget mapping, reversible reconstruction compression, normalized reversible folding based on the budget vector, outputting a gate-level description vector, and simultaneously writing back the actual consumed auxiliary bits to S1 to form a closed-loop calibration; Grover verification feedback recompression, real-time acquisition of performance vectors; circuit output, completing area-depth collaborative optimization; by mapping the full-round function of the advanced cryptographic algorithm to a dual-graph structure composed of qubits and quantum gates, and dividing the overall node set into several local subgraphs according to the coupling topology of the target chip, the peak value of qubits, the quota of auxiliary bits, and the number of cross-layer edges are simultaneously included in the weight model during the resource budget stage, ensuring that subsequent circuits are within the area-constrained envelope from the starting point, avoiding the repeated dismantling caused by traditional pre-construction and post-compression, thereby significantly reducing the redundancy of the initial layout.

The application discloses an implementation method of a high-diffusion lightweight block cipher (HDLBC), which comprises the following steps: obtaining plaintext or ciphertext as to-be-encrypted / decrypted data; performing R-round encryption / decryption operation on the to-be-encrypted / decrypted data; each round of encryption operation is to perform RA1 function operation, branch XOR operation, RA2 function operation and P permutation on the to-be-encrypted data; in each round of encryption operation, part of bits in a sub-key participates in round key addition operation in the RA1 function operation; the remaining bits participate in round key addition operation in the RA2 function operation; the decryption operation is performed in the reverse order of the encryption operation, and the order of the sub-key used in the R-round decryption operation is opposite to the order of the sub-key used in the R-round encryption operation. The method designed in the application is an F function based on NAND operation and designed to introduce two F functions to realize round functions affecting all branches, so that the diffusion and area consumption of the algorithm are better ensured.

The invention discloses an automatic key guessing path searching method for an LLLWBC cryptographic algorithm, and belongs to the technical field of information security. Aiming at the problem that a key guessing path depends on manual analysis in an integral attack key recovery stage of the LLLWBC block cipher, and optimality is difficult to guarantee, the method comprises the following steps of: uniformly modeling certainty of an intermediate status word and guessing requirements of a round key in a decryption process into binary variables based on an integral discriminator; according to an LLLWBC round function and a key arrangement structure, a state and key dependence constraint is established, a mixed integer linear optimization model is constructed by taking minimization of a key bit number needing guessing as a target, and an optimal key guessing path is obtained through automatic solving. And executing partial decryption based on the optimal path and realizing key recovery by utilizing integral balance judgment. According to the method, the key recovery complexity is remarkably reduced, and the automation degree and the analysis efficiency of integral attacks are improved.

The application discloses a kind of password period evaluation method and device based on SH structure.Method includes: obtaining the password algorithm to be evaluated;The input of password algorithm is converted into plaintext mode and the structural model of the password algorithm is constructed;The plaintext mode is input into the structural model of password algorithm, and the round function iteration operation is carried out, to obtain the round number of the periodic function of the password algorithm, independent variable, parameter and output variable;Periodic function is constructed, the correctness of the constructed periodic function is verified, and in the case of being correct, whether the round number of periodic function is greater than half of the full round of the password algorithm to be evaluated is judged, if it is satisfied, the evaluation result of the password algorithm to be evaluated is safe under quantum model;If not satisfied, the evaluation result of the password algorithm to be evaluated is unsafe under quantum model.The design method of the application is simple, easy to implement on hardware and software platform, and has the advantages of high efficiency.

The application discloses a kind of SM4 fast software implementation methods based on AES- NI instruction set, this method includes: based on AVX2 (Advanced Vector Extensions) instruction set and AES- NI (Advanced Encryption Standard New Instructions) instruction set, SM4 algorithm is optimized, realizes 8 groups of plaintext parallel encryption, by finding the isomorphism between finite field, S box in SM4 algorithm is mapped to the S box of AES algorithm, and the S box operation of SM4 algorithm is completed using AES- NI extension instruction;In algorithm implementation, the shuffle instruction in AVX2 instruction set is used to improve the matrix operation efficiency in round function.

The application discloses an ARX lightweight block encryption method and system based on pseudo-random dynamic round number, relates to the technical field of cryptography and information security, and comprises the following steps: step 1, dividing to-be-encrypted data into n to-be-encrypted data blocks; step 2, obtaining a basic round number and a master key, and calculating r and rd; step 3, generating an initial round key based on the master key, introducing a temporary variable, and generating a round key by using a round function algorithm; step 4, inputting the n to-be-encrypted data blocks into n branches of an encryption round function, generating an initial to-be-encrypted data block, performing exclusive OR operation on the initial to-be-encrypted data block and the round key, performing exclusive OR operation on the initial to-be-encrypted data block and a corresponding to-be-encrypted data block to obtain an intermediate variable, and performing modulo addition on the intermediate variable after cyclic bit shift and the exclusive OR result; and step 5, iteratively calculating step 4, and outputting ciphertext. The application realizes lightweight design, meanwhile, maintains efficient encryption / decryption speed, and can flexibly adapt to various application scenarios.

This application provides a method, apparatus, device, and medium for dynamically adjustable block cipher algorithm structures, relating to the field of information security. The method includes: inputting a master key, master control parameters, and plaintext to be encrypted; iteratively executing 32 rounds of encryption operations using the master key and master control parameters on the plaintext until 128 bits of ciphertext are obtained. This application achieves dynamic adjustability of the cryptographic algorithm structure by adding parameter control, allowing for the generation of round functions with different structures through parameter adjustment, while simultaneously ensuring the algorithm's resistance to differential attacks. This enriches the diversity of block cipher algorithm structures and improves the algorithm's security.